From 1f318a2a0e993dd655cac123aa36ac4a7854ac6d Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Sat, 24 Apr 2021 01:18:34 +0200 Subject: [PATCH] 6502: Optimize sign extension --- .../assembly/mos/opt/LaterOptimizations.scala | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala index 7d42e412..dece238b 100644 --- a/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala +++ b/src/main/scala/millfork/assembly/mos/opt/LaterOptimizations.scala @@ -509,6 +509,30 @@ object LaterOptimizations { (Elidable & HasOpcodeIn(ADC, ORA, EOR, AND) & HasAddrModeIn(Absolute, LongAbsolute, ZeroPage) & MatchParameter(1)) ~~> { (code, ctx) => ctx.get[List[AssemblyLine]](4) ++ ctx.get[List[AssemblyLine]](5) ++ ctx.get[List[AssemblyLine]](66).map(_.copy(opcode = code.last.opcode)) }, + + (Elidable & HasOpcode(LDA) & HasClear(State.D)) ~ + (Elidable & HasOpcode(ORA) & HasImmediate(0x7f)) ~ + (Elidable & HasOpcode(BMI) & MatchParameter(0)) ~ + (Elidable & HasOpcode(LDA) & HasImmediate(0)) ~ + (Elidable & IsNotALabelUsedManyTimes & HasOpcode(LABEL) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) => + List(AssemblyLine.immediate(LDA, 0x7f), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7f)) + }, + + (Elidable & HasOpcode(LDA) & HasClear(State.D) & HasY(0)) ~ + (Elidable & HasOpcode(ORA) & HasImmediate(0x7f)) ~ + (Elidable & HasOpcode(BMI) & MatchParameter(0)) ~ + (Elidable & HasOpcode(TYA) & HasY(0)) ~ + (Elidable & IsNotALabelUsedManyTimes & HasOpcode(LABEL) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) => + List(AssemblyLine.immediate(LDA, 0x7f), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7f)) + }, + + (Elidable & HasOpcode(LDA) & HasClear(State.D) & HasX(0)) ~ + (Elidable & HasOpcode(ORA) & HasImmediate(0x7f)) ~ + (Elidable & HasOpcode(BMI) & MatchParameter(0)) ~ + (Elidable & HasOpcode(TXA) & HasX(0)) ~ + (Elidable & IsNotALabelUsedManyTimes & HasOpcode(LABEL) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) => + List(AssemblyLine.immediate(LDA, 0x7f), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7f)) + }, ) val DontUseIndexRegisters = new RuleBasedAssemblyOptimization("Don't use index registers unnecessarily",