6502/millfork
1
0
Fork 0
mirror of https://github.com/KarolS/millfork.git synced 2025-01-01 06:29:53 +00:00
Code Issues Projects Releases Wiki Activity

8080: optimize more pointless loads

Browse Source
This commit is contained in:
Karol Stasiak 2019-06-24 15:17:05 +02:00
parent 4dd470141a
commit 23b4b110a6
3 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
View File

@ -292,6 +292,10 @@ object AlwaysGoodI80Optimizations {
ctx.get[List[ZLine]](2) :+ ZLine.register(DEC_16, HL)
},
// 67
(HasOpcode(LD) & MatchSourceRealRegister(0) & MatchTargetRealRegister(1)) ~
(Linear & Not(ChangesMatchedRegister(0)) & Not(ChangesMatchedRegister(1))).* ~
(Elidable & HasOpcode(LD) & MatchSourceRealRegister(1) & MatchTargetRealRegister(0)) ~~> (_.init),
)
val PointlessStackStashing = new RuleBasedAssemblyOptimization("Pointless stack stashing",

27
src/main/scala/millfork/assembly/z80/opt/RuleBasedAssemblyOptimization.scala
View File

@ -573,6 +573,26 @@ case class MatchTargetRegisterAndOffset(i: Int) extends AssemblyLinePattern {
override def hitRate: Double = 0.879
}
case class MatchSourceRealRegister(i: Int) extends AssemblyLinePattern {
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean =
line.registers match {
case TwoRegisters(_, s) if ZRegister.main7Registers(s) => ctx.addObject(i, s)
case _ => false
}
override def hitRate: Double = 0.931
}
case class MatchTargetRealRegister(i: Int) extends AssemblyLinePattern {
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean =
line.registers match {
case TwoRegisters(t, _) if ZRegister.main7Registers(t) => ctx.addObject(i, t)
case _ => false
}
override def hitRate: Double = 0.879
}
case class MatchSoleRegisterAndOffset(i: Int) extends AssemblyLinePattern {
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean =
line.registers match {
@ -924,6 +944,13 @@ case class Changes(register: ZRegister.Value) extends TrivialAssemblyLinePattern
override def hitRate: Double = 0.212
}
case class ChangesMatchedRegister(register: Int) extends AssemblyLinePattern {
override def hitRate: Double = 0.212 // ?
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean = line.changesRegister(ctx.get[ZRegister.Value](register))
}
case class Concerns(register: ZRegister.Value) extends TrivialAssemblyLinePattern {
override def apply(line: ZLine): Boolean = line.readsRegister(register) || line.changesRegister(register)

2
src/main/scala/millfork/node/Node.scala
View File

@ -174,6 +174,8 @@ object ZRegister extends Enumeration {
case 1 => MEM_ABS_8
case 2 => MEM_ABS_16
}
val main7Registers: Set[ZRegister.Value] = Set[ZRegister.Value](ZRegister.A, ZRegister.B, ZRegister.C, ZRegister.D, ZRegister.D, ZRegister.E, ZRegister.H, ZRegister.L)
}
//case class Indexing(child: Expression, register: Register.Value) extends Expression