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6809: Correctly assemble STS and STY

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Karol Stasiak 2020-07-31 13:25:42 +02:00
parent cad6f27185
commit 33d67ec932
1 changed files with 1 additions and 1 deletions
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src/main/scala/millfork/assembly/m6809/MOpcode.scala
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@ -37,7 +37,7 @@ object MOpcode extends Enumeration {
values.filterNot(notActualOpcodes).map(o => o.toString -> o).toMap ++ Map("BHS" -> BCC, "BLO" -> BCS, "LSL" -> ASL) values.filterNot(notActualOpcodes).map(o => o.toString -> o).toMap ++ Map("BHS" -> BCC, "BLO" -> BCS, "LSL" -> ASL)
} }
val NoopDiscard: Set[MOpcode.Value] = Set(DISCARD_D, DISCARD_X, DISCARD_Y, DISCARD_CC) val NoopDiscard: Set[MOpcode.Value] = Set(DISCARD_D, DISCARD_X, DISCARD_Y, DISCARD_CC)
val PrefixedBy10: Set[MOpcode.Value] = Set(CMPD, CMPY, LDS, LDY, SWI2) // TODO: branches val PrefixedBy10: Set[MOpcode.Value] = Set(CMPD, CMPY, LDS, LDY, SWI2, STS, STY) // TODO: branches
val PrefixedBy11: Set[MOpcode.Value] = Set(CMPS, CMPU, SWI3) val PrefixedBy11: Set[MOpcode.Value] = Set(CMPS, CMPU, SWI3)
val Prefixed: Set[MOpcode.Value] = PrefixedBy10 ++ PrefixedBy11 val Prefixed: Set[MOpcode.Value] = PrefixedBy10 ++ PrefixedBy11
val CanHaveInherentAccumulator: Set[MOpcode.Value] = Set(ASL, ASR, CLR, COM, DEC, INC, LSR, NEG, ROL, ROR, TST) val CanHaveInherentAccumulator: Set[MOpcode.Value] = Set(ASL, ASR, CLR, COM, DEC, INC, LSR, NEG, ROL, ROR, TST)