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6809: fix indirect addressing mode

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This commit is contained in:
Karol Stasiak 2020-07-13 22:10:04 +02:00
parent a22571f60b
commit 350c5d2d5d
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/millfork/output/M6809Assembler.scala
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@ -145,8 +145,9 @@ class M6809Assembler(program: Program,
index + 3
case MLine0(op, Absolute(true), param) if M6809Assembler.indexable.contains(op) =>
writeByte(bank, index, M6809Assembler.standard(op) + 0x20)
writeByte(bank, index + 1, 0x9f)
writeWord(bank, index + 2, param)
index + 3
index + 4
case MLine0(op, Indexed(M6809Register.PC, indirect), param) if M6809Assembler.indexable.contains(op) =>
???
case MLine0(op, Indexed(register, indirect), param) if M6809Assembler.indexable.contains(op) =>