From 53f550d2663d3b0d87fa7a803bfdae87d467cf0e Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Tue, 31 Jul 2018 00:52:01 +0200
Subject: [PATCH] Z80: Fix line size calculations

---
 .../scala/millfork/assembly/z80/ZLine.scala   |  9 ++--
 .../scala/millfork/test/ZLineSizeSuite.scala  | 54 +++++++++++++++++++
 2 files changed, 60 insertions(+), 3 deletions(-)
 create mode 100644 src/test/scala/millfork/test/ZLineSizeSuite.scala

diff --git a/src/main/scala/millfork/assembly/z80/ZLine.scala b/src/main/scala/millfork/assembly/z80/ZLine.scala
index bf009276..cabc9e20 100644
--- a/src/main/scala/millfork/assembly/z80/ZLine.scala
+++ b/src/main/scala/millfork/assembly/z80/ZLine.scala
@@ -175,7 +175,7 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
       case BYTE => 1
       case d if ZOpcodeClasses.NoopDiscards(d) => 0
       case JP => registers match {
-        case OneRegister(HL | IX | IY) => 0
+        case OneRegister(HL | IX | IY) => 1
         case _ => 2
       }
       case JR => 2
@@ -185,11 +185,14 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
     }
     val fromParams = registers match {
       case OneRegister(IX | IXL | IXH | IY | IYH | IYL | IMM_8) => 1
-      case OneRegister(MEM_IX_D | MEM_IY_D | IMM_16 | MEM_ABS_8 | MEM_ABS_16) => 2
+      case OneRegister(IMM_16 | MEM_ABS_8 | MEM_ABS_16) => 2
+      case OneRegisterOffset(MEM_IX_D | MEM_IY_D, _) => 2
       case TwoRegisters(_, IX | IXL | IXH | IY | IYH | IYL | IMM_8) => 1
       case TwoRegisters(_, MEM_IX_D | MEM_IY_D | IMM_16 | MEM_ABS_8 | MEM_ABS_16) => 2
+      case TwoRegistersOffset(_, MEM_IX_D | MEM_IY_D, _) => 2
       case TwoRegisters(IX | IXL | IXH | IY | IYH | IYL | IMM_8, _) => 1
-      case TwoRegisters(MEM_IX_D | MEM_IY_D | IMM_16 | MEM_ABS_8 | MEM_ABS_16, _) => 2
+      case TwoRegisters(IMM_16 | MEM_ABS_8 | MEM_ABS_16, _) => 2
+      case TwoRegistersOffset(MEM_IX_D | MEM_IY_D, _, _) => 2
       case _ => 0
     }
     inherent + fromParams
diff --git a/src/test/scala/millfork/test/ZLineSizeSuite.scala b/src/test/scala/millfork/test/ZLineSizeSuite.scala
new file mode 100644
index 00000000..30c657cf
--- /dev/null
+++ b/src/test/scala/millfork/test/ZLineSizeSuite.scala
@@ -0,0 +1,54 @@
+package millfork.test
+
+import millfork.{CompilationOptions, Cpu, CpuFamily}
+import millfork.assembly.z80.{LocalVariableAddressViaIX, NoRegisters, ZLine}
+import millfork.env.{Constant, Environment, NumericConstant}
+import millfork.output.Z80Assembler
+import millfork.test.emu._
+import org.scalatest.{FunSuite, Matchers}
+
+
+/**
+  * @author Karol Stasiak
+  */
+class ZLineSizeSuite extends FunSuite with Matchers {
+  private def runCase(line: ZLine): Unit = {
+    val platform = EmuPlatform.get(Cpu.Z80)
+    val env = new Environment(None, "", CpuFamily.I80, TestErrorReporting.log)
+    val options = CompilationOptions(platform, Map(), None, 0, TestErrorReporting.log)
+    val correctSize = new Z80Assembler(null, env, platform).emitInstruction("default", options, 0x100, line) - 0x100
+    val guessedSize = line.sizeInBytes
+    guessedSize should equal(correctSize)
+  }
+
+  test("Z80 instruction size") {
+    import millfork.assembly.z80.ZOpcode._
+    import millfork.node.ZRegister._
+    import millfork.env.Constant.Zero
+    runCase(ZLine.implied(RET))
+    runCase(ZLine.implied(NEG))
+    runCase(ZLine.implied(RETI))
+    runCase(ZLine.implied(RETN))
+    runCase(ZLine.implied(EX_DE_HL))
+    runCase(ZLine.implied(HALT))
+    runCase(ZLine.ldViaIx(0, A))
+    runCase(ZLine.ld8(B, C))
+    runCase(ZLine.ldImm8(B, 9))
+    runCase(ZLine.ldAbs8(A, Zero))
+    runCase(ZLine.ldAbs16(HL, Zero))
+    runCase(ZLine.ldImm16(HL, Zero))
+    runCase(ZLine.register(SLA, E))
+    runCase(ZLine.register(BIT0, E))
+    runCase(ZLine.register(JP, IX))
+    runCase(ZLine.register(JP, HL))
+    runCase(ZLine(IM, NoRegisters, NumericConstant(1, 1), true))
+    runCase(ZLine.register(DEC, HL))
+    runCase(ZLine.register(DEC, LocalVariableAddressViaIX(7)))
+    runCase(ZLine.ld8(A, MEM_HL))
+    runCase(ZLine.ld8(A, MEM_BC))
+    runCase(ZLine.ld8(A, MEM_DE))
+    runCase(ZLine.ld8(MEM_HL, A))
+    runCase(ZLine.ld8(MEM_BC, A))
+    runCase(ZLine.ld8(MEM_DE, A))
+  }
+}