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Z80: Optimization improvements and fixes
This commit is contained in:
Karol Stasiak
parent
80aef5c412
commit
55e9fd5174
@ -198,7 +198,12 @@ object AlwaysGoodZ80Optimizations {
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}
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}
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},
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// 55-59
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for5LargeRegisters(register =>
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(Is16BitLoad(register, ZRegister.MEM_ABS_16) & MatchParameter(0)).captureLine(1) ~
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(Linear & Not(Changes(register)) & DoesntChangeMemoryAt(1)).* ~
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(Elidable & Is16BitLoad(register, ZRegister.MEM_ABS_16) & MatchParameter(0)) ~~> (_.init)
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),
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)
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val PointlessStackStashing = new RuleBasedAssemblyOptimization("Pointless stack stashing",
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@ -206,45 +211,54 @@ object AlwaysGoodZ80Optimizations {
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// 0-4
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for5LargeRegisters(register => {
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(register)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(register))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(register))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(register)) ~~> (_.tail.init)
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}),
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// 5
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(ZRegister.DE) & DoesntMatterWhatItDoesWith(ZRegister.D)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(ZRegister.D))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(ZRegister.D))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(ZRegister.DE)) ~~> {code =>
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ZLine.ld8(ZRegister.D, ZRegister.E) :: (code.tail.init :+ ZLine.ld8(ZRegister.E, ZRegister.D))
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},
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// 6
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(ZRegister.DE) & DoesntMatterWhatItDoesWith(ZRegister.E)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(ZRegister.E))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(ZRegister.E))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(ZRegister.DE)) ~~> { code =>
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ZLine.ld8(ZRegister.E, ZRegister.D) :: (code.tail.init :+ ZLine.ld8(ZRegister.D, ZRegister.E))
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},
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// 7
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(ZRegister.BC) & DoesntMatterWhatItDoesWith(ZRegister.B)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(ZRegister.B))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(ZRegister.B))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(ZRegister.BC)) ~~> (code =>
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ZLine.ld8(ZRegister.B, ZRegister.C) :: (code.tail.init :+ ZLine.ld8(ZRegister.C, ZRegister.B))
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),
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// 8
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(ZRegister.BC) & DoesntMatterWhatItDoesWith(ZRegister.C)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(ZRegister.C))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(ZRegister.C))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(ZRegister.BC)) ~~> { code =>
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ZLine.ld8(ZRegister.C, ZRegister.B) :: (code.tail.init :+ ZLine.ld8(ZRegister.B, ZRegister.C))
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},
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// 9
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(ZRegister.HL) & DoesntMatterWhatItDoesWith(ZRegister.H)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(ZRegister.H))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(ZRegister.H))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(ZRegister.HL)) ~~> { code =>
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ZLine.ld8(ZRegister.H, ZRegister.L) :: (code.tail.init :+ ZLine.ld8(ZRegister.L, ZRegister.H))
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},
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// 10
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(ZRegister.HL) & DoesntMatterWhatItDoesWith(ZRegister.L)) ~
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(Linear & Not(HasOpcode(POP)) & Not(Changes(ZRegister.L))).* ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH))) & Not(Changes(ZRegister.L)) ).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(ZRegister.HL)) ~~> { code =>
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ZLine.ld8(ZRegister.L, ZRegister.H) :: (code.tail.init :+ ZLine.ld8(ZRegister.H, ZRegister.L))
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},
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// 11-15
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for5LargeRegisters(register => {
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(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(register, ZRegister.IMM_16))) ~
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(Elidable & HasOpcode(PUSH) & HasRegisterParam(register) & DoesntMatterWhatItDoesWith(register)) ~
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(Linear & Not(HasOpcodeIn(Set(POP,PUSH)))).* ~
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(Elidable & HasOpcode(POP) & HasRegisterParam(register)) ~~> { code =>
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code.drop(2).init :+ code.head
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}
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}),
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)
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@ -415,7 +429,34 @@ object AlwaysGoodZ80Optimizations {
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(Is8BitLoadTo(ZRegister.A) | HasOpcode(LD) & HasRegisters(TwoRegisters(ZRegister.A, ZRegister.MEM_ABS_8))) ~
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(Elidable & HasOpcode(SBC)) ~~> { code =>
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List(code(2), code(3).copy(opcode = SUB))
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}
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},
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(Elidable & HasOpcode(DEC) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~
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(Elidable & Linear & DoesntConcernMatchedRegisterAndOffset(0)).* ~
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(Elidable & HasOpcode(INC) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_.tail.init),
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(Elidable & HasOpcode(INC) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~
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(Elidable & Linear & DoesntConcernMatchedRegisterAndOffset(0)).* ~
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(Elidable & HasOpcode(DEC) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_.tail.init),
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(Elidable & HasOpcode(DEC_16) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~
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(Elidable & Linear & DoesntConcernMatchedRegisterAndOffset(0)).* ~
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(Elidable & HasOpcode(INC_16) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_.tail.init),
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(Elidable & HasOpcode(INC_16) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~
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(Elidable & Linear & DoesntConcernMatchedRegisterAndOffset(0)).* ~
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(Elidable & HasOpcode(DEC_16) & MatchSoleRegisterAndOffset(0) & DoesntMatterWhatItDoesWithFlags) ~~> (_.tail.init),
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(Elidable & Is8BitLoad(ZRegister.D, ZRegister.B)) ~
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(Elidable & Is8BitLoad(ZRegister.E, ZRegister.C)) ~
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(Elidable & HasOpcode(ADD_16) & HasRegisters(TwoRegisters(ZRegister.HL, ZRegister.DE))) ~~> { code =>
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ZLine.registers(code.last.opcode, ZRegister.HL, ZRegister.BC) :: code.take(2)
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},
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(Elidable & Is8BitLoad(ZRegister.B, ZRegister.D)) ~
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(Elidable & Is8BitLoad(ZRegister.C, ZRegister.E)) ~
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(Elidable & HasOpcode(ADD_16) & HasRegisters(TwoRegisters(ZRegister.HL, ZRegister.BC))) ~~> { code =>
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ZLine.registers(code.last.opcode, ZRegister.HL, ZRegister.DE) :: code.take(2)
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},
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)
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@ -522,6 +563,50 @@ object AlwaysGoodZ80Optimizations {
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ZLine.ld8(ZRegister.E, ZRegister.C),
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code(2).copy(registers = OneRegister(ZRegister.DE))
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)),
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// 2 bytes more, but 3 cycles fewer and frees BC
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(Elidable & Is16BitLoad(ZRegister.BC, ZRegister.IMM_16) & MatchParameter(0)) ~
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(Linear & Not(Concerns(ZRegister.BC)) & Not(Concerns(ZRegister.HL))).*.capture(1) ~
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(Elidable & Is8BitLoad(ZRegister.L, ZRegister.A)) ~
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(Elidable & Is8BitLoadTo(ZRegister.H) & Has8BitImmediate(0)) ~
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(Elidable & HasOpcode(ADD_16) & HasRegisters(TwoRegisters(ZRegister.HL, ZRegister.BC)) &
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DoesntMatterWhatItDoesWithFlagsExceptCarry &
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DoesntMatterWhatItDoesWith(ZRegister.BC)) ~~> { (code, ctx) =>
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val offset = ctx.get[Constant](0)
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ctx.get[List[ZLine]](1) ++ List(
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ZLine.imm8(ADD, offset.loByte),
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ZLine.ld8(ZRegister.L, ZRegister.A),
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ZLine.ldImm8(ZRegister.A, 0),
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ZLine.imm8(ADC, offset.hiByte),
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ZLine.ld8(ZRegister.H, ZRegister.A))
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},
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(Elidable & Is8BitLoad(ZRegister.H, ZRegister.B)) ~
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(Elidable & Is8BitLoad(ZRegister.L, ZRegister.C)) ~
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(Elidable & Is8BitLoad(ZRegister.MEM_HL, ZRegister.A) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> {_ =>
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List(ZLine.ld8(ZRegister.MEM_BC, ZRegister.A))
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},
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(Elidable & Is8BitLoad(ZRegister.H, ZRegister.D)) ~
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(Elidable & Is8BitLoad(ZRegister.L, ZRegister.E)) ~
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(Elidable & Is8BitLoad(ZRegister.MEM_HL, ZRegister.A) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> {_ =>
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List(ZLine.ld8(ZRegister.MEM_DE, ZRegister.A))
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},
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(Elidable & Is8BitLoad(ZRegister.H, ZRegister.B)) ~
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(Elidable & Is8BitLoad(ZRegister.L, ZRegister.C)) ~
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(Elidable & Is8BitLoad(ZRegister.A, ZRegister.MEM_HL) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> {_ =>
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List(ZLine.ld8(ZRegister.A, ZRegister.MEM_BC))
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},
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(Elidable & Is8BitLoad(ZRegister.H, ZRegister.D)) ~
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(Elidable & Is8BitLoad(ZRegister.L, ZRegister.E)) ~
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(Elidable & Is8BitLoad(ZRegister.A, ZRegister.MEM_HL) & DoesntMatterWhatItDoesWith(ZRegister.HL)) ~~> {_ =>
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List(ZLine.ld8(ZRegister.A, ZRegister.MEM_DE))
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},
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)
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val UnusedCodeRemoval = new RuleBasedAssemblyOptimization("Unreachable code removal",
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@ -541,6 +626,76 @@ object AlwaysGoodZ80Optimizations {
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(HasOpcode(LABEL) & MatchJumpTarget(0)) ~~> (c => c.last :: Nil),
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)
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val SimplifiableShifting = new RuleBasedAssemblyOptimization("Simplifiable shifting",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A) & DoesntMatterWhatItDoesWithFlags) ~~> { _ =>
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List(
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ZLine.register(RRC, ZRegister.A),
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ZLine.imm8(AND, 0x80))
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},
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A) & DoesntMatterWhatItDoesWithFlags) ~~> { _ =>
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List(
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ZLine.register(RRC, ZRegister.A),
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ZLine.register(RRC, ZRegister.A),
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ZLine.imm8(AND, 0xc0))
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},
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SLA) & HasRegisterParam(ZRegister.A) & DoesntMatterWhatItDoesWithFlags) ~~> { _ =>
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List(
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ZLine.register(RRC, ZRegister.A),
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ZLine.register(RRC, ZRegister.A),
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ZLine.register(RRC, ZRegister.A),
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ZLine.imm8(AND, 0xe0))
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},
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A) & DoesntMatterWhatItDoesWithFlags) ~~> { _ =>
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List(
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ZLine.register(RLC, ZRegister.A),
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ZLine.imm8(AND, 1))
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},
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A) & DoesntMatterWhatItDoesWithFlags) ~~> { _ =>
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List(
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ZLine.register(RLC, ZRegister.A),
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ZLine.register(RLC, ZRegister.A),
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ZLine.imm8(AND, 3))
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},
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A)) ~
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(Elidable & HasOpcode(SRL) & HasRegisterParam(ZRegister.A) & DoesntMatterWhatItDoesWithFlags) ~~> { _ =>
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List(
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ZLine.register(RLC, ZRegister.A),
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ZLine.register(RLC, ZRegister.A),
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ZLine.register(RLC, ZRegister.A),
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ZLine.imm8(AND, 7))
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},
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)
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val All: List[AssemblyOptimization[ZLine]] = List[AssemblyOptimization[ZLine]](
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BranchInPlaceRemoval,
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FreeHL,
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@ -548,6 +703,7 @@ object AlwaysGoodZ80Optimizations {
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PointlessStackStashing,
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ReloadingKnownValueFromMemory,
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SimplifiableMaths,
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SimplifiableShifting,
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UnusedCodeRemoval,
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UnusedLabelRemoval,
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UsingKnownValueFromAnotherRegister,
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@ -119,7 +119,7 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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var done = false
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bestHLs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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ErrorReporting.debug(s"Inlining $v to register HL")
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ErrorReporting.debug(s"Inlining $v to register pair HL")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars(v, "", "", oldCode.map(_._2))
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reportOptimizedBlock(oldCode, newCode)
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@ -133,7 +133,7 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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if (!done) {
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bestBCs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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ErrorReporting.debug(s"Inlining $v to register BC")
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ErrorReporting.debug(s"Inlining $v to register pair BC")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars("", v, "", oldCode.map(_._2))
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reportOptimizedBlock(oldCode, newCode)
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@ -148,7 +148,7 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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if (!done) {
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bestDEs.find(_._2.start == i).foreach {
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case (v, range, _) =>
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ErrorReporting.debug(s"Inlining $v to register DE")
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ErrorReporting.debug(s"Inlining $v to register pair DE")
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val oldCode = vs.codeWithFlow.slice(range.start, range.end)
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val newCode = inlineVars("", "", v, oldCode.map(_._2))
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reportOptimizedBlock(oldCode, newCode)
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@ -190,6 +190,16 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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}
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code match {
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case (_, ZLine(LD_16, TwoRegisters(BC, IMM_16), _, true))::
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(i, ZLine(ADD_16, TwoRegisters(HL, BC), _, true)) :: xs if target == BC =>
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if (i.importanceAfter.getRegister(BC) == Important || i.importanceAfter.getRegister(DE) == Important) fail(22)
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else canBeInlined(vname, synced = true, target, xs)
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case (_, ZLine(LD_16, TwoRegisters(DE, IMM_16), _, true))::
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(i, ZLine(ADD_16, TwoRegisters(HL, DE), _, true)) :: xs if target == DE =>
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if (i.importanceAfter.getRegister(BC) == Important || i.importanceAfter.getRegister(DE) == Important) fail(23)
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else canBeInlined(vname, synced = true, target, xs)
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th1), true)) ::
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(_, ZLine(ADD_16, TwoRegisters(HL, BC | DE), _, _)) ::
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(i, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th2), true)) ::
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@ -222,13 +232,15 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), true)) ::
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(_, ZLine(LD_16, TwoRegisters(t, _), _, true)) ::
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(i, ZLine(ADD_16, TwoRegisters(HL, t2), _, _)) ::
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xs if t != HL && t == t2 && i.importanceAfter.getRegister(t) == Unimportant =>
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xs if th.name == vname && t != HL && t == t2 && i.importanceAfter.getRegister(t) == Unimportant =>
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// LD (vv),HL ; LD QQ,__ ; ADD HL,QQ (vv@QQ)→ LD QQ,HL ; LD HL,__, ADD HL,QQ
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canBeInlined(vname, synced = true, target, xs).map(add(target == t, CyclesAndBytes(16, 3), CyclesAndBytes(8, 1)))
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case (_, ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), true)) ::
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(_, ZLine(LD_16, TwoRegisters(t, _), _, true)) ::
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(i, ZLine(ADD_16, TwoRegisters(HL, t2), _, _)) ::
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xs if t == target && t != HL && t == t2 && i.importanceAfter.getRegister(t) == Unimportant =>
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xs if t == target && th.name == vname && t != HL && t == t2 && i.importanceAfter.getRegister(t) == Unimportant =>
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// LD (vv),HL ; LD QQ,__ ; ADD HL,QQ (vv@QQ)→ LD QQ,HL ; LD PP,__, ADD HL,PP
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canBeInlined(vname, synced = true, target, xs).map(add(CyclesAndBytes(16, 3)))
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case (_, ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), MemoryAddressConstant(th), true)) :: xs if th.name == vname =>
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@ -275,9 +287,23 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
|
||||
if (code.nonEmpty) println(code.head)
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code match {
|
||||
|
||||
case ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), a1@MemoryAddressConstant(th1), true) ::
|
||||
case (load@ZLine(LD_16, TwoRegisters(BC, IMM_16), _, _)) ::
|
||||
ZLine(ADD_16, TwoRegisters(HL, BC), _, _) ::
|
||||
xs if bc != "" =>
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||||
load.copy(registers = TwoRegisters(DE, IMM_16)) ::
|
||||
ZLine.registers(ADD_16, HL, DE) ::
|
||||
inlineVars(hl, bc, de, xs)
|
||||
|
||||
case (load@ZLine(LD_16, TwoRegisters(DE, IMM_16), _, _)) ::
|
||||
ZLine(ADD_16, TwoRegisters(HL, DE), _, _) ::
|
||||
xs if de != "" =>
|
||||
load.copy(registers = TwoRegisters(BC, IMM_16)) ::
|
||||
ZLine.registers(ADD_16, HL, BC) ::
|
||||
inlineVars(hl, bc, de, xs)
|
||||
|
||||
case ZLine(LD_16, TwoRegisters(HL, MEM_ABS_16), a1@MemoryAddressConstant(th1), _) ::
|
||||
ZLine(ADD_16, TwoRegisters(HL, reg@(DE | BC)), _, _) ::
|
||||
ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), a2@MemoryAddressConstant(th2), true) ::
|
||||
ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), a2@MemoryAddressConstant(th2), _) ::
|
||||
xs if hl != "" && th1.name != hl && th2.name != hl =>
|
||||
// bytes before: 3 + 1 + 3 = 7
|
||||
// cycles before: 16 + 11 + 16 = 43
|
||||
@ -387,6 +413,13 @@ object WordVariableToRegisterOptimization extends AssemblyOptimization[ZLine] {
|
||||
case ZLine(LD, TwoRegisters(MEM_ABS_8, A), CompoundConstant(MathOperator.Plus, MemoryAddressConstant(th), NumericConstant(1,_)), _) :: xs if th.name == de =>
|
||||
ZLine.ld8(D, A) :: inlineVars(hl, bc, de, xs)
|
||||
|
||||
case x :: ZLine(LD_16, TwoRegisters(MEM_ABS_16, HL), MemoryAddressConstant(th), _) :: xs if x.changesRegister(HL) && th.name == hl =>
|
||||
x :: inlineVars(hl, bc, de, xs)
|
||||
case x :: ZLine(LD_16, TwoRegisters(MEM_ABS_16, BC), MemoryAddressConstant(th), _) :: xs if x.changesRegister(BC) && th.name == bc =>
|
||||
x :: inlineVars(hl, bc, de, xs)
|
||||
case x :: ZLine(LD_16, TwoRegisters(MEM_ABS_16, DE), MemoryAddressConstant(th), _) :: xs if x.changesRegister(DE) && th.name == de =>
|
||||
x :: inlineVars(hl, bc, de, xs)
|
||||
|
||||
case x :: _ if bc != "" && x.changesRegister(BC) => ???
|
||||
case x :: _ if de != "" && x.changesRegister(DE) => ???
|
||||
case x :: _ if hl != "" && x.changesRegister(HL) => ???
|
||||
|
||||
Loading…
Reference in New Issue
Block a user