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Fix Z80 shifting

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This commit is contained in:
Karol Stasiak 2018-07-03 01:46:57 +02:00
parent e5ee32f7d6
commit 57bde60ced
3 changed files with 22 additions and 18 deletions
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4
src/main/scala/millfork/compiler/z80/Z80BulkMemoryOperations.scala
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@ -223,8 +223,8 @@ object Z80BulkMemoryOperations {
case "|=" => (ZOpcode.OR, false, None) case "|=" => (ZOpcode.OR, false, None)
case "&=" => (ZOpcode.AND, false, None) case "&=" => (ZOpcode.AND, false, None)
case "^=" => (ZOpcode.XOR, false, None) case "^=" => (ZOpcode.XOR, false, None)
case "<<=" => (ZOpcode.SLA, false, Some(RLC, 0xfe)) case "<<=" => (ZOpcode.SLA, false, Some(RL, 0xfe))
case ">>=" => (ZOpcode.SRL, false, Some(RRC, 0x7f)) case ">>=" => (ZOpcode.SRL, false, Some(RR, 0x7f))
case _ => return None case _ => return None
} }
shift match { shift match {

26
src/main/scala/millfork/compiler/z80/Z80Shifting.scala
View File

@ -29,7 +29,7 @@ object Z80Shifting {
if (extendedOps) { if (extendedOps) {
if (left) ZOpcode.SLA else ZOpcode.SRL if (left) ZOpcode.SLA else ZOpcode.SRL
} else { } else {
if (left) ZOpcode.RLC else ZOpcode.RRC if (left) ZOpcode.RL else ZOpcode.RR
} }
val l = Z80ExpressionCompiler.compileToA(ctx, lhs) val l = Z80ExpressionCompiler.compileToA(ctx, lhs)
env.eval(rhs) match { env.eval(rhs) match {
@ -57,7 +57,7 @@ object Z80Shifting {
if (extendedOps) { if (extendedOps) {
if (left) ZOpcode.SLA else ZOpcode.SRL if (left) ZOpcode.SLA else ZOpcode.SRL
} else { } else {
if (left) ZOpcode.RLC else ZOpcode.RRC if (left) ZOpcode.RL else ZOpcode.RR
} }
env.eval(rhs) match { env.eval(rhs) match {
case Some(NumericConstant(i, _)) => case Some(NumericConstant(i, _)) =>
@ -123,23 +123,23 @@ object Z80Shifting {
if (extendedOps) { if (extendedOps) {
l ++ (0L until i).flatMap(_ => List( l ++ (0L until i).flatMap(_ => List(
ZLine.register(ZOpcode.SRL, ZRegister.H), ZLine.register(ZOpcode.SRL, ZRegister.H),
ZLine.register(ZOpcode.RRC, ZRegister.L) ZLine.register(ZOpcode.RR, ZRegister.L)
)) ))
} else { } else {
l ++ (1L until i).flatMap(_ => List( l ++ (1L until i).flatMap(_ => List(
ZLine.ld8(ZRegister.A, ZRegister.H), ZLine.ld8(ZRegister.A, ZRegister.H),
ZLine.register(ZOpcode.RRC, ZRegister.A), ZLine.register(ZOpcode.RR, ZRegister.A),
ZLine.ld8(ZRegister.H, ZRegister.A), ZLine.ld8(ZRegister.H, ZRegister.A),
ZLine.ld8(ZRegister.A, ZRegister.L), ZLine.ld8(ZRegister.A, ZRegister.L),
ZLine.register(ZOpcode.RRC, ZRegister.A), ZLine.register(ZOpcode.RR, ZRegister.A),
ZLine.ld8(ZRegister.L, ZRegister.A) ZLine.ld8(ZRegister.L, ZRegister.A)
)) ++ List( )) ++ List(
ZLine.ld8(ZRegister.A, ZRegister.H), ZLine.ld8(ZRegister.A, ZRegister.H),
ZLine.register(ZOpcode.RRC, ZRegister.A), ZLine.register(ZOpcode.RR, ZRegister.A),
ZLine.imm8(ZOpcode.AND, (0xff >> i) & 0xff), ZLine.imm8(ZOpcode.AND, (0xff >> i) & 0xff),
ZLine.ld8(ZRegister.H, ZRegister.A), ZLine.ld8(ZRegister.H, ZRegister.A),
ZLine.ld8(ZRegister.A, ZRegister.L), ZLine.ld8(ZRegister.A, ZRegister.L),
ZLine.register(ZOpcode.RRC, ZRegister.A), ZLine.register(ZOpcode.RR, ZRegister.A),
// ZLine.imm8(ZOpcode.AND, (0xff << (i - 8)) & 0xff), // TODO: properly mask the low byte!!! // ZLine.imm8(ZOpcode.AND, (0xff << (i - 8)) & 0xff), // TODO: properly mask the low byte!!!
ZLine.ld8(ZRegister.L, ZRegister.A) ZLine.ld8(ZRegister.L, ZRegister.A)
) )
@ -153,30 +153,30 @@ object Z80Shifting {
if (left) { if (left) {
List( List(
ZLine.register(ZOpcode.SLA, ZRegister.L), ZLine.register(ZOpcode.SLA, ZRegister.L),
ZLine.register(ZOpcode.RLC, ZRegister.H)) ZLine.register(ZOpcode.RL, ZRegister.H))
} else { } else {
List( List(
ZLine.register(ZOpcode.SRL, ZRegister.H), ZLine.register(ZOpcode.SRL, ZRegister.H),
ZLine.register(ZOpcode.RRC, ZRegister.L)) ZLine.register(ZOpcode.RR, ZRegister.L))
} }
} else { } else {
if (left) { if (left) {
List( List(
ZLine.ld8(ZRegister.A, ZRegister.L), ZLine.ld8(ZRegister.A, ZRegister.L),
ZLine.register(ZOpcode.RLC, ZRegister.A), ZLine.register(ZOpcode.RL, ZRegister.A),
ZLine.imm8(ZOpcode.AND, 0xfe), ZLine.imm8(ZOpcode.AND, 0xfe),
ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ld8(ZRegister.L, ZRegister.A),
ZLine.ld8(ZRegister.A, ZRegister.H), ZLine.ld8(ZRegister.A, ZRegister.H),
ZLine.register(ZOpcode.RLC, ZRegister.A), ZLine.register(ZOpcode.RL, ZRegister.A),
ZLine.ld8(ZRegister.H, ZRegister.A)) ZLine.ld8(ZRegister.H, ZRegister.A))
} else { } else {
List( List(
ZLine.ld8(ZRegister.A, ZRegister.H), ZLine.ld8(ZRegister.A, ZRegister.H),
ZLine.register(ZOpcode.RRC, ZRegister.A), ZLine.register(ZOpcode.RR, ZRegister.A),
ZLine.imm8(ZOpcode.AND, 0x7f), ZLine.imm8(ZOpcode.AND, 0x7f),
ZLine.ld8(ZRegister.H, ZRegister.A), ZLine.ld8(ZRegister.H, ZRegister.A),
ZLine.ld8(ZRegister.A, ZRegister.L), ZLine.ld8(ZRegister.A, ZRegister.L),
ZLine.register(ZOpcode.RRC, ZRegister.A), ZLine.register(ZOpcode.RR, ZRegister.A),
ZLine.ld8(ZRegister.L, ZRegister.A)) ZLine.ld8(ZRegister.L, ZRegister.A))
} }
} }

10
src/main/scala/millfork/output/Z80Assembler.scala
View File

@ -73,6 +73,10 @@ class Z80Assembler(program: Program,
case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), param, _) => case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), param, _) =>
writeByte(bank, index, 9 + 16 * internalRegisterIndex(source)) writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
index + 1 index + 1
case ZLine(SBC_16, TwoRegisters(ZRegister.HL, reg), _, _) =>
writeByte(bank, index, 0xed)
writeByte(bank, index + 1, 0x42 + 0x10 * internalRegisterIndex(reg))
index + 2
case ZLine(LD_16, TwoRegisters(target, ZRegister.IMM_16), param, _) => case ZLine(LD_16, TwoRegisters(target, ZRegister.IMM_16), param, _) =>
writeByte(bank, index, 1 + 16 * internalRegisterIndex(target)) writeByte(bank, index, 1 + 16 * internalRegisterIndex(target))
writeWord(bank, index + 1, param) writeWord(bank, index + 1, param)
@ -390,10 +394,10 @@ object Z80Assembler {
oneRegister(POP) = One(0xc1, 0x10) oneRegister(POP) = One(0xc1, 0x10)
oneRegister(PUSH) = One(0xc5, 0x10) oneRegister(PUSH) = One(0xc5, 0x10)
cbOneRegister(RL) = One(0x10, 1)
cbOneRegister(RLC) = One(0, 1) cbOneRegister(RLC) = One(0, 1)
cbOneRegister(RR) = One(8, 1) cbOneRegister(RRC) = One(8, 1)
cbOneRegister(RRC) = One(0x18, 1) cbOneRegister(RL) = One(0x10, 1)
cbOneRegister(RR) = One(0x18, 1)
cbOneRegister(SLA) = One(0x20, 1) cbOneRegister(SLA) = One(0x20, 1)
cbOneRegister(SRA) = One(0x28, 1) cbOneRegister(SRA) = One(0x28, 1)
cbOneRegister(SLL) = One(0x30, 1) cbOneRegister(SLL) = One(0x30, 1)