diff --git a/src/main/scala/millfork/output/MosDeduplicate.scala b/src/main/scala/millfork/output/MosDeduplicate.scala
index e920e123..c5fe7d93 100644
--- a/src/main/scala/millfork/output/MosDeduplicate.scala
+++ b/src/main/scala/millfork/output/MosDeduplicate.scala
@@ -51,7 +51,7 @@ class MosDeduplicate(env: Environment, options: CompilationOptions) extends Dedu
   private val badAddressingModes = Set(Stack, IndexedSY, AbsoluteIndexedX, Indirect, LongIndirect)
 
   override def isExtractable(line: AssemblyLine): Boolean =
-    goodOpcodes(line.opcode) && !badAddressingModes(line.addrMode)
+    line.elidable && goodOpcodes(line.opcode) && !badAddressingModes(line.addrMode)
 
   override def isBadExtractedCodeHead(head: AssemblyLine): Boolean = false
 
diff --git a/src/main/scala/millfork/output/Z80Deduplicate.scala b/src/main/scala/millfork/output/Z80Deduplicate.scala
index 06a875c5..9e6f2a0d 100644
--- a/src/main/scala/millfork/output/Z80Deduplicate.scala
+++ b/src/main/scala/millfork/output/Z80Deduplicate.scala
@@ -49,13 +49,13 @@ class Z80Deduplicate(env: Environment, options: CompilationOptions) extends Dedu
   )
 
   override def isExtractable(line: ZLine): Boolean = {
-    alwaysGoodOpcodes(line.opcode) ||
+    line.elidable && (alwaysGoodOpcodes(line.opcode) ||
       conditionallyGoodOpcodes(line.opcode) && (line.registers match {
         case OneRegister(SP) => false
         case TwoRegisters(_, SP) => false
         case TwoRegisters(SP, _) => false
         case _ => true
-      })
+      }))
   }
 
   override def isBadExtractedCodeHead(head: ZLine): Boolean = false
diff --git a/src/test/scala/millfork/test/AssemblySuite.scala b/src/test/scala/millfork/test/AssemblySuite.scala
index 78a819ab..ee5d032d 100644
--- a/src/test/scala/millfork/test/AssemblySuite.scala
+++ b/src/test/scala/millfork/test/AssemblySuite.scala
@@ -178,28 +178,28 @@ class AssemblySuite extends FunSuite with Matchers with AppendedClues {
         |   e()
         |   f()
         | }
-        | noinline void a() {
+        | void a() {
         |   port = 1
         | }
-        | noinline void b() {
+        | void b() {
         |   port_alt = 2
         | }
-        | noinline asm void c() {
+        | asm void c() {
         |   lda #3
         |   sta 1
         |   rts
         | }
-        | noinline asm void d() {
+        | asm void d() {
         |   lda #4
         |   sta port
         |   rts
         | }
-        | noinline asm void e() {
+        | asm void e() {
         |   lda #5
         |   sta port_addr
         |   rts
         | }
-        | noinline asm void f() {
+        | asm void f() {
         |   lda #6
         |   sta port_alt
         |   rts