From 6e4e5863c68709910227db09692f1526f0f17abd Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Sat, 15 Jun 2019 01:43:46 +0200 Subject: [PATCH] More details on 8086 support --- docs/lang/x86disclaimer.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/docs/lang/x86disclaimer.md b/docs/lang/x86disclaimer.md index 014be62f..7c630fae 100644 --- a/docs/lang/x86disclaimer.md +++ b/docs/lang/x86disclaimer.md @@ -79,6 +79,13 @@ as 8080's `DAD` changes only the carry flag, and 8086's `ADD` changes many flags Luckily, this is not an issue with Millfork code, as the optimizer does not assume anything about flags after that instruction. The proper sequence is `LAHF`/`ADD r1,r2`/`RCR SI,1`/`SAHF`/`RCL SI,1`, but it is obviously too slow. +* the converter translates the `INX` instruction (16-bit `INC` on Z80) to `INC`, +and similarly, the `DCX` instruction (16-bit `DEC` on Z80) to `DEC` , +which may change behaviour of assembly code, +as 8080's `INX` and `DCX` don't change any flags, and 8086's `INC` and `DEC` change many flags. +Luckily, this is not an issue with Millfork code, as the optimizer does not assume anything about flags after that instruction. +The proper sequence is `LAHF`/`INC r` (or `DEC r`)/`SAHF`, but it is obviously too slow. + #### Register mapping The registers are translated as following: