From 72f8806c54b29d882c3272526a4e8a8bdf4f6f17 Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Wed, 23 Oct 2019 12:56:48 +0200
Subject: [PATCH] 6502: Word addition optimizations

---
 .../mos/opt/AlwaysGoodOptimizations.scala       | 17 +++++++++++++++++
 .../compiler/mos/PseudoregisterBuiltIns.scala   | 17 +++++++++++++----
 2 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
index 48b4ac50..0dd8772b 100644
--- a/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
+++ b/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
@@ -2540,6 +2540,23 @@ object AlwaysGoodOptimizations {
         code(8).copy(opcode = INC),
         AssemblyLine.label(label))
     },
+    (Elidable & HasOpcode(LDX) & HasImmediate(0) & HasClear(State.D)) ~
+      (Elidable & HasOpcode(BCC) & MatchParameter(14)) ~
+      (Elidable & HasOpcode(INX)) ~
+      (Elidable & HasOpcode(LABEL) & MatchParameter(14) & HasCallerCount(1)) ~
+      (Elidable & HasOpcode(STA) & Not(ConcernsX)) ~
+      (Elidable & HasOpcode(TXA)) ~
+      (Elidable & HasOpcode(CLC)) ~
+      (Elidable & HasOpcode(ADC)) ~
+      (Elidable & HasOpcode(STA) & DoesntMatterWhatItDoesWith(State.C, State.N, State.V, State.Z)) ~~> { (code, ctx) =>
+      val label = ctx.nextLabel("in")
+      List(
+        code(4), // STA
+        AssemblyLine.implied(TAX),
+        AssemblyLine.immediate(LDA, 0),
+        code(7), // ADC
+        code(8)) // STA
+    },
     (Elidable & HasOpcode(LDX) & HasAddrMode(Immediate) & HasClear(State.D)) ~
       (Elidable & HasOpcode(BCC) & MatchParameter(14)) ~
       (Elidable & HasOpcode(INX)) ~
diff --git a/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala b/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
index f7f49aed..df637af2 100644
--- a/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
+++ b/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
@@ -65,11 +65,20 @@ object PseudoregisterBuiltIns {
       case Some(ax) =>
         niceReads.prepend(ax -> List(AssemblyLine.implied(TXA)))
         if (!constant.isProvablyZero) {
-          if (constant.isQuiteNegative) {
-            niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte))
+          if (constant.loByte.quickSimplify.isProvablyZero) {
+            if (constant.isQuiteNegative) {
+              val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
+              niceReads += Nil -> List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.hiByte))
+            } else {
+              niceReads += Nil -> List(AssemblyLine.implied(CLC),AssemblyLine.immediate(ADC, constant.hiByte))
+            }
           } else {
-            val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
-            niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte))
+            if (constant.isQuiteNegative) {
+              val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
+              niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte))
+            } else {
+              niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte))
+            }
           }
         }
       case None =>