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https://github.com/KarolS/millfork.git
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Preliminary support for volatile variables
This commit is contained in:
Karol Stasiak
parent
5a99dc7293
commit
78afe3d5f5
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@ -51,6 +51,9 @@ but you need to be careful with using absolute vs immediate addressing:
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Any assembly opcode can be prefixed with `?`, which allows the optimizer change it or elide it if needed.
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Opcodes without that prefix will be always compiled as written.
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The '!' prefix marks the statement as volatile, which means it will be a subject to certain, but not all optimizations,
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in order to preserve its semantics.
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You can insert macros into assembly, by prefixing them with `+` and using the same syntax as in Millfork:
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macro void run(byte x) {
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@ -70,6 +70,9 @@ but you need to be careful with using absolute vs immediate addressing:
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Any assembly opcode can be prefixed with `?`, which allows the optimizer change it or elide it if needed.
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Opcodes without that prefix will be always compiled as written.
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The '!' prefix marks the statement as volatile, which means it will be a subject to certain, but not all optimizations,
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in order to preserve its semantics.
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You can insert macros into assembly, by prefixing them with `+` and using the same syntax as in Millfork:
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macro void run(byte x) {
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@ -20,10 +20,14 @@ or a top level of a function (*local* variables).
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Syntax:
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`[segment(<segment>)] [<storage>] <type> <name> [@<address>] [= <initial_value>]`
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`[segment(<segment>)] [volatile] [<storage>] <type> <name> [@<address>] [= <initial_value>]`
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* `<segment>`: segment name; if absent, then defaults to `default`.
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* `volatile` means that the variable is volatile.
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The optimizer shouldn't remove or reorder accesses to volatile variables.
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Volatile variables cannot be declared as `register` or `stack.
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* `<storage>` can be only specified for local variables. It can be either `stack`, `static`, `register` or nothing.
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`register` is only a hint for the optimizer.
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See [the description of variable storage](../abi/variable-storage.md).
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@ -5,21 +5,21 @@
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#endif
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// CIA1
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byte cia1_pra @$DC00
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byte cia1_prb @$DC01
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volatile byte cia1_pra @$DC00
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volatile byte cia1_prb @$DC01
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byte cia1_ddra @$DC02
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byte cia1_ddrb @$DC03
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byte cia2_pra @$DD00
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byte cia2_prb @$DD01
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volatile byte cia2_pra @$DD00
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volatile byte cia2_prb @$DD01
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byte cia2_ddra @$DD02
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byte cia2_ddrb @$DD03
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macro asm void cia_disable_irq() {
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LDA #$7f
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LDA $dc0d
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LDA $dd0d
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LDA $dc0d
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LDA $dd0d
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? LDA #$7f
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! LDA $dc0d
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! LDA $dd0d
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! LDA $dc0d
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! LDA $dd0d
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}
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@ -24,5 +24,5 @@ byte sid_v3_cr @$D412
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byte sid_v3_ad @$D413
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byte sid_v3_sr @$D414
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byte sid_paddle_x @$D419
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byte sid_paddle_y @$D41A
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volatile byte sid_paddle_x @$D419
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volatile byte sid_paddle_y @$D41A
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@ -24,15 +24,15 @@ byte vic_spr7_x @$D00E
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byte vic_spr7_y @$D00F
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byte vic_spr_hi_x @$D010
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byte vic_cr1 @$D011
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byte vic_raster @$D012
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volatile byte vic_raster @$D012
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byte vic_lp_x @$D013
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byte vic_lp_y @$D014
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byte vic_spr_ena @$D015
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byte vic_cr2 @$D016
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byte vic_spr_exp_y @$D017
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byte vic_mem @$D018
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byte vic_irq @$D019
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byte vic_irq_ena @$D01A
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volatile byte vic_irq @$D019
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volatile byte vic_irq_ena @$D01A
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byte vic_spr_dp @$D01B
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byte vic_spr_mcolor @$D01C
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byte vic_spr_exp_x @$D01D
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@ -2,58 +2,58 @@
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#warn nes_hardware module should be only used on NES/Famicom targets
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#endif
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byte ppu_ctrl @$2000
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byte ppu_mask @$2001
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byte ppu_status @$2002
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byte oam_addr @$2003
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byte oam_data @$2004
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byte ppu_scroll @$2005
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byte ppu_addr @$2006
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byte ppu_data @$2007
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byte oam_dma @$4014
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volatile byte ppu_ctrl @$2000
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volatile byte ppu_mask @$2001
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volatile byte ppu_status @$2002
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volatile byte oam_addr @$2003
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volatile byte oam_data @$2004
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volatile byte ppu_scroll @$2005
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volatile byte ppu_addr @$2006
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volatile byte ppu_data @$2007
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volatile byte oam_dma @$4014
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// TODO: better names
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byte apu_pulse1_ctrl @$4000
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byte apu_pulse1_sweep @$4001
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word apu_pulse1_period @$4002
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volatile byte apu_pulse1_ctrl @$4000
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volatile byte apu_pulse1_sweep @$4001
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volatile word apu_pulse1_period @$4002
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byte apu_pulse2_ctrl @$4004
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byte apu_pulse2_sweep @$4005
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word apu_pulse2_period @$4006
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volatile byte apu_pulse2_ctrl @$4004
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volatile byte apu_pulse2_sweep @$4005
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volatile word apu_pulse2_period @$4006
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byte apu_triangle_unmute @$4008
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word apu_triangle_period @$400A
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volatile byte apu_triangle_unmute @$4008
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volatile word apu_triangle_period @$400A
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byte apu_noise_ctrl @$400C
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byte apu_noise_period @$400E
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volatile byte apu_noise_ctrl @$400C
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volatile byte apu_noise_period @$400E
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byte apu_dmc_ctrl @$4010
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byte apu_dmc_load @$4011
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byte apu_dmc_sample_addr @$4012
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byte apu_dmc_sample_length @$4013
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volatile byte apu_dmc_ctrl @$4010
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volatile byte apu_dmc_load @$4011
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volatile byte apu_dmc_sample_addr @$4012
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volatile byte apu_dmc_sample_length @$4013
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byte apu_status @$4015
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byte apu_frame_counter @$4017
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volatile byte apu_status @$4015
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volatile byte apu_frame_counter @$4017
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byte joypad1_ctrl @$4016
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byte joypad2_ctrl @$4017
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volatile byte joypad1_ctrl @$4016
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volatile byte joypad2_ctrl @$4017
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inline asm byte strobe_joypad() {
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? LDA #1
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STA joypad1_ctrl
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LSR
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STA joypad1_ctrl
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! STA joypad1_ctrl
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? LSR
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! STA joypad1_ctrl
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? RTS
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}
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inline asm byte read_joypad1() {
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LDA joypad1_ctrl
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! LDA joypad1_ctrl
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? RTS
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}
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inline asm byte read_joypad2() {
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LDA joypad2_ctrl
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! LDA joypad2_ctrl
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? RTS
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}
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@ -62,29 +62,29 @@ macro asm void simulate_reset() {
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}
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inline asm void ppu_set_addr(word ax) {
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STX ppu_addr
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STA ppu_addr
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! STX ppu_addr
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! STA ppu_addr
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?RTS
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}
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inline asm byte read_ppu_status() {
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LDA ppu_status
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! LDA ppu_status
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? RTS
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}
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inline asm void ppu_set_scroll(word a, word x) {
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STA ppu_scroll
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STX ppu_scroll
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?RTS
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! STA ppu_scroll
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! STX ppu_scroll
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? RTS
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}
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inline asm void ppu_write_data(byte a) {
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STA ppu_data
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?RTS
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! STA ppu_data
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? RTS
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}
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inline asm void ppu_oam_dma_write(byte a) {
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STA oam_dma
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?RTS
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! STA oam_dma
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? RTS
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}
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@ -9,11 +9,11 @@ word reset_routine_addr @$FFFC
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word irq_routine_addr @$FFFE
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macro asm void poke(word const addr, byte a) {
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STA addr
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! STA addr
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}
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macro asm byte peek(word const addr) {
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LDA addr
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! LDA addr
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}
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macro asm void disable_irq() {
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@ -33,7 +33,7 @@ asm byte hi_nibble_to_hex(byte a) {
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}
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asm byte lo_nibble_to_hex(byte a) {
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AND #$F
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! AND #$F
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CLC
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ADC #$30
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CMP #$3A
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@ -44,7 +44,7 @@ _lo_nibble_to_hex_lbl:
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}
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macro asm void panic() {
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JSR _panic
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? JSR _panic
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}
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array __constant8 = [8]
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@ -9,11 +9,11 @@
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import i80_math
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macro asm void poke(word const addr, byte a) {
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LD (addr), A
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! LD (addr), A
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}
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macro asm byte peek(word const addr) {
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LD A, (addr)
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! LD A, (addr)
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}
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macro asm void disable_irq() {
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@ -51,5 +51,5 @@ _lo_nibble_to_hex_lbl:
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}
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macro asm void panic() {
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CALL _panic
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? CALL _panic
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}
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@ -3,75 +3,75 @@
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#warn vcs_hardware module should be only used on Atari 2600-compatible targets
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#endif
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byte VSYNC @$00
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byte VBLANK @$01
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byte WSYNC @$02
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byte RSYNC @$03
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byte NUSIZ0 @$04
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byte NUSIZ1 @$05
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byte COLUP0 @$06
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byte COLUP1 @$07
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byte COLUPF @$08
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byte COLUBK @$09
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byte CTRLPF @$0A
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byte REFP0 @$0B
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byte REFP1 @$0C
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byte PF0 @$0D
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byte PF1 @$0E
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byte PF2 @$0F
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byte RESP0 @$10
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byte RESP1 @$11
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byte RESM0 @$12
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byte RESM1 @$13
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byte RESBL @$14
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byte AUDC0 @$15
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byte AUDC1 @$16
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byte AUDF0 @$17
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byte AUDF1 @$18
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byte AUDV0 @$19
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byte AUDV1 @$1A
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byte GRP0 @$1B
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byte GRP1 @$1C
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byte ENAM0 @$1D
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byte ENAM1 @$1E
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byte ENABL @$1F
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byte HMP0 @$20
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byte HMP1 @$21
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byte HMM0 @$22
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byte HMM1 @$23
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byte HMBL @$24
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byte VDELP0 @$25
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byte VDELP1 @$26
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byte VDELBL @$27
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byte RESMP0 @$28
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byte RESMP1 @$29
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byte HMOVE @$2A
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byte HMCLR @$2B
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byte CXCLR @$2C
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byte CXM0P @$30
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byte CXM1P @$31
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byte CXP0FB @$32
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byte CXP1FB @$33
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byte CXM0FB @$34
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byte CXM1FB @$35
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byte CXBLPF @$36
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byte CXPPMM @$37
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byte INPT0 @$38
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byte INPT1 @$39
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byte INPT2 @$3A
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byte INPT3 @$3B
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byte INPT4 @$3C
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byte INPT5 @$3D
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byte SWCHA @$0280
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byte SWACNT @$0281
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byte SWCHB @$0282
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byte SWBCNT @$0283
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byte INTIM @$0284
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byte INSTAT @$0285
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byte TIM1T @$0294
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byte TIM8T @$0295
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byte TIM64T @$0296
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byte T1024T @$0297
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volatile byte VSYNC @$00
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volatile byte VBLANK @$01
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volatile byte WSYNC @$02
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volatile byte RSYNC @$03
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volatile byte NUSIZ0 @$04
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volatile byte NUSIZ1 @$05
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volatile byte COLUP0 @$06
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volatile byte COLUP1 @$07
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volatile byte COLUPF @$08
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volatile byte COLUBK @$09
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volatile byte CTRLPF @$0A
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volatile byte REFP0 @$0B
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volatile byte REFP1 @$0C
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volatile byte PF0 @$0D
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volatile byte PF1 @$0E
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volatile byte PF2 @$0F
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volatile byte RESP0 @$10
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volatile byte RESP1 @$11
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volatile byte RESM0 @$12
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volatile byte RESM1 @$13
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volatile byte RESBL @$14
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volatile byte AUDC0 @$15
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volatile byte AUDC1 @$16
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volatile byte AUDF0 @$17
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volatile byte AUDF1 @$18
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volatile byte AUDV0 @$19
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volatile byte AUDV1 @$1A
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volatile byte GRP0 @$1B
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volatile byte GRP1 @$1C
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volatile byte ENAM0 @$1D
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volatile byte ENAM1 @$1E
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volatile byte ENABL @$1F
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volatile byte HMP0 @$20
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volatile byte HMP1 @$21
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volatile byte HMM0 @$22
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volatile byte HMM1 @$23
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volatile byte HMBL @$24
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volatile byte VDELP0 @$25
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volatile byte VDELP1 @$26
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volatile byte VDELBL @$27
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volatile byte RESMP0 @$28
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volatile byte RESMP1 @$29
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volatile byte HMOVE @$2A
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volatile byte HMCLR @$2B
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volatile byte CXCLR @$2C
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volatile byte CXM0P @$30
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volatile byte CXM1P @$31
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volatile byte CXP0FB @$32
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volatile byte CXP1FB @$33
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volatile byte CXM0FB @$34
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volatile byte CXM1FB @$35
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volatile byte CXBLPF @$36
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volatile byte CXPPMM @$37
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volatile byte INPT0 @$38
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volatile byte INPT1 @$39
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volatile byte INPT2 @$3A
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volatile byte INPT3 @$3B
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volatile byte INPT4 @$3C
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volatile byte INPT5 @$3D
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volatile byte SWCHA @$0280
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volatile byte SWACNT @$0281
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volatile byte SWCHB @$0282
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volatile byte SWBCNT @$0283
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volatile byte INTIM @$0284
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volatile byte INSTAT @$0285
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volatile byte TIM1T @$0294
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volatile byte TIM8T @$0295
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volatile byte TIM64T @$0296
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volatile byte T1024T @$0297
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macro asm void wsync() {
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@ -79,28 +79,28 @@ macro asm void wsync() {
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}
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macro asm void start_frame() {
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LDA #0
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STA VBLANK
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LDA #2
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STA VSYNC
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STA WSYNC
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STA WSYNC
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STA WSYNC
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LDA #0
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STA VSYNC
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LDX #37
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? LDA #0
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! STA VBLANK
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? LDA #2
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! STA VSYNC
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! STA WSYNC
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! STA WSYNC
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! STA WSYNC
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! LDA #0
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! STA VSYNC
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? LDX #37
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start_frame_loop:
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STA WSYNC
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DEX
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! STA WSYNC
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? DEX
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BNE start_frame_loop
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}
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macro asm void end_frame() {
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LDA #%01000010
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STA VBLANK
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LDX #30
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? LDA #%01000010
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! STA VBLANK
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? LDX #30
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end_frame_loop:
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STA WSYNC
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DEX
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! STA WSYNC
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? DEX
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BNE end_frame_loop
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}
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|
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@ -414,12 +414,13 @@ object AssemblyLine {
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???
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}
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} else {
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val elidability = if (variable.isVolatile) Elidability.Volatile else Elidability.Elidable
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variable match {
|
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case v@MemoryVariable(_, _, VariableAllocationMethod.Zeropage) =>
|
||||
List(AssemblyLine.zeropage(opcode, v.toAddress + offset))
|
||||
case v@RelativeVariable(_, _, _, true, None) =>
|
||||
List(AssemblyLine.zeropage(opcode, v.toAddress + offset))
|
||||
case v: VariableInMemory => List(AssemblyLine.absolute(opcode, v.toAddress + offset))
|
||||
List(AssemblyLine.zeropage(opcode, v.toAddress + offset).copy(elidability = elidability))
|
||||
case v@RelativeVariable(_, _, _, true, None, _) =>
|
||||
List(AssemblyLine.zeropage(opcode, v.toAddress + offset).copy(elidability = elidability))
|
||||
case v: VariableInMemory => List(AssemblyLine.absolute(opcode, v.toAddress + offset).copy(elidability = elidability))
|
||||
case v: StackVariable =>
|
||||
AssemblyLine.tsx(ctx) :+ AssemblyLine.dataStackX(ctx, opcode, v, offset)
|
||||
}
|
||||
|
|
@ -520,8 +521,11 @@ case class AssemblyLine(opcode: Opcode.Value, addrMode: AddrMode.Value, var para
|
|||
|
||||
def mergePos(s: Seq[Option[SourceLine]]): AssemblyLine = if (s.isEmpty) this else pos(SourceLine.merge(this.source, s))
|
||||
|
||||
@inline
|
||||
def elidable: Boolean = elidability == Elidability.Elidable
|
||||
|
||||
@inline
|
||||
def notFixed: Boolean = elidability != Elidability.Fixed
|
||||
|
||||
import AddrMode._
|
||||
import OpcodeClasses._
|
||||
|
|
|
|||
|
|
@ -198,16 +198,16 @@ object AlwaysGoodOptimizations {
|
|||
HasOpcode(ANC) & HasAddrMode(Immediate) & DoesntMatterWhatItDoesWith(State.C)) ~~> { (code, ctx) =>
|
||||
AssemblyLine.immediate(LDA, CompoundConstant(MathOperator.And, NumericConstant(ctx.get[Int](0), 1), ctx.get[Constant](1)).quickSimplify) :: Nil
|
||||
},
|
||||
(Elidable & HasA(0) & HasOpcodeIn(ORA, EOR)) ~~> (code => code.map(_.copy(opcode = LDA))),
|
||||
(Elidable & HasA(0) & HasOpcode(ADC) &
|
||||
(NotFixed & HasA(0) & HasOpcodeIn(ORA, EOR)) ~~> (code => code.map(_.copy(opcode = LDA))),
|
||||
(NotFixed & HasA(0) & HasOpcode(ADC) &
|
||||
HasClear(State.D) & HasClear(State.C) &
|
||||
// C stays cleared!
|
||||
DoesntMatterWhatItDoesWith(State.V)) ~~> (code => code.map(_.copy(opcode = LDA))),
|
||||
(Elidable & HasA(0) & HasOpcode(ADC) &
|
||||
(NotFixed & HasA(0) & HasOpcode(ADC) &
|
||||
HasClear(State.C) &
|
||||
// C stays cleared!
|
||||
DoesntMatterWhatItDoesWith(State.N, State.Z, State.V)) ~~> (code => code.map(_.copy(opcode = LDA))),
|
||||
(Elidable & HasA(0xff) & HasOpcode(AND)) ~~> (code => code.map(_.copy(opcode = LDA))),
|
||||
(NotFixed & HasA(0xff) & HasOpcode(AND)) ~~> (code => code.map(_.copy(opcode = LDA))),
|
||||
(Elidable & HasA(0) & HasOpcode(AND)) ~~> (code => List(AssemblyLine.immediate(LDA, 0))),
|
||||
(Elidable & HasX(0) & HasOpcode(XAA)) ~~> (code => List(AssemblyLine.immediate(LDA, 0))),
|
||||
(Elidable & HasImmediate(0) & HasOpcode(AND)) ~~> (code => List(AssemblyLine.immediate(LDA, 0))),
|
||||
|
|
@ -455,6 +455,21 @@ object AlwaysGoodOptimizations {
|
|||
(Elidable & HasOpcode(TAZ) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
||||
(Linear & Not(ConcernsIZ) & DoesntChangeMemoryAt(0, 1)).* ~
|
||||
(Elidable & HasOpcode(TZA) & DoesntMatterWhatItDoesWith(State.IZ)) ~~> (code => code.head :: (code.drop(2).init :+ code.head.copy(opcode = LDA))),
|
||||
|
||||
(NotFixed & HasOpcodeIn(LDA, STA) & IsZeroPage & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
||||
(Elidable & Linear & Not(ConcernsX) & DoesNotConcernMemoryAt(0, 1)).* ~
|
||||
(Elidable & HasOpcode(TXA) & DoesntMatterWhatItDoesWith(State.X)) ~~> (code => code.head :: (code.drop(2).init :+ code.head.copy(opcode = LDA))),
|
||||
|
||||
(NotFixed & HasOpcodeIn(LDA, STA) & IsZeroPage & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(Elidable & HasOpcode(TAY) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
||||
(Elidable & Linear & Not(ConcernsY) & DoesNotConcernMemoryAt(0, 1)).* ~
|
||||
(Elidable & HasOpcode(TYA) & DoesntMatterWhatItDoesWith(State.Y)) ~~> (code => code.head :: (code.drop(2).init :+ code.head.copy(opcode = LDA))),
|
||||
|
||||
(NotFixed & HasOpcodeIn(LDA, STA) & IsZeroPage & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(Elidable & HasOpcode(TAZ) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
||||
(Elidable & Linear & Not(ConcernsIZ) & DoesNotConcernMemoryAt(0, 1)).* ~
|
||||
(Elidable & HasOpcode(TZA) & DoesntMatterWhatItDoesWith(State.IZ)) ~~> (code => code.head :: (code.drop(2).init :+ code.head.copy(opcode = LDA))),
|
||||
)
|
||||
|
||||
private def operationPairBuilder(op1: Opcode.Value, op2: Opcode.Value, middle: AssemblyLinePattern, discardToRemove: Option[Opcode.Value]) = {
|
||||
|
|
|
|||
|
|
@ -16,13 +16,13 @@ object CmosOptimizations {
|
|||
|
||||
val ZeroStoreAsStz = new RuleBasedAssemblyOptimization("Zero store",
|
||||
needsFlowInfo = FlowInfoRequirement.ForwardFlow,
|
||||
(HasA(0) & HasZ(0) & HasOpcode(STA) & Elidable & HasAddrModeIn(StzAddrModes)) ~~> {code =>
|
||||
(HasA(0) & HasZ(0) & HasOpcode(STA) & NotFixed & HasAddrModeIn(StzAddrModes)) ~~> {code =>
|
||||
code.head.copy(opcode = STZ) :: Nil
|
||||
},
|
||||
(HasX(0) & HasZ(0) & HasOpcode(STX) & Elidable & HasAddrModeIn(StzAddrModes)) ~~> {code =>
|
||||
(HasX(0) & HasZ(0) & HasOpcode(STX) & NotFixed & HasAddrModeIn(StzAddrModes)) ~~> {code =>
|
||||
code.head.copy(opcode = STZ) :: Nil
|
||||
},
|
||||
(HasY(0) & HasZ(0) & HasOpcode(STY) & Elidable & HasAddrModeIn(StzAddrModes)) ~~> {code =>
|
||||
(HasY(0) & HasZ(0) & HasOpcode(STY) & NotFixed & HasAddrModeIn(StzAddrModes)) ~~> {code =>
|
||||
code.head.copy(opcode = STZ) :: Nil
|
||||
},
|
||||
)
|
||||
|
|
|
|||
|
|
@ -86,17 +86,17 @@ object LaterOptimizations {
|
|||
|
||||
val DoubleLoadToTwoRegistersWhenOneWillBeTrashed = new RuleBasedAssemblyOptimization("Double load to two registers when one will be trashed",
|
||||
needsFlowInfo = FlowInfoRequirement.BackwardFlow,
|
||||
(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) ~
|
||||
(Elidable & HasOpcode(STA) & HasAddrModeIn(StxAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsX)).+ ~
|
||||
(NotFixed & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) ~
|
||||
(NotFixed & HasOpcode(STA) & HasAddrModeIn(StxAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsX)).+ ~
|
||||
(Elidable & (HasOpcode(TAX) | HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.init.map(a2x)),
|
||||
(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) ~
|
||||
(Elidable & HasOpcode(STA) & HasAddrModeIn(StyAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsY)).+ ~
|
||||
(NotFixed & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) ~
|
||||
(NotFixed & HasOpcode(STA) & HasAddrModeIn(StyAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsY)).+ ~
|
||||
(Elidable & (HasOpcode(TAY) | HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.init.map(a2y)),
|
||||
(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(Elidable & HasOpcode(STX) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
|
||||
(NotFixed & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(NotFixed & HasOpcode(STX) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
|
||||
(Elidable & (HasOpcode(TXA) | HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) & DoesntMatterWhatItDoesWith(State.X)) ~~> (_.init.map(x2a)),
|
||||
(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(Elidable & HasOpcode(STY) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
|
||||
(NotFixed & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
(NotFixed & HasOpcode(STY) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
|
||||
(Elidable & (HasOpcode(TYA) | HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) & DoesntMatterWhatItDoesWith(State.Y)) ~~> (_.init.map(y2a)),
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -744,7 +744,12 @@ case class EitherPattern(l: AssemblyLinePattern, r: AssemblyLinePattern) extends
|
|||
|
||||
case object Elidable extends AssemblyLinePattern {
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean =
|
||||
line.elidability == Elidability.Elidable
|
||||
line.elidable
|
||||
}
|
||||
|
||||
case object NotFixed extends AssemblyLinePattern {
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean =
|
||||
line.notFixed
|
||||
}
|
||||
|
||||
case object DebugMatching extends AssemblyPattern {
|
||||
|
|
|
|||
|
|
@ -88,6 +88,10 @@ object ZLine {
|
|||
import ZOpcode._
|
||||
import ZRegister._
|
||||
|
||||
private def elidability(source: ThingInMemory): Elidability.Value = {
|
||||
if (source.isVolatile) Elidability.Volatile else Elidability.Elidable
|
||||
}
|
||||
|
||||
def label(label: String): ZLine = ZLine.label(Label(label))
|
||||
|
||||
def label(label: Label): ZLine = ZLine(LABEL, NoRegisters, label.toAddress)
|
||||
|
|
@ -148,22 +152,50 @@ object ZLine {
|
|||
|
||||
def ldImm16(target: ZRegister.Value, source: Constant): ZLine = ZLine(LD_16, TwoRegisters(target, IMM_16), source)
|
||||
|
||||
def ldAbs8(target: ZRegister.Value, source: ThingInMemory): ZLine = ZLine(LD, TwoRegisters(target, MEM_ABS_8), source.toAddress)
|
||||
def ldAbs8(target: ZRegister.Value, source: ThingInMemory): ZLine =
|
||||
ZLine(LD, TwoRegisters(target, MEM_ABS_8), source.toAddress, elidability = elidability(source))
|
||||
|
||||
def ldAbs16(target: ZRegister.Value, source: ThingInMemory): ZLine = ZLine(LD_16, TwoRegisters(target, MEM_ABS_16), source.toAddress)
|
||||
def ldAbs16(target: ZRegister.Value, source: ThingInMemory): ZLine =
|
||||
ZLine(LD_16, TwoRegisters(target, MEM_ABS_16), source.toAddress, elidability = elidability(source))
|
||||
|
||||
def ldAbs8(target: ZRegister.Value, source: ThingInMemory, offset: Int): ZLine =
|
||||
ZLine(LD, TwoRegisters(target, MEM_ABS_8), source.toAddress + offset, elidability = elidability(source))
|
||||
|
||||
def ldAbs16(target: ZRegister.Value, source: ThingInMemory, offset: Int): ZLine =
|
||||
ZLine(LD_16, TwoRegisters(target, MEM_ABS_16), source.toAddress + offset, elidability = elidability(source))
|
||||
|
||||
def ldAbs8(target: ZRegister.Value, source: Constant): ZLine = ZLine(LD, TwoRegisters(target, MEM_ABS_8), source)
|
||||
|
||||
def ldAbs16(target: ZRegister.Value, source: Constant): ZLine = ZLine(LD_16, TwoRegisters(target, MEM_ABS_16), source)
|
||||
|
||||
def ldAbs8(target: ThingInMemory, source: ZRegister.Value): ZLine = ZLine(LD, TwoRegisters(MEM_ABS_8, source), target.toAddress)
|
||||
def ldAbs8(target: ZRegister.Value, source: Constant, elidability: Elidability.Value): ZLine =
|
||||
ZLine(LD, TwoRegisters(target, MEM_ABS_8), source, elidability = elidability)
|
||||
|
||||
def ldAbs16(target: ThingInMemory, source: ZRegister.Value): ZLine = ZLine(LD_16, TwoRegisters(MEM_ABS_16, source), target.toAddress)
|
||||
def ldAbs16(target: ZRegister.Value, source: Constant, elidability: Elidability.Value): ZLine =
|
||||
ZLine(LD_16, TwoRegisters(target, MEM_ABS_16), source, elidability = elidability)
|
||||
|
||||
def ldAbs8(target: ThingInMemory, source: ZRegister.Value): ZLine =
|
||||
ZLine(LD, TwoRegisters(MEM_ABS_8, source), target.toAddress, elidability = elidability(target))
|
||||
|
||||
def ldAbs16(target: ThingInMemory, source: ZRegister.Value): ZLine =
|
||||
ZLine(LD_16, TwoRegisters(MEM_ABS_16, source), target.toAddress, elidability = elidability(target))
|
||||
|
||||
def ldAbs8(target: ThingInMemory, source: ZRegister.Value, offset: Int): ZLine =
|
||||
ZLine(LD, TwoRegisters(MEM_ABS_8, source), target.toAddress + offset, elidability = elidability(target))
|
||||
|
||||
def ldAbs16(target: ThingInMemory, source: ZRegister.Value, offset: Int): ZLine =
|
||||
ZLine(LD_16, TwoRegisters(MEM_ABS_16, source), target.toAddress + offset, elidability = elidability(target))
|
||||
|
||||
def ldAbs8(target: Constant, source: ZRegister.Value): ZLine = ZLine(LD, TwoRegisters(MEM_ABS_8, source), target)
|
||||
|
||||
def ldAbs16(target: Constant, source: ZRegister.Value): ZLine = ZLine(LD_16, TwoRegisters(MEM_ABS_16, source), target)
|
||||
|
||||
def ldAbs8(target: Constant, source: ZRegister.Value, elidability: Elidability.Value): ZLine =
|
||||
ZLine(LD, TwoRegisters(MEM_ABS_8, source), target, elidability = elidability)
|
||||
|
||||
def ldAbs16(target: Constant, source: ZRegister.Value, elidability: Elidability.Value): ZLine =
|
||||
ZLine(LD_16, TwoRegisters(MEM_ABS_16, source), target, elidability = elidability)
|
||||
|
||||
def ldViaIx(target: ZRegister.Value, sourceOffset: Int): ZLine = ZLine(LD, TwoRegistersOffset(target, ZRegister.MEM_IX_D, sourceOffset), Constant.Zero)
|
||||
|
||||
def ldViaIx(targetOffset: Int, source: ZRegister.Value): ZLine = ZLine(LD, TwoRegistersOffset(ZRegister.MEM_IX_D, source, targetOffset), Constant.Zero)
|
||||
|
|
@ -194,8 +226,12 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
|
|||
|
||||
def mergePos(s: Seq[Option[SourceLine]]): ZLine = if (s.isEmpty) this else pos(SourceLine.merge(this.source, s))
|
||||
|
||||
@inline
|
||||
def elidable: Boolean = elidability == Elidability.Elidable
|
||||
|
||||
@inline
|
||||
def notFixed: Boolean = elidability != Elidability.Fixed
|
||||
|
||||
override def sizeInBytes: Int = {
|
||||
import ZOpcode._
|
||||
import ZRegister._
|
||||
|
|
|
|||
|
|
@ -722,6 +722,11 @@ case object Elidable extends AssemblyLinePattern {
|
|||
line.elidable
|
||||
}
|
||||
|
||||
case object NotFixed extends AssemblyLinePattern {
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: ZLine): Boolean =
|
||||
line.notFixed
|
||||
}
|
||||
|
||||
case object DebugMatching extends AssemblyPattern {
|
||||
override def matchTo(ctx: AssemblyMatchingContext, code: List[(FlowInfo, ZLine)]): Option[List[(FlowInfo, ZLine)]] = {
|
||||
println(ctx)
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ abstract class AbstractStatementPreprocessor(ctx: CompilationContext, statements
|
|||
}
|
||||
protected val reentrantVars: Set[String] = trackableVars.filter(v => env.get[Variable](v) match {
|
||||
case _: StackVariable => true
|
||||
case UninitializedMemoryVariable(_, _, VariableAllocationMethod.Auto, _, _) => ctx.options.flag(CompilationFlag.DangerousOptimizations)
|
||||
case v:UninitializedMemoryVariable if v.alloc == VariableAllocationMethod.Auto => ctx.options.flag(CompilationFlag.DangerousOptimizations)
|
||||
case _ => false
|
||||
})
|
||||
protected val nonreentrantVars: Set[String] = trackableVars -- reentrantVars
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ import millfork.assembly.mos.Opcode._
|
|||
import millfork.assembly.mos._
|
||||
import millfork.compiler._
|
||||
import millfork.env._
|
||||
import millfork.error.ConsoleLogger
|
||||
import millfork.node._
|
||||
|
||||
import scala.collection.mutable
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
package millfork.compiler.z80
|
||||
|
||||
import millfork.CompilationFlag
|
||||
import millfork.assembly.Elidability
|
||||
import millfork.assembly.z80._
|
||||
import millfork.compiler._
|
||||
import millfork.env._
|
||||
|
|
@ -248,7 +249,7 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
import ZRegister._
|
||||
v.typ.size match {
|
||||
case 0 => ???
|
||||
case 1 => loadByte(v.toAddress, target)
|
||||
case 1 => loadByte(v.toAddress, target, v.isVolatile)
|
||||
case 2 => target match {
|
||||
case ZExpressionTarget.NOTHING => Nil
|
||||
case ZExpressionTarget.HL =>
|
||||
|
|
@ -256,7 +257,7 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
List(ZLine.ldAbs16(HL, v))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(L, A), ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(H, A))
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(L, A), ZLine.ldAbs8(A, v, 1), ZLine.ld8(H, A))
|
||||
}
|
||||
case ZExpressionTarget.EHL =>
|
||||
// TODO: signed words
|
||||
|
|
@ -264,7 +265,7 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
List(ZLine.ldAbs16(HL, v), ZLine.ldImm8(E, 0))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(L, A), ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(H, A), ZLine.ldImm8(E, 0))
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(L, A), ZLine.ldAbs8(A, v, 1), ZLine.ld8(H, A), ZLine.ldImm8(E, 0))
|
||||
}
|
||||
case ZExpressionTarget.DEHL =>
|
||||
// TODO: signed words
|
||||
|
|
@ -272,7 +273,7 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
List(ZLine.ldAbs16(HL, v), ZLine.ldImm16(DE, 0))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(L, A), ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(H, A), ZLine.ldImm16(DE, 0))
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(L, A), ZLine.ldAbs8(A, v, 1), ZLine.ld8(H, A), ZLine.ldImm16(DE, 0))
|
||||
}
|
||||
case ZExpressionTarget.BC =>
|
||||
if (ctx.options.flag(CompilationFlag.EmitZ80Opcodes)) {
|
||||
|
|
@ -281,7 +282,7 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
List(ZLine.ldAbs16(HL, v), ZLine.ld8(B, H), ZLine.ld8(C, L))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(C, A), ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(B, A))
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(C, A), ZLine.ldAbs8(A, v, 1), ZLine.ld8(B, A))
|
||||
}
|
||||
case ZExpressionTarget.DE =>
|
||||
if (ctx.options.flag(CompilationFlag.EmitZ80Opcodes)) {
|
||||
|
|
@ -290,31 +291,31 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
List(ZLine.ldAbs16(HL, v), ZLine.ld8(D, H), ZLine.ld8(E, L))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(E, A), ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(D, A))
|
||||
List(ZLine.ldAbs8(A, v), ZLine.ld8(E, A), ZLine.ldAbs8(A, v, 1), ZLine.ld8(D, A))
|
||||
}
|
||||
}
|
||||
case 3 => target match {
|
||||
case ZExpressionTarget.NOTHING => Nil
|
||||
case ZExpressionTarget.EHL =>
|
||||
if (ctx.options.flag(CompilationFlag.EmitIntel8080Opcodes)) {
|
||||
List(ZLine.ldAbs16(HL, v), ZLine.ldAbs8(A, v.toAddress + 2), ZLine.ld8(E, A))
|
||||
List(ZLine.ldAbs16(HL, v), ZLine.ldAbs8(A, v, 2), ZLine.ld8(E, A))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(
|
||||
ZLine.ldAbs8(A, v), ZLine.ld8(L, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(H, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 2), ZLine.ld8(E, A))
|
||||
ZLine.ldAbs8(A, v, 1), ZLine.ld8(H, A),
|
||||
ZLine.ldAbs8(A, v, 2), ZLine.ld8(E, A))
|
||||
}
|
||||
case ZExpressionTarget.DEHL =>
|
||||
// TODO: signed farwords
|
||||
if (ctx.options.flag(CompilationFlag.EmitIntel8080Opcodes)) {
|
||||
List(ZLine.ldAbs16(HL, v), ZLine.ldAbs8(A, v.toAddress + 2), ZLine.ld8(E, A), ZLine.ldImm8(D, 0))
|
||||
List(ZLine.ldAbs16(HL, v), ZLine.ldAbs8(A, v, 2), ZLine.ld8(E, A), ZLine.ldImm8(D, 0))
|
||||
} else {
|
||||
// TODO: is it optimal?
|
||||
List(
|
||||
ZLine.ldAbs8(A, v), ZLine.ld8(L, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(H, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 2), ZLine.ld8(E, A), ZLine.ldImm8(D, 0))
|
||||
ZLine.ldAbs8(A, v, 1), ZLine.ld8(H, A),
|
||||
ZLine.ldAbs8(A, v, 2), ZLine.ld8(E, A), ZLine.ldImm8(D, 0))
|
||||
}
|
||||
}
|
||||
case 4 => target match {
|
||||
|
|
@ -330,9 +331,9 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
// TODO: is it optimal?
|
||||
List(
|
||||
ZLine.ldAbs8(A, v), ZLine.ld8(L, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 1), ZLine.ld8(H, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 2), ZLine.ld8(E, A),
|
||||
ZLine.ldAbs8(A, v.toAddress + 3), ZLine.ld8(D, A))
|
||||
ZLine.ldAbs8(A, v, 1), ZLine.ld8(H, A),
|
||||
ZLine.ldAbs8(A, v, 2), ZLine.ld8(E, A),
|
||||
ZLine.ldAbs8(A, v, 3), ZLine.ld8(D, A))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -438,7 +439,7 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
}
|
||||
case i: IndexedExpression =>
|
||||
calculateAddressToHL(ctx, i) match {
|
||||
case List(ZLine0(LD_16, TwoRegisters(ZRegister.HL, ZRegister.IMM_16), addr)) => loadByte(addr, target)
|
||||
case List(ZLine0(LD_16, TwoRegisters(ZRegister.HL, ZRegister.IMM_16), addr)) => loadByte(addr, target, volatile = false)
|
||||
case code => code ++ loadByteViaHL(target)
|
||||
}
|
||||
case SumExpression(params, decimal) =>
|
||||
|
|
@ -985,15 +986,16 @@ object Z80ExpressionCompiler extends AbstractExpressionCompiler[ZLine] {
|
|||
}
|
||||
}
|
||||
|
||||
def loadByte(sourceAddr: Constant, target: ZExpressionTarget.Value): List[ZLine] = {
|
||||
def loadByte(sourceAddr: Constant, target: ZExpressionTarget.Value, volatile: Boolean): List[ZLine] = {
|
||||
val elidability = if (volatile) Elidability.Volatile else Elidability.Elidable
|
||||
target match {
|
||||
case ZExpressionTarget.NOTHING => Nil
|
||||
case ZExpressionTarget.A => List(ZLine.ldAbs8(ZRegister.A, sourceAddr))
|
||||
case ZExpressionTarget.HL => List(ZLine.ldAbs8(ZRegister.A, sourceAddr), ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ldImm8(ZRegister.H, 0))
|
||||
case ZExpressionTarget.BC => List(ZLine.ldAbs8(ZRegister.A, sourceAddr), ZLine.ld8(ZRegister.C, ZRegister.A), ZLine.ldImm8(ZRegister.B, 0))
|
||||
case ZExpressionTarget.DE => List(ZLine.ldAbs8(ZRegister.A, sourceAddr), ZLine.ld8(ZRegister.E, ZRegister.A), ZLine.ldImm8(ZRegister.D, 0))
|
||||
case ZExpressionTarget.EHL => List(ZLine.ldAbs8(ZRegister.A, sourceAddr), ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ldImm8(ZRegister.H, 0), ZLine.ldImm8(ZRegister.E, 0))
|
||||
case ZExpressionTarget.DEHL => List(ZLine.ldAbs8(ZRegister.A, sourceAddr), ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ldImm8(ZRegister.H, 0), ZLine.ldImm16(ZRegister.DE, 0))
|
||||
case ZExpressionTarget.A => List(ZLine.ldAbs8(ZRegister.A, sourceAddr, elidability))
|
||||
case ZExpressionTarget.HL => List(ZLine.ldAbs8(ZRegister.A, sourceAddr, elidability), ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ldImm8(ZRegister.H, 0))
|
||||
case ZExpressionTarget.BC => List(ZLine.ldAbs8(ZRegister.A, sourceAddr, elidability), ZLine.ld8(ZRegister.C, ZRegister.A), ZLine.ldImm8(ZRegister.B, 0))
|
||||
case ZExpressionTarget.DE => List(ZLine.ldAbs8(ZRegister.A, sourceAddr, elidability), ZLine.ld8(ZRegister.E, ZRegister.A), ZLine.ldImm8(ZRegister.D, 0))
|
||||
case ZExpressionTarget.EHL => List(ZLine.ldAbs8(ZRegister.A, sourceAddr, elidability), ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ldImm8(ZRegister.H, 0), ZLine.ldImm8(ZRegister.E, 0))
|
||||
case ZExpressionTarget.DEHL => List(ZLine.ldAbs8(ZRegister.A, sourceAddr, elidability), ZLine.ld8(ZRegister.L, ZRegister.A), ZLine.ldImm8(ZRegister.H, 0), ZLine.ldImm16(ZRegister.DE, 0))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
59
src/main/scala/millfork/env/Environment.scala
vendored
59
src/main/scala/millfork/env/Environment.scala
vendored
|
|
@ -34,7 +34,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
}
|
||||
|
||||
def genRelativeVariable(constant: Constant, typ: Type, zeropage: Boolean): RelativeVariable = {
|
||||
val variable = RelativeVariable(nextLabel("rv"), constant, typ, zeropage = zeropage, declaredBank = None /*TODO*/)
|
||||
val variable = RelativeVariable(nextLabel("rv"), constant, typ, zeropage = zeropage, declaredBank = None /*TODO*/, isVolatile = false)
|
||||
addThing(variable, None)
|
||||
variable
|
||||
}
|
||||
|
|
@ -83,7 +83,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
things.values.flatMap {
|
||||
case RelativeArray(_, NumericConstant(addr, _), size, declaredBank, _, _) =>
|
||||
List((declaredBank.getOrElse("default"), addr.toInt, size))
|
||||
case RelativeVariable(_, NumericConstant(addr, _), typ, _, declaredBank) =>
|
||||
case RelativeVariable(_, NumericConstant(addr, _), typ, _, declaredBank, _) =>
|
||||
List((declaredBank.getOrElse("default"), addr.toInt, typ.size))
|
||||
case f: NormalFunction =>
|
||||
f.environment.getAllFixedAddressObjects
|
||||
|
|
@ -830,11 +830,11 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
if (!thing.zeropage && options.flag(CompilationFlag.LUnixRelocatableCode)) {
|
||||
val b = get[Type]("byte")
|
||||
val w = get[Type]("word")
|
||||
val relocatable = UninitializedMemoryVariable(thing.name + ".addr", w, VariableAllocationMethod.Static, None, defaultVariableAlignment(options, 2))
|
||||
val relocatable = UninitializedMemoryVariable(thing.name + ".addr", w, VariableAllocationMethod.Static, None, defaultVariableAlignment(options, 2), isVolatile = false)
|
||||
val addr = relocatable.toAddress
|
||||
addThing(relocatable, position)
|
||||
addThing(RelativeVariable(thing.name + ".addr.hi", addr + 1, b, zeropage = false, None), position)
|
||||
addThing(RelativeVariable(thing.name + ".addr.lo", addr, b, zeropage = false, None), position)
|
||||
addThing(RelativeVariable(thing.name + ".addr.hi", addr + 1, b, zeropage = false, None, isVolatile = false), position)
|
||||
addThing(RelativeVariable(thing.name + ".addr.lo", addr, b, zeropage = false, None, isVolatile = false), position)
|
||||
val rawaddr = thing.toAddress
|
||||
addThing(ConstantThing(thing.name + ".rawaddr", rawaddr, get[Type]("pointer")), position)
|
||||
addThing(ConstantThing(thing.name + ".rawaddr.hi", rawaddr.hiByte, get[Type]("byte")), position)
|
||||
|
|
@ -858,12 +858,12 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
stmt.assemblyParamPassingConvention match {
|
||||
case ByVariable(name) =>
|
||||
val zp = typ.name == "pointer" // TODO
|
||||
val v = UninitializedMemoryVariable(prefix + name, typ, if (zp) VariableAllocationMethod.Zeropage else VariableAllocationMethod.Auto, None, defaultVariableAlignment(options, 2))
|
||||
val v = UninitializedMemoryVariable(prefix + name, typ, if (zp) VariableAllocationMethod.Zeropage else VariableAllocationMethod.Auto, None, defaultVariableAlignment(options, 2), isVolatile = false)
|
||||
addThing(v, stmt.position)
|
||||
registerAddressConstant(v, stmt.position, options)
|
||||
val addr = v.toAddress
|
||||
for((suffix, offset, t) <- getSubvariables(typ)) {
|
||||
addThing(RelativeVariable(v.name + suffix, addr + offset, t, zeropage = zp, None), stmt.position)
|
||||
addThing(RelativeVariable(v.name + suffix, addr + offset, t, zeropage = zp, None, isVolatile = v.isVolatile), stmt.position)
|
||||
}
|
||||
case ByMosRegister(_) => ()
|
||||
case ByZRegister(_) => ()
|
||||
|
|
@ -872,10 +872,10 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
addThing(v, stmt.position)
|
||||
case ByReference(name) =>
|
||||
val addr = UnexpandedConstant(prefix + name, typ.size)
|
||||
val v = RelativeVariable(prefix + name, addr, p, zeropage = false, None)
|
||||
val v = RelativeVariable(prefix + name, addr, p, zeropage = false, None, isVolatile = false)
|
||||
addThing(v, stmt.position)
|
||||
addThing(RelativeVariable(v.name + ".hi", addr + 1, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(v.name + ".lo", addr, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(v.name + ".hi", addr + 1, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
addThing(RelativeVariable(v.name + ".lo", addr, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -966,23 +966,23 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
declaredBank = stmt.bank, indexType, b)
|
||||
}
|
||||
addThing(array, stmt.position)
|
||||
registerAddressConstant(UninitializedMemoryVariable(stmt.name, p, VariableAllocationMethod.None, stmt.bank, NoAlignment), stmt.position, options)
|
||||
registerAddressConstant(UninitializedMemoryVariable(stmt.name, p, VariableAllocationMethod.None, stmt.bank, NoAlignment, isVolatile = false), stmt.position, options)
|
||||
val a = address match {
|
||||
case None => array.toAddress
|
||||
case Some(aa) => aa
|
||||
}
|
||||
addThing(RelativeVariable(stmt.name + ".first", a, b, zeropage = false,
|
||||
declaredBank = stmt.bank), stmt.position)
|
||||
declaredBank = stmt.bank, isVolatile = false), stmt.position)
|
||||
if (options.flag(CompilationFlag.LUnixRelocatableCode)) {
|
||||
val b = get[Type]("byte")
|
||||
val w = get[Type]("word")
|
||||
val relocatable = UninitializedMemoryVariable(stmt.name, w, VariableAllocationMethod.Static, None, NoAlignment)
|
||||
val relocatable = UninitializedMemoryVariable(stmt.name, w, VariableAllocationMethod.Static, None, NoAlignment, isVolatile = false)
|
||||
val addr = relocatable.toAddress
|
||||
addThing(relocatable, stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".addr.hi", addr + 1, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".addr.lo", addr, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.hi", addr + 1, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.lo", addr, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".addr.hi", addr + 1, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".addr.lo", addr, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.hi", addr + 1, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.lo", addr, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
} else {
|
||||
addThing(ConstantThing(stmt.name, a, p), stmt.position)
|
||||
addThing(ConstantThing(stmt.name + ".hi", a.hiByte.quickSimplify, b), stmt.position)
|
||||
|
|
@ -1035,21 +1035,21 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
val array = InitializedArray(stmt.name + ".array", address, contents, declaredBank = stmt.bank, indexType, b, alignment)
|
||||
addThing(array, stmt.position)
|
||||
registerAddressConstant(UninitializedMemoryVariable(stmt.name, p, VariableAllocationMethod.None,
|
||||
declaredBank = stmt.bank, alignment), stmt.position, options)
|
||||
declaredBank = stmt.bank, alignment, isVolatile = false), stmt.position, options)
|
||||
val a = address match {
|
||||
case None => array.toAddress
|
||||
case Some(aa) => aa
|
||||
}
|
||||
addThing(RelativeVariable(stmt.name + ".first", a, b, zeropage = false,
|
||||
declaredBank = stmt.bank), stmt.position)
|
||||
declaredBank = stmt.bank, isVolatile = false), stmt.position)
|
||||
if (options.flag(CompilationFlag.LUnixRelocatableCode)) {
|
||||
val b = get[Type]("byte")
|
||||
val w = get[Type]("word")
|
||||
val relocatable = UninitializedMemoryVariable(stmt.name, w, VariableAllocationMethod.Static, None, NoAlignment)
|
||||
val relocatable = UninitializedMemoryVariable(stmt.name, w, VariableAllocationMethod.Static, None, NoAlignment, isVolatile = false)
|
||||
val addr = relocatable.toAddress
|
||||
addThing(relocatable, stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.hi", addr + 1, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.lo", addr, b, zeropage = false, None), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.hi", addr + 1, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
addThing(RelativeVariable(stmt.name + ".array.lo", addr, b, zeropage = false, None, isVolatile = false), stmt.position)
|
||||
} else {
|
||||
addThing(ConstantThing(stmt.name, a, p), stmt.position)
|
||||
addThing(ConstantThing(stmt.name + ".hi", a.hiByte.quickSimplify, b), stmt.position)
|
||||
|
|
@ -1064,9 +1064,6 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
}
|
||||
|
||||
def registerVariable(stmt: VariableDeclarationStatement, options: CompilationOptions): Unit = {
|
||||
if (stmt.volatile) {
|
||||
log.warn("`volatile` not yet supported", stmt.position)
|
||||
}
|
||||
val name = stmt.name
|
||||
val position = stmt.position
|
||||
if (stmt.stack && parent.isEmpty) {
|
||||
|
|
@ -1103,6 +1100,8 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
if (stmt.register && typ.size != 1) log.error(s"A register variable `$name` is too large", position)
|
||||
if (stmt.register && stmt.global) log.error(s"`$name` is static or global and cannot be in a register", position)
|
||||
if (stmt.register && stmt.stack) log.error(s"`$name` cannot be simultaneously on stack and in a register", position)
|
||||
if (stmt.volatile && stmt.stack) log.error(s"`$name` cannot be simultaneously on stack and volatile", position)
|
||||
if (stmt.volatile && stmt.register) log.error(s"`$name` cannot be simultaneously volatile and in a register", position)
|
||||
if (stmt.initialValue.isDefined && parent.isDefined) log.error(s"`$name` is local and not a constant and therefore cannot have a value", position)
|
||||
if (stmt.initialValue.isDefined && stmt.address.isDefined) log.warn(s"`$name` has both address and initial value - this may not work as expected!", position)
|
||||
if (stmt.register && stmt.address.isDefined) log.error(s"`$name` cannot by simultaneously at an address and in a register", position)
|
||||
|
|
@ -1124,11 +1123,11 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
log.error(s"`$name` cannot be preinitialized`", position)
|
||||
}
|
||||
val v = stmt.initialValue.fold[MemoryVariable](UninitializedMemoryVariable(prefix + name, typ, alloc,
|
||||
declaredBank = stmt.bank, alignment)){ive =>
|
||||
declaredBank = stmt.bank, alignment, isVolatile = stmt.volatile)){ive =>
|
||||
if (options.flags(CompilationFlag.ReadOnlyArrays)) {
|
||||
log.warn("Initialized variable in read-only segment", position)
|
||||
}
|
||||
InitializedMemoryVariable(name, None, typ, ive, declaredBank = stmt.bank, alignment)
|
||||
InitializedMemoryVariable(name, None, typ, ive, declaredBank = stmt.bank, alignment, isVolatile = stmt.volatile)
|
||||
}
|
||||
registerAddressConstant(v, stmt.position, options)
|
||||
(v, v.toAddress)
|
||||
|
|
@ -1139,7 +1138,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
case _ => false
|
||||
}
|
||||
val v = RelativeVariable(prefix + name, addr, typ, zeropage = zp,
|
||||
declaredBank = stmt.bank)
|
||||
declaredBank = stmt.bank, isVolatile = stmt.volatile)
|
||||
registerAddressConstant(v, stmt.position, options)
|
||||
(v, addr)
|
||||
})
|
||||
|
|
@ -1148,7 +1147,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
addThing(ConstantThing(v.name + "`", addr, b), stmt.position)
|
||||
}
|
||||
for((suffix, offset, t) <- getSubvariables(typ)) {
|
||||
addThing(RelativeVariable(prefix + name + suffix, addr + offset, t, zeropage = v.zeropage, declaredBank = stmt.bank), stmt.position)
|
||||
addThing(RelativeVariable(prefix + name + suffix, addr + offset, t, zeropage = v.zeropage, declaredBank = stmt.bank, isVolatile = v.isVolatile), stmt.position)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1263,7 +1262,7 @@ class Environment(val parent: Option[Environment], val prefix: String, val cpuFa
|
|||
}
|
||||
if (options.flag(CompilationFlag.SoftwareStack)) {
|
||||
if (!things.contains("__sp")) {
|
||||
things("__sp") = UninitializedMemoryVariable("__sp", b, VariableAllocationMethod.Auto, None, NoAlignment)
|
||||
things("__sp") = UninitializedMemoryVariable("__sp", b, VariableAllocationMethod.Auto, None, NoAlignment, isVolatile = false)
|
||||
things("__stack") = UninitializedArray("__stack", 256, None, b, b, WithinPageAlignment)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
41
src/main/scala/millfork/env/Thing.scala
vendored
41
src/main/scala/millfork/env/Thing.scala
vendored
|
|
@ -105,6 +105,8 @@ sealed trait ThingInMemory extends Thing {
|
|||
|
||||
def isFar(compilationOptions: CompilationOptions): Boolean
|
||||
def bank(compilationOptions: CompilationOptions): String
|
||||
|
||||
def isVolatile: Boolean
|
||||
}
|
||||
|
||||
sealed trait PreallocableThing extends ThingInMemory {
|
||||
|
|
@ -129,9 +131,13 @@ case class Label(name: String) extends ThingInMemory {
|
|||
override val declaredBank: Option[String] = None
|
||||
|
||||
override def zeropage: Boolean = false
|
||||
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
sealed trait Variable extends TypedThing with VariableLikeThing
|
||||
sealed trait Variable extends TypedThing with VariableLikeThing {
|
||||
def isVolatile: Boolean
|
||||
}
|
||||
|
||||
sealed trait VariableInMemory extends Variable with ThingInMemory with IndexableThing {
|
||||
|
||||
|
|
@ -144,13 +150,18 @@ sealed trait VariableInMemory extends Variable with ThingInMemory with Indexable
|
|||
|
||||
case class RegisterVariable(register: MosRegister.Value, typ: Type) extends Variable {
|
||||
def name: String = register.toString
|
||||
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
case class ZRegisterVariable(register: ZRegister.Value, typ: Type) extends Variable {
|
||||
def name: String = register.toString
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
case class Placeholder(name: String, typ: Type) extends Variable
|
||||
case class Placeholder(name: String, typ: Type) extends Variable {
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
sealed trait UninitializedMemory extends ThingInMemory {
|
||||
def sizeInBytes: Int
|
||||
|
|
@ -166,6 +177,7 @@ object VariableAllocationMethod extends Enumeration {
|
|||
|
||||
case class StackVariable(name: String, typ: Type, baseOffset: Int) extends Variable {
|
||||
def sizeInBytes: Int = typ.size
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
object MemoryVariable {
|
||||
|
|
@ -176,7 +188,14 @@ abstract class MemoryVariable extends VariableInMemory {
|
|||
def alloc: VariableAllocationMethod.Value
|
||||
}
|
||||
|
||||
case class UninitializedMemoryVariable(name: String, typ: Type, alloc: VariableAllocationMethod.Value, declaredBank: Option[String], override val alignment: MemoryAlignment) extends MemoryVariable with UninitializedMemory {
|
||||
case class UninitializedMemoryVariable(
|
||||
name: String,
|
||||
typ: Type,
|
||||
alloc:
|
||||
VariableAllocationMethod.Value,
|
||||
declaredBank: Option[String],
|
||||
override val alignment: MemoryAlignment,
|
||||
override val isVolatile: Boolean) extends MemoryVariable with UninitializedMemory {
|
||||
override def sizeInBytes: Int = typ.size
|
||||
|
||||
override def zeropage: Boolean = alloc == VariableAllocationMethod.Zeropage
|
||||
|
|
@ -184,7 +203,14 @@ case class UninitializedMemoryVariable(name: String, typ: Type, alloc: VariableA
|
|||
override def toAddress: MemoryAddressConstant = MemoryAddressConstant(this)
|
||||
}
|
||||
|
||||
case class InitializedMemoryVariable(name: String, address: Option[Constant], typ: Type, initialValue: Expression, declaredBank: Option[String], override val alignment: MemoryAlignment) extends MemoryVariable with PreallocableThing {
|
||||
case class InitializedMemoryVariable(
|
||||
name: String,
|
||||
address: Option[Constant],
|
||||
typ: Type,
|
||||
initialValue: Expression,
|
||||
declaredBank: Option[String],
|
||||
override val alignment: MemoryAlignment,
|
||||
override val isVolatile: Boolean) extends MemoryVariable with PreallocableThing {
|
||||
override def zeropage: Boolean = false
|
||||
|
||||
override def toAddress: MemoryAddressConstant = MemoryAddressConstant(this)
|
||||
|
|
@ -197,6 +223,7 @@ case class InitializedMemoryVariable(name: String, address: Option[Constant], ty
|
|||
trait MfArray extends ThingInMemory with IndexableThing {
|
||||
def indexType: VariableType
|
||||
def elementType: VariableType
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
case class UninitializedArray(name: String, /* TODO: what if larger elements? */ sizeInBytes: Int, declaredBank: Option[String], indexType: VariableType, elementType: VariableType, override val alignment: MemoryAlignment) extends MfArray with UninitializedMemory {
|
||||
|
|
@ -231,7 +258,7 @@ case class InitializedArray(name: String, address: Option[Constant], contents: L
|
|||
override def zeropage: Boolean = false
|
||||
}
|
||||
|
||||
case class RelativeVariable(name: String, address: Constant, typ: Type, zeropage: Boolean, declaredBank: Option[String]) extends VariableInMemory {
|
||||
case class RelativeVariable(name: String, address: Constant, typ: Type, zeropage: Boolean, declaredBank: Option[String], override val isVolatile: Boolean) extends VariableInMemory {
|
||||
override def toAddress: Constant = address
|
||||
}
|
||||
|
||||
|
|
@ -282,6 +309,8 @@ case class ExternFunction(name: String,
|
|||
override def interrupt = false
|
||||
|
||||
override def zeropage: Boolean = false
|
||||
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
case class NormalFunction(name: String,
|
||||
|
|
@ -300,6 +329,8 @@ case class NormalFunction(name: String,
|
|||
override def shouldGenerate = true
|
||||
|
||||
override def zeropage: Boolean = false
|
||||
|
||||
override def isVolatile: Boolean = false
|
||||
}
|
||||
|
||||
case class ConstantThing(name: String, value: Constant, typ: Type) extends TypedThing with VariableLikeThing with IndexableThing {
|
||||
|
|
|
|||
|
|
@ -592,8 +592,9 @@ object MfParser {
|
|||
val nonStatementLevel = 1 // everything but not `=`
|
||||
val mathLevel = 4 // the `:` operator
|
||||
|
||||
val elidable: P[Elidability.Value] = ("?".! ~/ HWS).?.map{
|
||||
case Some(_) => Elidability.Elidable
|
||||
val elidable: P[Elidability.Value] = (("!" | "?").! ~/ HWS).?.map{
|
||||
case Some("?") => Elidability.Elidable
|
||||
case Some("!") => Elidability.Volatile
|
||||
case _ => Elidability.Fixed
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user