From 7b040c280bb0f5d38ec2943a582db499f5a8827c Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Wed, 13 Nov 2019 19:08:50 +0100
Subject: [PATCH] (part 2) 6502: Do not optimize away register restoration in
 interrupt routines (fixes #19)

---
 .../scala/millfork/compiler/mos/MosStatementCompiler.scala    | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/millfork/compiler/mos/MosStatementCompiler.scala b/src/main/scala/millfork/compiler/mos/MosStatementCompiler.scala
index c7fd0bd2..4e3066dd 100644
--- a/src/main/scala/millfork/compiler/mos/MosStatementCompiler.scala
+++ b/src/main/scala/millfork/compiler/mos/MosStatementCompiler.scala
@@ -136,7 +136,7 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
           val lastByte = if (zpRegisterSize % 2 != 0) {
             List(
               AssemblyLine.implied(PLA),
-              AssemblyLine.zeropage(STA, reg, zpRegisterSize - 1),
+              AssemblyLine.zeropage(STA, reg, zpRegisterSize - 1).copy(elidability = Elidability.Volatile),
               AssemblyLine.accu16)
           } else {
             List(AssemblyLine.accu16)
@@ -144,7 +144,7 @@ object MosStatementCompiler extends AbstractStatementCompiler[AssemblyLine] {
           val remainingBytes = (zpRegisterSize.&(0xfe).-(2) to 0 by (-2)).flatMap { i =>
             List(
               AssemblyLine.implied(PLA_W),
-              AssemblyLine.zeropage(STA_W, reg, i),
+              AssemblyLine.zeropage(STA_W, reg, i).copy(elidability = Elidability.Volatile),
               AssemblyLine.accu8)
           }
           lastByte ++ remainingBytes