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Division optimizations
This commit is contained in:
Karol Stasiak
parent
fbe20a240b
commit
869211658a
@ -552,6 +552,35 @@ case class MatchA(i: Int) extends AssemblyLinePattern {
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override def hitRate: Double = 0.42
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}
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case class MatchStoredRegister(i: Int) extends AssemblyLinePattern {
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override def validate(needsFlowInfo: FlowInfoRequirement.Value): Unit =
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FlowInfoRequirement.assertForward(needsFlowInfo)
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override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean = {
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import Opcode._
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line.opcode match {
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case STA =>
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flowInfo.statusBefore.a match {
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case SingleStatus(value) => ctx.addObject(i, value)
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case _ => false
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}
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case STX =>
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flowInfo.statusBefore.x match {
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case SingleStatus(value) => ctx.addObject(i, value)
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case _ => false
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}
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case STY =>
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flowInfo.statusBefore.y match {
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case SingleStatus(value) => ctx.addObject(i, value)
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case _ => false
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}
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case _ => false
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}
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}
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override def hitRate: Double = 0.42
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}
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case class MatchX(i: Int) extends AssemblyLinePattern {
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override def validate(needsFlowInfo: FlowInfoRequirement.Value): Unit =
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FlowInfoRequirement.assertForward(needsFlowInfo)
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@ -5,6 +5,7 @@ import millfork.assembly.mos.AddrMode._
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import millfork.assembly.AssemblyOptimization
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import millfork.assembly.mos.{AssemblyLine, AssemblyLine0, Opcode, State}
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import millfork.DecimalUtils.asDecimal
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import millfork.assembly.z80.opt.HasRegister
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import millfork.error.FatalErrorReporting
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/**
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* @author Karol Stasiak
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@ -115,6 +116,76 @@ object ZeropageRegisterOptimizations {
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},
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)
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val ConstantDivision = new RuleBasedAssemblyOptimization("Constant division",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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// TODO: constants other than power of 2:
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(HasOpcodeIn(STA, STX, STY) & RefersTo("__reg", 1) & MatchStoredRegister(2) & MatchAddrMode(0) & MatchParameter(1)) ~
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Where({ ctx =>
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val a = ctx.get[Int](2)
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a != 0 && a.-(1).&(a) == 0
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}) ~
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(Linear & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(JSR) & RefersTo("__div_u8u8u8u8", 0)
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& DoesntMatterWhatItDoesWith(State.C, State.Z, State.N, State.V) // everything else (including Y) should be preserved
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& DoesntMatterWhatItDoesWithReg(0)
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& DoesntMatterWhatItDoesWithReg(1)) ~~> { (code, ctx) =>
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val count = Integer.numberOfTrailingZeros(ctx.get[Int](2))
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val zreg = ctx.zeropageRegister.get
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code.init ++ List(AssemblyLine.zeropage(LDA, zreg)) ++ List.fill(count)(AssemblyLine.implied(LSR))
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},
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(HasOpcodeIn(STA, STX, STY) & RefersTo("__reg", 1) & MatchStoredRegister(2) & MatchAddrMode(0) & MatchParameter(1)) ~
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Where({ ctx =>
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val a = ctx.get[Int](2)
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a != 0 && a.-(1).&(a) == 0
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}) ~
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(Linear & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(JSR) & RefersTo("__mod_u8u8u8u8", 0)
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& DoesntMatterWhatItDoesWith(State.C, State.Z, State.N, State.V, State.X) // everything else (including Y) should be preserved
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& DoesntMatterWhatItDoesWithReg(0)
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& DoesntMatterWhatItDoesWithReg(1)) ~~> { (code, ctx) =>
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val a = ctx.get[Int](2)
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val zreg = ctx.zeropageRegister.get
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code.init ++ List(AssemblyLine.zeropage(LDA, zreg), AssemblyLine.immediate(AND, a - 1))
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},
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(HasOpcodeIn(STA, STX, STY) & RefersTo("__reg", 2) & MatchStoredRegister(2) & MatchAddrMode(0) & MatchParameter(1)) ~
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Where({ ctx =>
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val a = ctx.get[Int](2)
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a != 0 && a.-(1).&(a) == 0
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}) ~
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(Linear & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(JSR) & RefersTo("__div_u16u8u16u8", 0)
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& DoesntMatterWhatItDoesWith(State.C, State.Z, State.N, State.V) // everything else (including Y) should be preserved
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& DoesntMatterWhatItDoesWithReg(0)
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& DoesntMatterWhatItDoesWithReg(1)
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& DoesntMatterWhatItDoesWithReg(2)) ~~> { (code, ctx) =>
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val count = Integer.numberOfTrailingZeros(ctx.get[Int](2))
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val zreg = ctx.zeropageRegister.get
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code.init ++
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List.fill(count)(List(AssemblyLine.zeropage(LSR, zreg, 1), AssemblyLine.zeropage(ROR, zreg))).flatten ++
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List(AssemblyLine.zeropage(LDA, zreg), AssemblyLine.zeropage(LDX, zreg, 1))
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},
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(HasOpcodeIn(STA, STX, STY) & RefersTo("__reg", 2) & MatchStoredRegister(2) & MatchAddrMode(0) & MatchParameter(1)) ~
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Where({ ctx =>
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val a = ctx.get[Int](2)
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a != 0 && a.-(1).&(a) == 0 && a <= 128
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}) ~
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(Linear & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(JSR) & RefersTo("__mod_u16u8u16u8", 0)
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& DoesntMatterWhatItDoesWith(State.C, State.Z, State.N, State.V, State.X) // everything else (including Y) should be preserved
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& DoesntMatterWhatItDoesWithReg(0)
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& DoesntMatterWhatItDoesWithReg(1)
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& DoesntMatterWhatItDoesWithReg(2)) ~~> { (code, ctx) =>
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val a = ctx.get[Int](2)
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val zreg = ctx.zeropageRegister.get
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code.init ++ List(AssemblyLine.zeropage(LDA, zreg), AssemblyLine.immediate(AND, a - 1), AssemblyLine.immediate(LDX, 0))
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},
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)
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val ConstantDecimalMath = new RuleBasedAssemblyOptimization("Constant decimal math",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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@ -400,6 +471,7 @@ object ZeropageRegisterOptimizations {
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val All: List[AssemblyOptimization[AssemblyLine]] = List(
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ConstantDecimalMath,
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ConstantDivision,
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ConstantMultiplication,
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ConstantInlinedMultiplication,
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LoadingKnownValue,
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@ -6,6 +6,7 @@ import millfork.assembly.z80.ZOpcode._
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import millfork.env.{CompoundConstant, Constant, InitializedArray, MathOperator, MemoryAddressConstant, NumericConstant}
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import millfork.node.{LiteralExpression, ZRegister}
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import ZRegister._
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import millfork.CompilationFlag
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import millfork.DecimalUtils._
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import millfork.error.FatalErrorReporting
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@ -1309,6 +1310,51 @@ object AlwaysGoodI80Optimizations {
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)
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val ConstantDivision = new RuleBasedAssemblyOptimization("Constant division",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(CALL)
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& IsUnconditional
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& RefersTo("__divmod_u16u8u16u8", 0)
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& MatchRegister(ZRegister.H, 4)
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& MatchRegister(ZRegister.L, 5)
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& MatchRegister(ZRegister.D, 6)
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& DoesntMatterWhatItDoesWithFlags
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& DoesntMatterWhatItDoesWith(ZRegister.D, ZRegister.E, ZRegister.C, ZRegister.B)) ~~> { (_, ctx) =>
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val p = ctx.get[Int](4) * 256 + ctx.get[Int](5).&(0xff)
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val q = ctx.get[Int](6)
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if (q == 0) Nil // lol undefined behaviour, everyone's favourite C feature
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else List(ZLine.ldImm16(ZRegister.HL, p / q), ZLine.ldImm8(ZRegister.A, p % q))
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},
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(Elidable & HasOpcode(CALL)
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& IsUnconditional
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& RefersTo("__divmod_u16u8u16u8", 0)
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& MatchRegister(ZRegister.D, 6)
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& DoesntMatterWhatItDoesWithFlags
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& DoesntMatterWhatItDoesWith(ZRegister.D, ZRegister.E, ZRegister.C, ZRegister.B)) ~
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Where(ctx => {
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val q = ctx.get[Int](6)
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q != 0 && q.&(q - 1) == 0
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}) ~~> { (_, ctx) =>
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val q = ctx.get[Int](6)
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if (ctx.compilationOptions.flag(CompilationFlag.EmitExtended80Opcodes)) {
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List(ZLine.ld8(ZRegister.A, ZRegister.L), ZLine.imm8(ZOpcode.AND, q - 1)) ++ (0L until Integer.numberOfTrailingZeros(q)).flatMap(_ => List(
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ZLine.register(ZOpcode.SRL, ZRegister.H),
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ZLine.register(ZOpcode.RR, ZRegister.L)
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))
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} else {
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List(ZLine.ld8(ZRegister.D, ZRegister.L)) ++ (0L until Integer.numberOfTrailingZeros(q)).flatMap(_ => List(
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ZLine.ld8(ZRegister.A, ZRegister.H),
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ZLine.register(ZOpcode.OR, ZRegister.A),
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ZLine.implied(ZOpcode.RRA),
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ZLine.ld8(ZRegister.H, ZRegister.A),
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ZLine.ld8(ZRegister.A, ZRegister.L),
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ZLine.implied(ZOpcode.RRA),
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ZLine.ld8(ZRegister.L, ZRegister.A)
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)) ++ List(ZLine.ld8(ZRegister.A, ZRegister.D), ZLine.imm8(ZOpcode.AND, q - 1))
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}
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},
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)
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private def compileMultiply[T](multiplicand: Int, add1:List[T], asl: List[T]): List[T] = {
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if (multiplicand == 0) FatalErrorReporting.reportFlyingPig("Trying to optimize multiplication by 0 in a wrong way!")
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def impl(m: Int): List[List[T]] = {
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@ -1537,6 +1583,7 @@ object AlwaysGoodI80Optimizations {
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val All: List[AssemblyOptimization[ZLine]] = List[AssemblyOptimization[ZLine]](
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BranchInPlaceRemoval,
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ConstantDivision,
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ConstantMultiplication,
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ConstantInlinedShifting,
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FreeHL,
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@ -390,4 +390,48 @@ class ByteMathSuite extends FunSuite with Matchers with AppendedClues {
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divisionCase1(42, 128)
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divisionCase1(142, 128)
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}
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test("Byte division 4") {
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divisionCase4(0, 2)
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divisionCase4(1, 2)
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divisionCase4(2, 2)
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divisionCase4(250, 128)
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divisionCase4(0, 4)
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divisionCase4(0, 8)
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divisionCase4(1, 4)
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divisionCase4(6, 8)
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divisionCase4(73, 16)
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divisionCase4(75, 128)
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divisionCase4(42, 128)
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divisionCase4(142, 128)
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}
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private def divisionCase4(x: Int, y: Int): Unit = {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Sharp, Cpu.Intel8086)(
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s"""
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| import zp_reg
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| byte output_q1 @$$c000
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| byte output_m1 @$$c001
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| byte output_q2 @$$c002
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| byte output_m2 @$$c003
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| void main () {
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| byte a
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| output_q2 = g()
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| output_m2 = g()
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| a = f()
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| output_q1 = $x / a
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| output_m1 = $x %% a
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| output_q2 /= a
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| output_m2 %%= a
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| }
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| byte f() {return $y}
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| noinline byte g() {return $x}
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""".
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stripMargin) { m =>
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m.readByte(0xc000) should equal(x / y) withClue s"$x / $y"
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m.readByte(0xc001) should equal(x % y) withClue s"$x %% $y"
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m.readByte(0xc002) should equal(x / y) withClue s"$x / $y"
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m.readByte(0xc003) should equal(x % y) withClue s"$x %% $y"
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}
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}
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}
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@ -538,4 +538,53 @@ class WordMathSuite extends FunSuite with Matchers with AppendedClues {
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m.readWord(0xc006) should equal(x % y) withClue s"= $x %% $y"
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}
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}
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test("Word division 4") {
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divisionCase4(0, 2)
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divisionCase4(1, 2)
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divisionCase4(2, 2)
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divisionCase4(250, 128)
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divisionCase4(0, 4)
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divisionCase4(0, 8)
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divisionCase4(1, 4)
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divisionCase4(6, 8)
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divisionCase4(73, 16)
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divisionCase4(75, 128)
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divisionCase4(42, 128)
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divisionCase4(142, 128)
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divisionCase2(2534, 2)
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divisionCase2(2534, 32)
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divisionCase2(35000, 2)
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divisionCase2(51462, 4)
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divisionCase2(51462, 1)
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}
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private def divisionCase4(x: Int, y: Int): Unit = {
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EmuCrossPlatformBenchmarkRun(Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Sharp, Cpu.Intel8086)(
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s"""
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| import zp_reg
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| word output_q1 @$$c000
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| byte output_m1 @$$c002
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| word output_q2 @$$c004
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| word output_m2 @$$c006
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| void main () {
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| byte a
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| output_q2 = g()
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| output_m2 = g()
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| a = f()
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| output_q1 = $x / a
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| output_m1 = $x %% a
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| output_q2 /= a
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| output_m2 %%= a
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| }
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| byte f() {return $y}
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| noinline word g() {return $x}
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""".
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stripMargin) { m =>
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m.readWord(0xc000) should equal(x / y) withClue s"$x / $y"
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m.readByte(0xc002) should equal(x % y) withClue s"$x %% $y"
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m.readWord(0xc004) should equal(x / y) withClue s"$x / $y"
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m.readByte(0xc006) should equal(x % y) withClue s"$x %% $y"
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}
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}
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}
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