mirror of
https://github.com/KarolS/millfork.git
synced 2024-07-05 09:28:54 +00:00
6502: Track values of zeropage registers
This commit is contained in:
Karol Stasiak
parent
64744f7559
commit
8dd8415432
@ -73,7 +73,7 @@ object CoarseFlowAnalyzer {
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currentStatus = FlowAnalyzerForImmediate.get(op)(nn.toInt, currentStatus)
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case AssemblyLine(op, _, _, _) if FlowAnalyzerForTheRest.hasDefinition(op) =>
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currentStatus = FlowAnalyzerForTheRest.get(op)(currentStatus)
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currentStatus = FlowAnalyzerForTheRest.get(op)(currentStatus, None)
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case AssemblyLine(opcode, addrMode, _, _) =>
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currentStatus = currentStatus.copy(src = AnyStatus)
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@ -47,6 +47,10 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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x: Status[Int] = UnknownStatus,
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y: Status[Int] = UnknownStatus,
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iz: Status[Int] = UnknownStatus,
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r0: Status[Int] = UnknownStatus,
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r1: Status[Int] = UnknownStatus,
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r2: Status[Int] = UnknownStatus,
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r3: Status[Int] = UnknownStatus,
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src: Status[SourceOfNZ] = UnknownStatus,
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eqSX: Boolean = false,
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z: Status[Boolean] = UnknownStatus,
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@ -90,7 +94,7 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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// case _ =>
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// }
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override def toString: String = s"A=$a,B=$ah,X=$x,Y=$y,Z=$iz; Z=$z,N=$n,C=$c,V=$v,D=$d,M=$m,X=$w; A7=$a7,A0=$a0,NZ:$src" +
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override def toString: String = s"A=$a,B=$ah,X=$x,Y=$y,Z=$iz; Z=$z,N=$n,C=$c,V=$v,D=$d,M=$m,X=$w; R0=$r0,R1=$r1,R2=$r2,R3=$r3; A7=$a7,A0=$a0,NZ:$src" +
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(if (eqSX) "; S=X"
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else /* */ " ")
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@ -159,6 +163,39 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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case State.W => w.contains(true)
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case _ => false
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}
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def reg(i: Int) : Status[Int] = i match {
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case 0 => r0
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case 1 => r1
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case 2 => r2
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case 3 => r3
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case _ => AnyStatus
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}
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def getReg(i: Option[Int]) : Status[Int] = i match {
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case Some(0) => r0
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case Some(1) => r1
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case Some(2) => r2
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case Some(3) => r3
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case _ => AnyStatus
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}
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def getRegHi(i: Option[Int]) : Status[Int] = i match {
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case Some(0) => r1
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case Some(1) => r2
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case Some(2) => r3
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case _ => AnyStatus
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}
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def setReg(i: Option[Int], status: Status[Int]): CpuStatus = {
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i match {
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case Some(0) => this.copy(r0 = status)
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case Some(1) => this.copy(r1 = status)
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case Some(2) => this.copy(r2 = status)
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case Some(3) => this.copy(r3 = status)
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case None => this
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}
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}
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}
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object CpuStatus {
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@ -173,7 +210,11 @@ object CpuStatus {
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = SingleStatus(0)
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iz = SingleStatus(0),
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialStatusCE = CpuStatus(
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a = AnyStatus,
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@ -186,7 +227,11 @@ object CpuStatus {
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d = SingleStatus(false),
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m = SingleStatus(true),
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w = SingleStatus(true),
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iz = AnyStatus
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iz = AnyStatus,
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialInterruptStatusStandard = CpuStatus(
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@ -200,7 +245,11 @@ object CpuStatus {
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d = AnyStatus,
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m = AnyStatus,
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w = AnyStatus,
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iz = SingleStatus(0)
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iz = SingleStatus(0),
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialInterruptStatusCmos = CpuStatus(
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a = AnyStatus,
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@ -213,7 +262,11 @@ object CpuStatus {
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d = SingleStatus(false),
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m = AnyStatus,
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w = AnyStatus,
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iz = SingleStatus(0)
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iz = SingleStatus(0),
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val initialInterruptStatusCE = CpuStatus(
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a = AnyStatus,
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@ -226,7 +279,11 @@ object CpuStatus {
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d = SingleStatus(false),
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m = AnyStatus,
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w = AnyStatus,
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iz = AnyStatus
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iz = AnyStatus,
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r0 = AnyStatus,
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r1 = AnyStatus,
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r2 = AnyStatus,
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r3 = AnyStatus,
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)
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val emptyStatusStandard = CpuStatus(iz = SingleStatus(0))
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@ -72,7 +72,7 @@ object FlowAnalyzerForImmediate {
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},
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ADC -> {(nn, currentStatus) =>
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val n = nn & 0xff
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val newA = currentStatus.a.adc(n, currentStatus.c, currentStatus.d)
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val (newA, newC) = currentStatus.a.adc(n, currentStatus.c, currentStatus.d)
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currentStatus.copy(
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n = newA.n(),
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z = newA.z(),
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@ -80,7 +80,7 @@ object FlowAnalyzerForImmediate {
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a = newA,
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a0 = newA.bit0,
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a7 = newA.bit7,
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c = Status.flatMap3(currentStatus.a, currentStatus.c, currentStatus.d) {
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c = newC | Status.flatMap3(currentStatus.a, currentStatus.c, currentStatus.d) {
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case (aa, false, false) => SingleStatus((aa & 0xff) + n >= 0x100)
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case _ => AnyStatus
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},
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@ -88,7 +88,7 @@ object FlowAnalyzerForImmediate {
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},
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SBC -> {(nn, currentStatus) =>
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val n = nn & 0xff
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val newA = currentStatus.a.sbc(n, currentStatus.c, currentStatus.d)
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val (newA, newC) = currentStatus.a.sbc(n, currentStatus.c, currentStatus.d)
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currentStatus.copy(
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n = newA.n(),
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z = newA.z(),
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@ -96,7 +96,7 @@ object FlowAnalyzerForImmediate {
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a = newA,
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a0 = newA.bit0,
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a7 = newA.bit7,
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c = AnyStatus,
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c = newC,
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v = AnyStatus)
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},
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EOR -> {(nn, currentStatus) =>
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@ -8,35 +8,35 @@ import millfork.assembly.opt.{AnyStatus, SingleStatus, Status}
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* @author Karol Stasiak
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*/
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object FlowAnalyzerForTheRest {
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private val map: Map[Opcode.Value, CpuStatus => CpuStatus] = Map(
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STA -> identity,
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STX -> identity,
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STY -> identity,
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STZ -> identity,
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SAX -> identity,
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NOP -> identity,
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DISCARD_AF -> identity,
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DISCARD_XF -> identity,
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DISCARD_YF -> identity,
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REP -> (currentStatus => {
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private val map: Map[Opcode.Value, (CpuStatus, Option[Int]) => CpuStatus] = Map(
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STA -> ((c,zpreg) => c.setReg(zpreg, c.a)),
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STX -> ((c,zpreg) => c.setReg(zpreg, c.x)),
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STY -> ((c,zpreg) => c.setReg(zpreg, c.y)),
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STZ -> ((c,zpreg) => c.setReg(zpreg, c.iz)),
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SAX -> ((c,zpreg) => c.setReg(zpreg, (c.a <*> c.x)(_ & _))),
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NOP -> ((x,_) => x),
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DISCARD_AF -> ((x,_) => x),
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DISCARD_XF -> ((x,_) => x),
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DISCARD_YF -> ((x,_) => x),
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REP -> ((currentStatus, zpreg) => {
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currentStatus.copy(c = AnyStatus, d = AnyStatus, n = AnyStatus, z= AnyStatus, v = AnyStatus, m = AnyStatus, w = AnyStatus)
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}),
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SEP -> (currentStatus => {
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SEP -> ((currentStatus, zpreg) => {
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currentStatus.copy(c = AnyStatus, d = AnyStatus, n = AnyStatus, z= AnyStatus, v = AnyStatus, m = AnyStatus, w = AnyStatus)
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}),
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BCC -> (currentStatus => {
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BCC -> ((currentStatus, zpreg) => {
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currentStatus.copy(c = Status.SingleTrue)
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}),
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BCS -> (currentStatus => {
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BCS -> ((currentStatus, zpreg) => {
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currentStatus.copy(c = Status.SingleFalse)
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}),
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BVS -> (currentStatus => {
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BVS -> ((currentStatus, zpreg) => {
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currentStatus.copy(v = Status.SingleFalse)
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}),
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BVC -> (currentStatus => {
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BVC -> ((currentStatus, zpreg) => {
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currentStatus.copy(v = Status.SingleTrue)
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}),
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BMI -> (c => {
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BMI -> ((c, zpreg) => {
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var currentStatus = c
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currentStatus = currentStatus.copy(n = Status.SingleFalse)
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if (currentStatus.src.isFromA) {
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@ -44,7 +44,7 @@ object FlowAnalyzerForTheRest {
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}
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currentStatus
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}),
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BPL -> (c => {
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BPL -> ((c, zpreg) => {
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var currentStatus = c
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currentStatus = currentStatus.copy(n = Status.SingleTrue)
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if (currentStatus.src.isFromA) {
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@ -52,10 +52,10 @@ object FlowAnalyzerForTheRest {
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}
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currentStatus
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}),
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BEQ -> (currentStatus => {
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BEQ -> ((currentStatus, zpreg) => {
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currentStatus.copy(z = Status.SingleFalse)
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}),
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BNE -> (c => {
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BNE -> ((c, zpreg) => {
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var currentStatus = c
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currentStatus = currentStatus.copy(z = Status.SingleTrue)
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if (currentStatus.src.isFromA) {
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@ -79,100 +79,123 @@ object FlowAnalyzerForTheRest {
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}
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currentStatus
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}),
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LDX -> (currentStatus => {
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LDX -> ((currentStatus, zpreg) => {
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val newX = currentStatus.getReg(zpreg)
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currentStatus.copy(
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x = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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x = newX,
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n = newX.n(),
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z = newX.z(),
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src = SourceOfNZ.X)
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}),
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LDY -> (currentStatus => {
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LDY -> ((currentStatus, zpreg) => {
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val newY = currentStatus.getReg(zpreg)
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currentStatus.copy(
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y = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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y = newY,
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n = newY.n(),
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z = newY.z(),
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src = SourceOfNZ.Y)
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}),
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LDA -> (currentStatus => {
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LDA -> ((currentStatus, zpreg) => {
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val newA = currentStatus.getReg(zpreg)
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currentStatus.copy(
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a = AnyStatus,
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a7 = AnyStatus,
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a0 = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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a = newA,
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a7 = newA.bit7,
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a0 = newA.bit0,
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n = newA.n(),
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z = newA.z(),
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src = SourceOfNZ.A)
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}),
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LDZ -> (currentStatus => {
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LDZ -> ((currentStatus, zpreg) => {
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val newZ = currentStatus.getReg(zpreg)
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currentStatus.copy(
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iz = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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iz = newZ,
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n = newZ.n(),
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z = newZ.z(),
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src = SourceOfNZ.Z)
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}),
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LAX -> (currentStatus => {
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LAX -> ((currentStatus, zpreg) => {
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val newA = currentStatus.getReg(zpreg)
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currentStatus.copy(
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x = AnyStatus,
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a = AnyStatus,
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a7 = AnyStatus,
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a0 = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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x = newA,
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a = newA,
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a7 = newA.bit7,
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a0 = newA.bit0,
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n = newA.n(),
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z = newA.z(),
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src = SourceOfNZ.AX)
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}),
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LDA_W -> (currentStatus => {
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LDA_W -> ((currentStatus, zpreg) => {
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val newA = currentStatus.getReg(zpreg)
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val newAH = currentStatus.getRegHi(zpreg)
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currentStatus.copy(
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ah = AnyStatus,
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a = AnyStatus,
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ah = newAH,
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a = newA,
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a7 = AnyStatus,
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a0 = AnyStatus,
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a0 = newA.bit0,
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n = AnyStatus,
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z = AnyStatus,
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src = SourceOfNZ.AW)
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}),
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LDX_W -> (currentStatus => {
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LDX_W -> ((currentStatus, zpreg) => {
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currentStatus.copy(
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x = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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src = AnyStatus)
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}),
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LDY_W -> (currentStatus => {
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LDY_W -> ((currentStatus, zpreg) => {
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currentStatus.copy(
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y = AnyStatus,
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n = AnyStatus,
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z = AnyStatus,
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src = AnyStatus)
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}),
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ADC -> (currentStatus => {
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ADC -> ((currentStatus, zpreg) => {
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val r = currentStatus.getReg(zpreg)
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val newA: Status[Int]= if (currentStatus.d.contains(false)) Status.flatMap3(currentStatus.a, r, currentStatus.c) {
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case (m, n, false) => SingleStatus((m + n) & 0xff)
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case (m, n, true) => SingleStatus((m + n + 1) & 0xff)
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} else AnyStatus
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val newC: Status[Boolean]= if (currentStatus.d.contains(false)) Status.flatMap3(currentStatus.a, r, currentStatus.c) {
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case (m, n, false) => SingleStatus((m.&(0xff) + n.&(0xff)) > 0xff)
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case (m, n, true) => SingleStatus((m.&(0xff) + n.&(0xff) + 1) > 0xff)
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} else AnyStatus
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currentStatus.copy(
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a = AnyStatus,
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a7 = AnyStatus,
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a0 = AnyStatus,
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a = newA,
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a7 = newA.bit7,
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a0 = newA.bit0,
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v = AnyStatus,
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c = Status.flatMap3(currentStatus.a, currentStatus.c, currentStatus.d) {
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c = newC | Status.flatMap3(currentStatus.a, currentStatus.c, currentStatus.d) {
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case (0, false, false) => SingleStatus[Boolean](false)
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case _ => AnyStatus
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},
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z = AnyStatus,
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n = AnyStatus,
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z = newA.z(),
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n = newA.n(),
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src = currentStatus.d.flatMap((dec: Boolean) => if (dec) AnyStatus else SourceOfNZ.A))
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}),
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SBC -> (currentStatus => {
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SBC -> ((currentStatus, zpreg) => {
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val r = currentStatus.getReg(zpreg)
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val newA: Status[Int]= if (currentStatus.d.contains(false)) Status.flatMap3(currentStatus.a, r, currentStatus.c) {
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case (m, n, false) => SingleStatus((m - n + 0xff) & 0xff)
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case (m, n, true) => SingleStatus((m - n + 0x100) & 0xff)
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} else AnyStatus
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currentStatus.copy(
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a = AnyStatus,
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a7 = AnyStatus,
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a0 = AnyStatus,
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a = newA,
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a7 = newA.bit7,
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a0 = newA.bit0,
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v = AnyStatus,
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c = Status.flatMap3(currentStatus.a, currentStatus.c, currentStatus.d) {
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case (0xff, true, false) => SingleStatus[Boolean](true)
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case _ => AnyStatus
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},
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z = AnyStatus,
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n = AnyStatus,
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z = newA.z(),
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n = newA.n(),
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src = currentStatus.d.flatMap((dec: Boolean) => if (dec) AnyStatus else SourceOfNZ.A))
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}),
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AND -> (currentStatus => {
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val newA: Status[Int] = currentStatus.a.flatMap(v => if ((v & 0xff) == 0) Status.SingleZero else AnyStatus)
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AND -> ((currentStatus, zpreg) => {
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val newA: Status[Int] =
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currentStatus.a.flatMap(v => if ((v & 0xff) == 0) Status.SingleZero else AnyStatus) |
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(currentStatus.a <*> currentStatus.getReg(zpreg))(_ & _)
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currentStatus.copy(
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a = newA,
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a7 = currentStatus.a7.flatMap(v => if (!v) Status.SingleFalse else AnyStatus),
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@ -181,8 +204,10 @@ object FlowAnalyzerForTheRest {
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z = newA.z(),
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src = SourceOfNZ.A)
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}),
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ORA -> (currentStatus => {
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val newA: Status[Int] = currentStatus.a.flatMap(v => if ((v & 0xff) == 0xff) Status.SingleFF else AnyStatus)
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ORA -> ((currentStatus, zpreg) => {
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val newA: Status[Int] =
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currentStatus.a.flatMap(v => if ((v & 0xff) == 0xff) Status.SingleFF else AnyStatus) |
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(currentStatus.a <*> currentStatus.getReg(zpreg))(_ | _)
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currentStatus.copy(
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a = newA,
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a7 = currentStatus.a7.flatMap(v => if (v) Status.SingleTrue else AnyStatus),
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@ -191,7 +216,7 @@ object FlowAnalyzerForTheRest {
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z = newA.z(),
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src = SourceOfNZ.A)
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}),
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SLO -> (currentStatus => {
|
||||
SLO -> ((currentStatus, zpreg) => {
|
||||
val newA: Status[Int] = currentStatus.a.flatMap(v => if ((v & 0xff) == 0xff) Status.SingleFF else AnyStatus)
|
||||
currentStatus.copy(
|
||||
c = AnyStatus,
|
||||
@ -200,18 +225,19 @@ object FlowAnalyzerForTheRest {
|
||||
a0 = currentStatus.a0.flatMap(v => if (v) Status.SingleTrue else AnyStatus),
|
||||
n = newA.n(),
|
||||
z = newA.z(),
|
||||
src = SourceOfNZ.A)
|
||||
src = SourceOfNZ.A).setReg(zpreg, AnyStatus)
|
||||
}),
|
||||
EOR -> (currentStatus => {
|
||||
EOR -> ((currentStatus, zpreg) => {
|
||||
val newA: Status[Int] = (currentStatus.a <*> currentStatus.getReg(zpreg))(_ ^ _)
|
||||
currentStatus.copy(
|
||||
n = AnyStatus,
|
||||
z = AnyStatus,
|
||||
a = AnyStatus,
|
||||
a7 = AnyStatus,
|
||||
a0 = AnyStatus,
|
||||
src = SourceOfNZ.A)
|
||||
n = newA.n(),
|
||||
z = newA.z(),
|
||||
a = newA,
|
||||
a7 = newA.bit7,
|
||||
a0 = newA.bit0,
|
||||
src = SourceOfNZ.A).setReg(zpreg, AnyStatus)
|
||||
}),
|
||||
SRE -> (currentStatus => {
|
||||
SRE -> ((currentStatus, zpreg) => {
|
||||
currentStatus.copy(
|
||||
c = AnyStatus,
|
||||
n = AnyStatus,
|
||||
@ -219,9 +245,9 @@ object FlowAnalyzerForTheRest {
|
||||
a = AnyStatus,
|
||||
a7 = AnyStatus,
|
||||
a0 = AnyStatus,
|
||||
src = SourceOfNZ.A)
|
||||
src = SourceOfNZ.A).setReg(zpreg, AnyStatus)
|
||||
}),
|
||||
RLA -> (currentStatus => {
|
||||
RLA -> ((currentStatus, zpreg) => {
|
||||
currentStatus.copy(
|
||||
c = AnyStatus,
|
||||
n = AnyStatus,
|
||||
@ -229,9 +255,9 @@ object FlowAnalyzerForTheRest {
|
||||
a = AnyStatus,
|
||||
a7 = AnyStatus,
|
||||
a0 = AnyStatus,
|
||||
src = SourceOfNZ.A)
|
||||
src = SourceOfNZ.A).setReg(zpreg, AnyStatus)
|
||||
}),
|
||||
RRA -> (currentStatus => {
|
||||
RRA -> ((currentStatus, zpreg) => {
|
||||
currentStatus.copy(
|
||||
c = AnyStatus,
|
||||
n = AnyStatus,
|
||||
@ -240,9 +266,18 @@ object FlowAnalyzerForTheRest {
|
||||
a7 = AnyStatus,
|
||||
a0 = AnyStatus,
|
||||
z = AnyStatus,
|
||||
src = currentStatus.d.flatMap(dec => if (dec) AnyStatus else SourceOfNZ.A))
|
||||
src = currentStatus.d.flatMap(dec => if (dec) AnyStatus else SourceOfNZ.A)).setReg(zpreg, AnyStatus)
|
||||
}),
|
||||
ISC -> (currentStatus => {
|
||||
DCP -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(
|
||||
c = AnyStatus,
|
||||
n = AnyStatus,
|
||||
z = AnyStatus,
|
||||
src = AnyStatus).setReg(zpreg, r.map(n => (n - 1) & 0xff))
|
||||
}),
|
||||
ISC -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(
|
||||
c = AnyStatus,
|
||||
n = AnyStatus,
|
||||
@ -251,27 +286,61 @@ object FlowAnalyzerForTheRest {
|
||||
a7 = AnyStatus,
|
||||
a0 = AnyStatus,
|
||||
z = AnyStatus,
|
||||
src = currentStatus.d.flatMap(dec => if (dec) AnyStatus else SourceOfNZ.A))
|
||||
src = currentStatus.d.flatMap(dec => if (dec) AnyStatus else SourceOfNZ.A)).setReg(zpreg, r.map(n => (n + 1) & 0xff))
|
||||
}),
|
||||
ROL -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
ROR -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
ASL -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
LSR -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
INC -> (_.copy(n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
DEC -> (_.copy(n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
CMP -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
CPX -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
CPY -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
CPZ -> (_.copy(c = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
BIT -> (_.copy(v = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
TRB -> (_.copy(z = AnyStatus, src = AnyStatus)),
|
||||
TSB -> (_.copy(z = AnyStatus, src = AnyStatus)),
|
||||
JMP -> (_ => CpuStatus()),
|
||||
BRA -> (_ => CpuStatus()),
|
||||
BRL -> (_ => CpuStatus()),
|
||||
ROL -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = r.bit7, n = AnyStatus, z = AnyStatus, src = AnyStatus).setReg(zpreg, currentStatus.c.flatMap { c =>
|
||||
r.map(n => (n << 1) & 0xff | (if (c) 1 else 0))
|
||||
})
|
||||
}),
|
||||
ROR -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = r.bit0, n = AnyStatus, z = AnyStatus, src = AnyStatus).setReg(zpreg, currentStatus.c.flatMap { c =>
|
||||
r.map(n => (n >> 1) & 0x7f | (if (c) 0x80 else 0))
|
||||
})
|
||||
}),
|
||||
ASL -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = r.bit7, n = AnyStatus, z = AnyStatus, src = AnyStatus).setReg(zpreg, r.map(n => (n << 1) & 0xff))
|
||||
}),
|
||||
LSR -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = r.bit0, n = AnyStatus, z = AnyStatus, src = AnyStatus).setReg(zpreg, r.map(n => (n >> 1) & 0xff))
|
||||
}),
|
||||
INC -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(n = AnyStatus, z = AnyStatus, src = AnyStatus).setReg(zpreg, r.map(n => (n + 1) & 0xff))
|
||||
}),
|
||||
DEC -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(n = AnyStatus, z = AnyStatus, src = AnyStatus).setReg(zpreg, r.map(n => (n - 1) & 0xff))
|
||||
}),
|
||||
CMP -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = AnyStatus, n = AnyStatus, z = (currentStatus.a <*> r)(_==_), src = if (r.contains(0)) SourceOfNZ.A else AnyStatus)
|
||||
}),
|
||||
CPX -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = AnyStatus, n = AnyStatus, z = (currentStatus.x <*> r)(_==_), src = if (r.contains(0)) SourceOfNZ.X else AnyStatus)
|
||||
}),
|
||||
CPY -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = AnyStatus, n = AnyStatus, z = (currentStatus.y <*> r)(_==_), src = if (r.contains(0)) SourceOfNZ.Y else AnyStatus)
|
||||
}),
|
||||
CPZ -> ((currentStatus, zpreg) => {
|
||||
val r = currentStatus.getReg(zpreg)
|
||||
currentStatus.copy(c = AnyStatus, n = AnyStatus, z = (currentStatus.iz <*> r)(_==_), src = if (r.contains(0)) SourceOfNZ.Z else AnyStatus)
|
||||
}),
|
||||
BIT -> ((currentStatus, zpreg) => currentStatus.copy(v = AnyStatus, n = AnyStatus, z = AnyStatus, src = AnyStatus)),
|
||||
TRB -> ((currentStatus, zpreg) => currentStatus.copy(z = AnyStatus, src = AnyStatus).setReg(zpreg, AnyStatus)),
|
||||
TSB -> ((currentStatus, zpreg) => currentStatus.copy(z = AnyStatus, src = AnyStatus).setReg(zpreg, AnyStatus)),
|
||||
JMP -> ((_,_) => CpuStatus()),
|
||||
BRA -> ((_,_) => CpuStatus()),
|
||||
BRL -> ((_,_) => CpuStatus()),
|
||||
)
|
||||
|
||||
def hasDefinition(opcode: Opcode.Value): Boolean = map.contains(opcode)
|
||||
|
||||
def get(opcode: Opcode.Value): CpuStatus => CpuStatus = map(opcode)
|
||||
def get(opcode: Opcode.Value): (CpuStatus, Option[Int]) => CpuStatus = map(opcode)
|
||||
}
|
||||
|
||||
@ -547,6 +547,17 @@ case class MatchY(i: Int) extends AssemblyLinePattern {
|
||||
}
|
||||
}
|
||||
|
||||
case class MatchZpReg(i: Int, registerIndex: Int) extends AssemblyLinePattern {
|
||||
override def validate(needsFlowInfo: FlowInfoRequirement.Value): Unit =
|
||||
FlowInfoRequirement.assertForward(needsFlowInfo)
|
||||
|
||||
override def matchLineTo(ctx: AssemblyMatchingContext, flowInfo: FlowInfo, line: AssemblyLine): Boolean =
|
||||
flowInfo.statusBefore.reg(registerIndex) match {
|
||||
case SingleStatus(value) => ctx.addObject(i, value)
|
||||
case _ => false
|
||||
}
|
||||
}
|
||||
|
||||
case class HasA(value: Int) extends AssemblyLinePattern {
|
||||
override def validate(needsFlowInfo: FlowInfoRequirement.Value): Unit =
|
||||
FlowInfoRequirement.assertForward(needsFlowInfo)
|
||||
|
||||
@ -5,7 +5,7 @@ import millfork.assembly.mos.AddrMode._
|
||||
import millfork.assembly.AssemblyOptimization
|
||||
import millfork.assembly.mos.{AssemblyLine, Opcode, State}
|
||||
import millfork.env.{CompoundConstant, Constant, MathOperator}
|
||||
|
||||
import millfork.DecimalUtils.asDecimal
|
||||
/**
|
||||
* @author Karol Stasiak
|
||||
*/
|
||||
@ -27,6 +27,11 @@ object ZeropageRegisterOptimizations {
|
||||
code.init :+ AssemblyLine.immediate(LDA, product & 0xff)
|
||||
},
|
||||
|
||||
(Elidable & HasOpcode(JSR) & RefersTo("__mul_u8u8u8", 0) & MatchZpReg(4, 0) & MatchZpReg(5, 1)) ~~> { (code, ctx) =>
|
||||
val product = ctx.get[Int](4) * ctx.get[Int](5)
|
||||
code.init :+ AssemblyLine.immediate(LDA, product & 0xff)
|
||||
},
|
||||
|
||||
// TODO: constants other than power of 2:
|
||||
|
||||
(Elidable & HasOpcode(STA) & RefersTo("__reg", 0) & MatchAddrMode(0) & MatchParameter(1)) ~
|
||||
@ -171,41 +176,74 @@ object ZeropageRegisterOptimizations {
|
||||
})
|
||||
)
|
||||
|
||||
val PointlessLoad = new RuleBasedAssemblyOptimization("Pointless load from zeropage register",
|
||||
needsFlowInfo = FlowInfoRequirement.BothFlows,
|
||||
MultipleAssemblyRules((0 until 4).flatMap{ zpregIndex =>
|
||||
List(
|
||||
(Elidable & HasOpcode(LDA) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchA(4) &
|
||||
DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> (_ => Nil),
|
||||
(Elidable & HasOpcode(LDX) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchX(4) &
|
||||
DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> (_ => Nil),
|
||||
(Elidable & HasOpcode(LDY) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchY(4) &
|
||||
DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~> (_ => Nil),
|
||||
|
||||
private def parseNormalToDecimalValue(a: Long): Long = {
|
||||
if (a < 0) -parseNormalToDecimalValue(-a)
|
||||
var x = a
|
||||
var result = 0L
|
||||
var multiplier = 1L
|
||||
while (x > 0) {
|
||||
result += multiplier * (x % 16L)
|
||||
x /= 16L
|
||||
multiplier *= 10L
|
||||
}
|
||||
result
|
||||
}
|
||||
(Elidable & HasOpcode(LDA) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchX(4)) ~~> (_ => List(AssemblyLine.implied(TXA))),
|
||||
(Elidable & HasOpcode(LDA) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchY(4)) ~~> (_ => List(AssemblyLine.implied(TYA))),
|
||||
(Elidable & HasOpcode(LDX) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchA(4)) ~~> (_ => List(AssemblyLine.implied(TAX))),
|
||||
(Elidable & HasOpcode(LDY) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchA(4)) ~~> (_ => List(AssemblyLine.implied(TAY))),
|
||||
(Elidable & HasOpcode(LAX) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchX(4)) ~~> (_ => List(AssemblyLine.implied(TXA))),
|
||||
(Elidable & HasOpcode(LAX) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(4, zpregIndex) & MatchA(4)) ~~> (_ => List(AssemblyLine.implied(TAX))),
|
||||
|
||||
private def storeDecimalValueInNormalRespresentation(a: Long): Long = {
|
||||
if (a < 0) -storeDecimalValueInNormalRespresentation(-a)
|
||||
var x = a
|
||||
var result = 0L
|
||||
var multiplier = 1L
|
||||
while (x > 0) {
|
||||
result += multiplier * (x % 10L)
|
||||
x /= 10L
|
||||
multiplier *= 16L
|
||||
}
|
||||
result
|
||||
}
|
||||
(Elidable & HasOpcode(ADC) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(5, zpregIndex) & MatchA(4) & HasClear(State.D) & HasClear(State.C) &
|
||||
DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
|
||||
val sum = ctx.get[Int](4) + ctx.get[Int](5)
|
||||
List(AssemblyLine.immediate(LDA, sum & 0xff))
|
||||
},
|
||||
|
||||
private def asDecimal(a: Long, b: Long, f: (Long, Long) => Long): Long =
|
||||
storeDecimalValueInNormalRespresentation(f(parseNormalToDecimalValue(a), parseNormalToDecimalValue(b)))
|
||||
(Elidable & HasOpcode(SBC) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(5, zpregIndex) & MatchA(4) & HasClear(State.D) & HasSet(State.C) &
|
||||
DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
|
||||
val sum = ctx.get[Int](4) - ctx.get[Int](5)
|
||||
List(AssemblyLine.immediate(LDA, sum & 0xff))
|
||||
},
|
||||
|
||||
(Elidable & HasOpcode(AND) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(5, zpregIndex) & MatchA(4)) ~~> { (code, ctx) =>
|
||||
val sum = ctx.get[Int](4) & ctx.get[Int](5)
|
||||
List(AssemblyLine.immediate(LDA, sum & 0xff))
|
||||
},
|
||||
|
||||
(Elidable & HasOpcode(ORA) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(5, zpregIndex) & MatchA(4)) ~~> { (code, ctx) =>
|
||||
val sum = ctx.get[Int](4) | ctx.get[Int](5)
|
||||
List(AssemblyLine.immediate(LDA, sum & 0xff))
|
||||
},
|
||||
|
||||
(Elidable & HasOpcode(EOR) & RefersTo("__reg", zpregIndex) &
|
||||
MatchZpReg(5, zpregIndex) & MatchA(4)) ~~> { (code, ctx) =>
|
||||
val sum = ctx.get[Int](4) ^ ctx.get[Int](5)
|
||||
List(AssemblyLine.immediate(LDA, sum & 0xff))
|
||||
}
|
||||
)
|
||||
})
|
||||
)
|
||||
|
||||
val All: List[AssemblyOptimization[AssemblyLine]] = List(
|
||||
ConstantDecimalMath,
|
||||
ConstantMultiplication,
|
||||
DeadRegStore,
|
||||
DeadRegStoreFromFlow,
|
||||
PointlessLoad,
|
||||
StashInRegInsteadOfStack,
|
||||
)
|
||||
|
||||
|
||||
@ -93,6 +93,12 @@ object Status {
|
||||
case _ => AnyStatus
|
||||
}
|
||||
|
||||
def flatMap4[T, U, V, W, R](a: Status[T], b: Status[U], c: Status[V], d: Status[W])(f: (T, U, V, W) => Status[R]): Status[R] = (a, b, c, d) match {
|
||||
case (SingleStatus(t), SingleStatus(u), SingleStatus(v), SingleStatus(w)) => f(t, u, v, w)
|
||||
case (UnknownStatus, UnknownStatus, UnknownStatus, UnknownStatus) => UnknownStatus
|
||||
case _ => AnyStatus
|
||||
}
|
||||
|
||||
implicit class BoolStatusOps(val inner: Status[Boolean]) extends AnyVal {
|
||||
def withHiddenHi: Status[Boolean] = inner match {
|
||||
case SingleStatus(false) => inner
|
||||
@ -187,28 +193,28 @@ object Status {
|
||||
case _ => AnyStatus
|
||||
}
|
||||
|
||||
def adc(value: Int, carry: Status[Boolean], decimal: Status[Boolean]): Status[Int] = inner match {
|
||||
def adc(value: Int, carry: Status[Boolean], decimal: Status[Boolean]): (Status[Int], Status[Boolean]) = inner match {
|
||||
case SingleStatus(x) => decimal match {
|
||||
case SingleStatus(false) => carry match {
|
||||
case SingleStatus(true) => SingleStatus((x + value + 1) & 0xff)
|
||||
case SingleStatus(false) => SingleStatus((x + value) & 0xff)
|
||||
case _ => AnyStatus
|
||||
case SingleStatus(true) => SingleStatus((x + value + 1) & 0xff) -> SingleStatus((x.&(0xff) + value.&(0xff) + 1) > 0xff)
|
||||
case SingleStatus(false) => SingleStatus((x + value) & 0xff) -> SingleStatus((x.&(0xff) + value.&(0xff)) > 0xff)
|
||||
case _ => AnyStatus -> (if (value == 0) SingleFalse else AnyStatus)
|
||||
}
|
||||
case _ => AnyStatus
|
||||
case _ => AnyStatus -> AnyStatus
|
||||
}
|
||||
case _ => AnyStatus
|
||||
case _ => AnyStatus -> AnyStatus
|
||||
}
|
||||
|
||||
def sbc(value: Int, carry: Status[Boolean], decimal: Status[Boolean]): Status[Int] = inner match {
|
||||
def sbc(value: Int, carry: Status[Boolean], decimal: Status[Boolean]): (Status[Int], Status[Boolean]) = inner match {
|
||||
case SingleStatus(x) => decimal match {
|
||||
case SingleStatus(false) => carry match {
|
||||
case SingleStatus(true) => SingleStatus((x - value) & 0xff)
|
||||
case SingleStatus(false) => SingleStatus((x - value - 1) & 0xff)
|
||||
case _ => AnyStatus
|
||||
case SingleStatus(true) => SingleStatus((x - value) & 0xff) -> SingleStatus((x.&(0xff) - value.&(0xff)) >= 0)
|
||||
case SingleStatus(false) => SingleStatus((x - value - 1) & 0xff) -> SingleStatus((x.&(0xff) - value.&(0xff) - 1) >= 0)
|
||||
case _ => AnyStatus -> (if (value == 0) SingleTrue else AnyStatus)
|
||||
}
|
||||
case _ => AnyStatus
|
||||
case _ => AnyStatus -> AnyStatus
|
||||
}
|
||||
case _ => AnyStatus
|
||||
case _ => AnyStatus -> AnyStatus
|
||||
}
|
||||
|
||||
def adc_w(value: Int, carry: Status[Boolean], decimal: Status[Boolean]): Status[Int] = inner match {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user