From 985663083ac875cd75d5ad6a916eadbdf45d3eb8 Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Thu, 27 Dec 2018 20:46:50 +0100
Subject: [PATCH] 6502: Fix some optimizations

---
 .../mos/opt/AlwaysGoodOptimizations.scala      | 18 ++++++++++++++----
 .../opt/VariableToRegisterOptimization.scala   |  4 ++--
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala b/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
index 3a6cae78..bf6cefde 100644
--- a/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
+++ b/src/main/scala/millfork/assembly/mos/opt/AlwaysGoodOptimizations.scala
@@ -1923,25 +1923,25 @@ object AlwaysGoodOptimizations {
     needsFlowInfo = FlowInfoRequirement.JustLabels,
     (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
       (Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
-      (Linear & Not(ChangesA) & DoesntChangeMemoryAt(0, 1)).* ~
+      (Linear & Not(ChangesA) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
       (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
       code(1) :: code(0) :: code.drop(2)
     },
     (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
       (Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
-      (Linear & Not(ChangesX) & DoesntChangeMemoryAt(0, 1)).* ~
+      (Linear & Not(ChangesX) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
       (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
       code(1) :: code(0) :: code.drop(2)
     },
     (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
       (Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
-      (Linear & Not(ChangesY) & DoesntChangeMemoryAt(0, 1)).* ~
+      (Linear & Not(ChangesY) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
       (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
       code(1) :: code(0) :: code.drop(2)
     },
     (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
       (Elidable & HasOpcode(LDZ) & MatchAddrMode(0) & MatchParameter(1)) ~
-      (Linear & Not(ChangesIZ) & DoesntChangeMemoryAt(0, 1)).* ~
+      (Linear & Not(ChangesIZ) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
       (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
       code(1) :: code(0) :: code.drop(2)
     },
@@ -2659,5 +2659,15 @@ object AlwaysGoodOptimizations {
         code(3).copy(opcode = BCC))
     },
 
+    (Elidable & HasOpcode(TXA)) ~
+      (Elidable & HasOpcode(CMP) & DoesntMatterWhatItDoesWith(State.A) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~~> { code =>
+      List(code.last.copy(opcode = CPX))
+    },
+
+    (Elidable & HasOpcode(TYA)) ~
+      (Elidable & HasOpcode(CMP) & DoesntMatterWhatItDoesWith(State.A) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~~> { code =>
+      List(code.last.copy(opcode = CPY))
+    },
+
   )
 }
diff --git a/src/main/scala/millfork/assembly/mos/opt/VariableToRegisterOptimization.scala b/src/main/scala/millfork/assembly/mos/opt/VariableToRegisterOptimization.scala
index e1ba9d14..40d49b11 100644
--- a/src/main/scala/millfork/assembly/mos/opt/VariableToRegisterOptimization.scala
+++ b/src/main/scala/millfork/assembly/mos/opt/VariableToRegisterOptimization.scala
@@ -52,7 +52,7 @@ object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine]
   private val opcodesThatAlwaysPrecludeXAllocation = Set(
     JSR, STX, TXA, INX, DEX, CPX,
     LDX_W, STX_W, CPX_W, DEX_W, INX_W,
-    PHX, PLX,
+    PHX, PLX, PHX_W, PLX_W,
     SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS,
     HuSAX, SXY, TXY, TXY,
     BYTE,
@@ -61,7 +61,7 @@ object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine]
   private val opcodesThatAlwaysPrecludeYAllocation = Set(
     JSR, STY, TYA, INY, DEY, CPY,
     LDY_W, STY_W, CPY_W, DEY_W, INY_W,
-    PHY, PLY,
+    PHY, PLY, PHY_W, PLY_W,
     AHX, SHX, SHY, LAS, TAS,
     SAY, SXY, TXY, TYX,
     BYTE,