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Using (zp,X) addressing mode when appropriate

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This commit is contained in:
Karol Stasiak 2018-03-01 15:58:28 +01:00
parent 50b93db337
commit b3e96a0c6e
1 changed files with 26 additions and 1 deletions
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27
src/main/scala/millfork/assembly/opt/LaterOptimizations.scala
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@ -439,6 +439,30 @@ object LaterOptimizations {
}, },
) )
val UseIndexedX = new RuleBasedAssemblyOptimization("Using indexed-indirect addressing mode",
needsFlowInfo = FlowInfoRequirement.BothFlows,
(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
(Linear & Not(ConcernsY)).* ~
(Elidable & HasAddrMode(IndexedY) & HasX(0) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { code =>
code.tail.init :+ code.last.copy(addrMode = IndexedX)
},
(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
(Linear & Not(ConcernsY)).* ~
(Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(0xff) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code =>
code.tail.init ++ List(AssemblyLine.implied(INX), code.last.copy(addrMode = IndexedX))
},
(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
(Linear & Not(ConcernsY)).* ~
(Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(1) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code =>
code.tail.init ++ List(AssemblyLine.implied(DEX), code.last.copy(addrMode = IndexedX))
},
)
val All = List( val All = List(
DoubleLoadToDifferentRegisters, DoubleLoadToDifferentRegisters,
DoubleLoadToTheSameRegister, DoubleLoadToTheSameRegister,
@ -452,7 +476,8 @@ object LaterOptimizations {
UseZeropageAddressingMode) UseZeropageAddressingMode)
val Nmos = List( val Nmos = List(
IncrementThroughIndexRegisters IncrementThroughIndexRegisters,
UseIndexedX
) )
} }