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Z80: Full assembly support
This commit is contained in:
Karol Stasiak
parent
80efa95ba7
commit
b724ba9c6a
@ -21,12 +21,12 @@ case class IfFlagSet(flag: ZFlag.Value) extends ZRegisters
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case class IfFlagClear(flag: ZFlag.Value) extends ZRegisters
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case class OneRegister(register: ZRegister.Value) extends ZRegisters {
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if (register == ZRegister.MEM_IY_D || register == ZRegister.MEM_IX_D) ???
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// if (register == ZRegister.MEM_IY_D || register == ZRegister.MEM_IX_D) ???
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}
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case class TwoRegisters(target: ZRegister.Value, source: ZRegister.Value) extends ZRegisters {
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if (target == ZRegister.MEM_IY_D || target == ZRegister.MEM_IX_D) ???
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if (source == ZRegister.MEM_IY_D || source == ZRegister.MEM_IX_D) ???
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// if (target == ZRegister.MEM_IY_D || target == ZRegister.MEM_IX_D) ???
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// if (source == ZRegister.MEM_IY_D || source == ZRegister.MEM_IX_D) ???
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}
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case class OneRegisterOffset(register: ZRegister.Value, offset: Int) extends ZRegisters {
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@ -214,10 +214,10 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
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case ZRegister.I => "I"
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case ZRegister.MEM_ABS_8 => s"($parameter)"
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case ZRegister.MEM_ABS_16 => s"($parameter)"
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case ZRegister.IMM_8 => s"#$parameter"
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case ZRegister.IMM_16 => s"#$parameter"
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case ZRegister.MEM_IX_D => s"(IX,$offset)"
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case ZRegister.MEM_IY_D => s"(IY,$offset)"
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case ZRegister.IMM_8 => s"$parameter"
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case ZRegister.IMM_16 => s"$parameter"
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case ZRegister.MEM_IX_D => s"IX($offset)"
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case ZRegister.MEM_IY_D => s"IY($offset)"
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case ZRegister.MEM_HL => "(HL)"
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case ZRegister.MEM_BC => "(BC)"
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case ZRegister.MEM_DE => "(DE)"
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@ -236,7 +236,7 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
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case IM => s" IM $parameter"
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case EX_AF_AF => " EX AF,AF'"
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case EX_SP => registers match {
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case OneRegister(r) => s" EX (SP),${asAssemblyString(r)})"
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case OneRegister(r) => s" EX (SP),${asAssemblyString(r)}"
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case _ => ???
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}
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case JP | JR | DJNZ | CALL =>
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@ -277,7 +277,7 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
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}
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s" RES ${ZOpcodeClasses.RES_seq.indexOf(op)},$ps"
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case op =>
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val os = op.toString//.stripSuffix("_16")
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val os = op.toString.stripSuffix("_16")
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val ps = registers match {
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case NoRegisters => ""
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case IfFlagSet(ZFlag.P) => " PO"
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@ -86,10 +86,23 @@ class Z80Assembler(program: Program,
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case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), _, _) =>
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writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
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index + 1
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case ZLine(ADD_16, TwoRegisters(ix@(ZRegister.IX | ZRegister.IY), source@(ZRegister.IX | ZRegister.IY)), _, _)=>
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if (ix == source) {
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writeByte(bank, index, prefixByte(ix))
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writeByte(bank, index + 1, 9 + 16 * internalRegisterIndex(HL))
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index + 2
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} else {
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ErrorReporting.fatal("Cannot assemble " + instr)
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index
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}
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case ZLine(ADD_16, TwoRegisters(ix@(ZRegister.IX | ZRegister.IY), source), _, _) =>
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writeByte(bank, index, prefixByte(ix))
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writeByte(bank, index + 1, 9 + 16 * internalRegisterIndex(source))
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index + 2
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case ZLine(ADC_16, TwoRegisters(ZRegister.HL, reg), _, _) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x4a + 0x10 * internalRegisterIndex(reg))
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index + 2
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case ZLine(SBC_16, TwoRegisters(ZRegister.HL, reg), _, _) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x42 + 0x10 * internalRegisterIndex(reg))
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@ -108,6 +121,11 @@ class Z80Assembler(program: Program,
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writeByte(bank, index + 1, 0x2a)
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writeWord(bank, index + 2, param)
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index + 4
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case ZLine(LD_16, TwoRegisters(ZRegister.MEM_ABS_16, ix@(ZRegister.IX | ZRegister.IY)), param, _) =>
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writeByte(bank, index, prefixByte(ix))
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writeByte(bank, index + 1, 0x22)
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writeWord(bank, index + 2, param)
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index + 4
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case ZLine(LD_16, TwoRegisters(ZRegister.HL, ZRegister.MEM_ABS_16), param, _) =>
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writeByte(bank, index, 0x2a)
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writeWord(bank, index + 1, param)
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@ -168,8 +186,33 @@ class Z80Assembler(program: Program,
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writeByte(bank, index, 0xcb)
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writeByte(bank, index + 1, o.opcode + internalRegisterIndex(reg) * o.multiplier)
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index + 2
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case ZLine(op, OneRegisterOffset(ix@(ZRegister.MEM_IX_D | ZRegister.MEM_IY_D), offset), _, _) if cbOneRegister.contains(op) =>
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val o = cbOneRegister(op)
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writeByte(bank, index, prefixByte(ix))
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writeByte(bank, index + 1, 0xcb)
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writeByte(bank, index + 2, offset)
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index + 3
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case ZLine(LD, registers, _, _) =>
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registers match {
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case TwoRegisters(I, A) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x47)
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index + 2
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case TwoRegisters(A, I) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x57)
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index + 2
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case TwoRegisters(R, A) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x4f)
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index + 2
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case TwoRegisters(A, R) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x5f)
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index + 2
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case TwoRegisters(I | R, _) | TwoRegisters(_, I | R) =>
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ErrorReporting.fatal("Cannot assemble " + instr)
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index
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case TwoRegisters(reg, ZRegister.IMM_8) =>
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writeByte(bank, index, 6 + 8 * internalRegisterIndex(reg))
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writeByte(bank, index + 1, instr.parameter)
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@ -377,6 +420,20 @@ class Z80Assembler(program: Program,
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writeByte(bank, index, 0x10)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case ZLine(EX_SP, OneRegister(HL), _, _) =>
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writeByte(bank, index, 0xe3)
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index + 1
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case ZLine(EX_SP, OneRegister(IX), _, _) =>
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writeByte(bank, index, 0xdd)
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writeByte(bank, index + 1, 0xe3)
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index + 2
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case ZLine(EX_SP, OneRegister(IY), _, _) =>
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writeByte(bank, index, 0xfd)
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writeByte(bank, index + 1, 0xe3)
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index + 2
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case ZLine(EX_DE_HL, _, _, _) =>
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writeByte(bank, index, 0xeb)
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index + 1
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case _ =>
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ErrorReporting.fatal("Cannot assemble " + instr)
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index
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@ -61,13 +61,15 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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"SP" -> ZRegister.SP, "sp" -> ZRegister.SP,
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)
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private def param(allowAbsolute: Boolean): P[(ZRegister.Value, Option[Expression])] = asmExpressionWithParens.map {
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private def param(allowAbsolute: Boolean, allowRI: Boolean = false): P[(ZRegister.Value, Option[Expression])] = asmExpressionWithParens.map {
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case (VariableExpression("R" | "r"), false) if allowRI => (ZRegister.R, None)
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case (VariableExpression("I" | "i"), false) if allowRI => (ZRegister.I, None)
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case (VariableExpression(r), false) if toRegister.contains(r)=> (toRegister(r), None)
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case (VariableExpression("HL" | "hl"), true) => (ZRegister.MEM_HL, None)
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case (VariableExpression("BC" | "bc"), true) => (ZRegister.MEM_BC, None)
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case (VariableExpression("DE" | "de"), true) => (ZRegister.MEM_DE, None)
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case (FunctionCallExpression("IX" | "ix", List(o)), true) => (ZRegister.MEM_IX_D, Some(o))
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case (FunctionCallExpression("IY" | "iy", List(o)), true) => (ZRegister.MEM_IY_D, Some(o))
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case (FunctionCallExpression("IX" | "ix", List(o)), _) => (ZRegister.MEM_IX_D, Some(o))
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case (FunctionCallExpression("IY" | "iy", List(o)), _) => (ZRegister.MEM_IY_D, Some(o))
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case (e, true) if allowAbsolute => (ZRegister.MEM_ABS_8, Some(e))
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case (e, _) => (ZRegister.IMM_8, Some(e))
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}
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@ -147,7 +149,7 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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case (t, None, s, Some(v)) =>
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(op8, TwoRegisters(t, s), None, v)
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case (t, None, s, None) =>
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(op8, TwoRegisters(t, s), None, zero)
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(if (is16Bit(t)) op16 else op8, TwoRegisters(t, s), None, zero)
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case _ => ???
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}
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@ -162,6 +164,7 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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opcode: String <- identifier ~/ HWS
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tuple4/*: (ZOpcode.Value, ZRegisters, Option[Expression], Expression)*/ <- opcode.toUpperCase(Locale.ROOT) match {
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case "RST" => asmExpression.map((RST, NoRegisters, None, _))
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case "IM" => asmExpression.map((IM, NoRegisters, None, _))
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case "EI" => imm(EI)
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case "DI" => imm(DI)
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case "HALT" => imm(HALT)
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@ -169,9 +172,21 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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case "RETN" => imm(RETN)
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case "RETI" => imm(RETI)
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case "RET" => P(jumpConditionWithoutComma).map((RET, _, None, zero))
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case "CALL" => (jumpConditionWithComma~asmExpression).map{case (reg, param) => (CALL, reg, None, param)}
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case "JP" => (jumpConditionWithComma~asmExpression).map{case (reg, param) => (JP, reg, None, param)}
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case "JR" => (jumpConditionWithComma~asmExpression).map{case (reg, param) => (JR, reg, None, param)}
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case "CALL" => (jumpConditionWithComma ~ asmExpression).map { case (reg, param) => (CALL, reg, None, param) }
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case "JP" => (jumpConditionWithComma ~ param(allowAbsolute = true)).map {
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case (NoRegisters, (ZRegister.MEM_ABS_8, Some(VariableExpression("ix" | "IX")))) =>
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(JP, OneRegister(ZRegister.IX), None, zero)
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case (NoRegisters, (ZRegister.MEM_ABS_8, Some(VariableExpression("iy" | "IY")))) =>
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(JP, OneRegister(ZRegister.IY), None, zero)
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case (NoRegisters, (ZRegister.MEM_HL, _)) =>
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(JP, OneRegister(ZRegister.HL), None, zero)
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case (cond, (ZRegister.MEM_ABS_8 | ZRegister.IMM_8, Some(param))) =>
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(JP, cond, None, param)
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case _ =>
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ErrorReporting.error("Invalid parameters for JP", Some(pos))
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(NOP, NoRegisters, None, zero)
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}
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case "JR" => (jumpConditionWithComma ~ asmExpression).map{case (reg, param) => (JR, reg, None, param)}
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case "DJNZ" => asmExpression.map((DJNZ, NoRegisters, None, _))
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case "CP" => one8Register(CP)
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@ -226,9 +241,10 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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case "DAA" => imm(DAA)
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case "EXX" => imm(EXX)
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case "NOP" => imm(NOP)
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case "NEG" => imm(NEG)
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case "LDI" => imm(LDI)
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case "LDD" => imm(LDD)
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case "LDI" => imm(LDI) // TODO: Gameboy has a different LDI
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case "LDD" => imm(LDD) // TODO: Gameboy has a different LDD
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case "LDIR" => imm(LDIR)
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case "LDDR" => imm(LDDR)
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case "CPI" => imm(CPI)
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@ -245,6 +261,8 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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case "OUTDR" => imm(OUTDR)
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case "OTIR" => imm(OUTIR)
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case "OTDR" => imm(OUTDR)
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case "RLD" => imm(RLD)
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case "RRD" => imm(RRD)
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case "PUSH" => one16Register(PUSH)
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case "POP" => one16Register(POP)
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@ -275,7 +293,7 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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(NOP, NoRegisters, None, zero)
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}
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}
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case "EX" => (asmExpressionWithParens ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ asmExpressionWithParens).map { p: (Expression, Boolean, (Expression, Boolean)) =>
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case "EX" => (asmExpressionWithParens ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ asmExpressionWithParensOrApostrophe).map { p: (Expression, Boolean, (Expression, Boolean)) =>
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p match {
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case (VariableExpression("AF" | "af"), false, (VariableExpression("AF" | "af"), true)) =>
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(EX_AF_AF, NoRegisters, None, zero)
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@ -295,16 +313,16 @@ case class Z80Parser(filename: String, input: String, currentDirectory: String,
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}
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}
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case "LD" => (param(true) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(true)).map {
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case "LD" => (param(allowAbsolute = true, allowRI = true) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(allowAbsolute = true, allowRI = true)).map {
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case (r1, e1, (r2, e2)) => merge(LD, LD_16, skipTargetA = false)((r1, e1, r2, e2))
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}
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case "ADD" => (param(false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(false)).map {
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case "ADD" => (param(allowAbsolute = false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(allowAbsolute = false)).map {
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case (r1, e1, (r2, e2)) => merge(ADD, ADD_16, skipTargetA = true)((r1, e1, r2, e2))
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}
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case "ADC" => (param(false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(false)).map {
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case "ADC" => (param(allowAbsolute = false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(allowAbsolute = false)).map {
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case (r1, e1, (r2, e2)) => merge(ADC, ADC_16, skipTargetA = true)((r1, e1, r2, e2))
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}
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case "SBC" => (param(false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(false)).map {
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case "SBC" => (param(allowAbsolute = false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(allowAbsolute = false)).map {
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case (r1, e1, (r2, e2)) => merge(SBC, SBC_16, skipTargetA = true)((r1, e1, r2, e2))
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}
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563
src/test/scala/millfork/test/Z80AssemblySuite.scala
Normal file
563
src/test/scala/millfork/test/Z80AssemblySuite.scala
Normal file
@ -0,0 +1,563 @@
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package millfork.test
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import millfork.test.emu.EmuUnoptimizedZ80Run
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import org.scalatest.{FunSuite, Matchers}
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/**
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* @author Karol Stasiak
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*/
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class Z80AssemblySuite extends FunSuite with Matchers {
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test("Common I80 instructions") {
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EmuUnoptimizedZ80Run(
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"""
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| asm void main () {
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| ret
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| nop
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| ld bc,$101
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| ld (bc),a
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| inc bc
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| inc b
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| dec b
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| ld b,6
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| rlca
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| add hl,bc
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| ld a,(bc)
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| dec bc
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| inc c
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| dec c
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| ld c,$e
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| rrca
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| ld de,$1111
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| ld (de),a
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| inc de
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| inc d
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| dec d
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| ld d,$16
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| rla
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| jr main
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| add hl,de
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| ld a,(de)
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| dec de
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| inc e
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| dec e
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| ld e,$1e
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| rra
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| jr nz,main
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| ld hl,$2121
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| inc hl
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| inc h
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| dec h
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| ld h,$26
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| daa
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| jr z,main
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| add hl,hl
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| dec hl
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| inc l
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| dec l
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| ld l,$2e
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| cpl
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| jr nc,main
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| ld hl,$2121
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| ld ($fffe),a
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| inc sp
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| inc (hl)
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| dec (hl)
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| ld h,$26
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| scf
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| jr c,main
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| add hl,sp
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| ld a,($fffe)
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| dec sp
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| inc a
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| dec a
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| ld l,$2e
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| ccf
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| ld b,b
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| ld b,c
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| ld b,d
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| ld b,e
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| ld b,h
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| ld b,l
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| ld b,(hl)
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| ld b,a
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| ld c,b
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| ld c,c
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| ld c,d
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| ld c,e
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| ld c,h
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| ld c,l
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| ld c,(hl)
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| ld c,a
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| ld d,b
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| ld d,c
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| ld d,d
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| ld d,e
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| ld d,h
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| ld d,l
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| ld d,(hl)
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| ld d,a
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| ld e,b
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| ld e,c
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| ld e,d
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| ld e,e
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| ld e,h
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| ld e,l
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| ld e,(hl)
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| ld e,a
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| ld h,b
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| ld h,c
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| ld h,d
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| ld h,e
|
||||
| ld h,h
|
||||
| ld h,l
|
||||
| ld h,(hl)
|
||||
| ld h,a
|
||||
|
|
||||
| ld l,b
|
||||
| ld l,c
|
||||
| ld l,d
|
||||
| ld l,e
|
||||
| ld l,h
|
||||
| ld l,l
|
||||
| ld l,(hl)
|
||||
| ld l,a
|
||||
|
|
||||
| ld (hl),b
|
||||
| ld (hl),c
|
||||
| ld (hl),d
|
||||
| ld (hl),e
|
||||
| ld (hl),h
|
||||
| ld (hl),l
|
||||
| halt
|
||||
| ld (hl),a
|
||||
|
|
||||
| ld a,b
|
||||
| ld a,c
|
||||
| ld a,d
|
||||
| ld a,e
|
||||
| ld a,h
|
||||
| ld a,l
|
||||
| ld a,(hl)
|
||||
| ld a,a
|
||||
|
|
||||
| add a,b
|
||||
| add a,c
|
||||
| add a,d
|
||||
| add a,e
|
||||
| add a,h
|
||||
| add a,l
|
||||
| add a,(hl)
|
||||
| add a,a
|
||||
|
|
||||
| adc a,b
|
||||
| adc a,c
|
||||
| adc a,d
|
||||
| adc a,e
|
||||
| adc a,h
|
||||
| adc a,l
|
||||
| adc a,(hl)
|
||||
| adc a,a
|
||||
|
|
||||
| sub b
|
||||
| sub c
|
||||
| sub d
|
||||
| sub e
|
||||
| sub h
|
||||
| sub l
|
||||
| sub (hl)
|
||||
| sub a
|
||||
|
|
||||
| sbc a,b
|
||||
| sbc a,c
|
||||
| sbc a,d
|
||||
| sbc a,e
|
||||
| sbc a,h
|
||||
| sbc a,l
|
||||
| sbc a,(hl)
|
||||
| sbc a,a
|
||||
|
|
||||
| and b
|
||||
| and c
|
||||
| and d
|
||||
| and e
|
||||
| and h
|
||||
| and l
|
||||
| and (hl)
|
||||
| and a
|
||||
|
|
||||
| xor b
|
||||
| xor c
|
||||
| xor d
|
||||
| xor e
|
||||
| xor h
|
||||
| xor l
|
||||
| xor (hl)
|
||||
| xor a
|
||||
|
|
||||
| or b
|
||||
| or c
|
||||
| or d
|
||||
| or e
|
||||
| or h
|
||||
| or l
|
||||
| or (hl)
|
||||
| or a
|
||||
|
|
||||
| cp b
|
||||
| cp c
|
||||
| cp d
|
||||
| cp e
|
||||
| cp h
|
||||
| cp l
|
||||
| cp (hl)
|
||||
| cp a
|
||||
|
|
||||
| ret nz
|
||||
| pop bc
|
||||
| jp nz,main
|
||||
| jp main
|
||||
| call nz,main
|
||||
| push bc
|
||||
| add a,1
|
||||
| rst 0
|
||||
|
|
||||
| ret z
|
||||
| ret
|
||||
| jp z,main
|
||||
| call z,main
|
||||
| call main
|
||||
| adc a,1
|
||||
| rst 8
|
||||
|
|
||||
| ret nc
|
||||
| pop de
|
||||
| jp nc,main
|
||||
| call nc,main
|
||||
| push de
|
||||
| sub 1
|
||||
| rst $10
|
||||
|
|
||||
| ret c
|
||||
| jp c,main
|
||||
| call c,main
|
||||
| sbc a,1
|
||||
| rst $18
|
||||
|
|
||||
| pop hl
|
||||
| ex (sp),hl
|
||||
| push hl
|
||||
| and 1
|
||||
| rst $20
|
||||
|
|
||||
| jp (hl)
|
||||
| xor 1
|
||||
| rst $28
|
||||
|
|
||||
| pop af
|
||||
| di
|
||||
| push af
|
||||
| or 1
|
||||
| rst $30
|
||||
|
|
||||
| ld sp,hl
|
||||
| ei
|
||||
| cp 1
|
||||
| rst $38
|
||||
|
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
test("Intel 8080 instructions") {
|
||||
EmuUnoptimizedZ80Run(
|
||||
"""
|
||||
| asm void main () {
|
||||
| ret
|
||||
| ex af,af'
|
||||
| djnz main
|
||||
| ld ($fffe),hl
|
||||
| ld hl,($fffe)
|
||||
| out (1),a
|
||||
| exx
|
||||
| in a,(1)
|
||||
| ret po
|
||||
| jp po,main
|
||||
| call po,main
|
||||
| ret pe
|
||||
| jp pe,main
|
||||
| ex de,hl
|
||||
| call pe,main
|
||||
| ret p
|
||||
| jp p,main
|
||||
| call p,main
|
||||
| ret m
|
||||
| jp m,main
|
||||
| call m,main
|
||||
|
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
test("Extended I80 instructions") {
|
||||
EmuUnoptimizedZ80Run(
|
||||
"""
|
||||
| asm void main () {
|
||||
| ret
|
||||
|
|
||||
| reti
|
||||
|
|
||||
| rlc b
|
||||
| rlc c
|
||||
| rlc d
|
||||
| rlc e
|
||||
| rlc h
|
||||
| rlc l
|
||||
| rlc (hl)
|
||||
| rlc a
|
||||
|
|
||||
| rrc b
|
||||
| rrc c
|
||||
| rrc d
|
||||
| rrc e
|
||||
| rrc h
|
||||
| rrc l
|
||||
| rrc (hl)
|
||||
| rrc a
|
||||
|
|
||||
| rl b
|
||||
| rl c
|
||||
| rl d
|
||||
| rl e
|
||||
| rl h
|
||||
| rl l
|
||||
| rl (hl)
|
||||
| rl a
|
||||
|
|
||||
| rr b
|
||||
| rr c
|
||||
| rr d
|
||||
| rr e
|
||||
| rr h
|
||||
| rr l
|
||||
| rr (hl)
|
||||
| rr a
|
||||
|
|
||||
| sla b
|
||||
| sla c
|
||||
| sla d
|
||||
| sla e
|
||||
| sla h
|
||||
| sla l
|
||||
| sla (hl)
|
||||
| sla a
|
||||
|
|
||||
| sra b
|
||||
| sra c
|
||||
| sra d
|
||||
| sra e
|
||||
| sra h
|
||||
| sra l
|
||||
| sra (hl)
|
||||
| sra a
|
||||
|
|
||||
| srl b
|
||||
| srl c
|
||||
| srl d
|
||||
| srl e
|
||||
| srl h
|
||||
| srl l
|
||||
| srl (hl)
|
||||
| srl a
|
||||
|
|
||||
| bit 1,a
|
||||
| res 1,a
|
||||
| set 1,a
|
||||
| bit 1,(hl)
|
||||
| res 1,(hl)
|
||||
| set 1,(hl)
|
||||
|
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
test("Z80 instructions with IX") {
|
||||
EmuUnoptimizedZ80Run(
|
||||
"""
|
||||
| asm void main () {
|
||||
| ret
|
||||
| add a,ix(0)
|
||||
| adc a,ix(0)
|
||||
| sub ix(0)
|
||||
| sbc a,ix(0)
|
||||
| and ix(0)
|
||||
| xor ix(0)
|
||||
| or ix(0)
|
||||
| cp ix(0)
|
||||
|
|
||||
| rrc ix(0)
|
||||
| rr ix(0)
|
||||
| rlc ix(0)
|
||||
| rl ix(0)
|
||||
| sla ix(0)
|
||||
| sra ix(0)
|
||||
| srl ix(0)
|
||||
| sll ix(0)
|
||||
|
|
||||
| pop ix
|
||||
| push ix
|
||||
| add ix,sp
|
||||
| add ix,ix
|
||||
| add ix,de
|
||||
| add ix,bc
|
||||
| inc ix
|
||||
| dec ix
|
||||
| ld ix,3
|
||||
| ld ix,(3)
|
||||
| ld (3),ix
|
||||
| ex (sp),ix
|
||||
| jp (ix)
|
||||
| ld sp,ix
|
||||
| ld a,ix(0)
|
||||
| ld ix(0),a
|
||||
|
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
test("Z80 instructions with IY") {
|
||||
EmuUnoptimizedZ80Run(
|
||||
"""
|
||||
| asm void main () {
|
||||
| ret
|
||||
| add a,iy(0)
|
||||
| adc a,iy(0)
|
||||
| sub iy(0)
|
||||
| sbc a,iy(0)
|
||||
| and iy(0)
|
||||
| xor iy(0)
|
||||
| or iy(0)
|
||||
| cp iy(0)
|
||||
|
|
||||
| rrc iy(0)
|
||||
| rr iy(0)
|
||||
| rlc iy(0)
|
||||
| rl iy(0)
|
||||
| sla iy(0)
|
||||
| sra iy(0)
|
||||
| srl iy(0)
|
||||
| sll iy(0)
|
||||
|
|
||||
| pop iy
|
||||
| push iy
|
||||
| add iy,sp
|
||||
| add iy,iy
|
||||
| add iy,de
|
||||
| add iy,bc
|
||||
| inc iy
|
||||
| dec iy
|
||||
| ld iy,3
|
||||
| ld iy,(3)
|
||||
| ld (3),iy
|
||||
| ex (sp),iy
|
||||
| jp (iy)
|
||||
| ld sp,iy
|
||||
| ld a,iy(0)
|
||||
| ld iy(0),a
|
||||
|
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
test("Other Z80 instructions") {
|
||||
EmuUnoptimizedZ80Run(
|
||||
"""
|
||||
| asm void main () {
|
||||
| ret
|
||||
|
|
||||
| sll b
|
||||
| sll c
|
||||
| sll d
|
||||
| sll e
|
||||
| sll h
|
||||
| sll l
|
||||
| sll (hl)
|
||||
| sll a
|
||||
|
|
||||
| in b,(c)
|
||||
| out(c),b
|
||||
| sbc hl,bc
|
||||
| ld (34),bc
|
||||
| neg
|
||||
| retn
|
||||
| im 0
|
||||
| ld i,a
|
||||
| in c,(c)
|
||||
| out (c),c
|
||||
| adc hl,bc
|
||||
| ld bc,(7)
|
||||
| ld r,a
|
||||
| in d,(c)
|
||||
| out (c),d
|
||||
| sbc hl,de
|
||||
| ld (55),de
|
||||
| im 1
|
||||
| ld a,i
|
||||
| in e,(c)
|
||||
| out (c),e
|
||||
| adc hl,de
|
||||
| ld de,(33)
|
||||
| im 2
|
||||
| ld a,r
|
||||
|
|
||||
| in h,(c)
|
||||
| out (c),h
|
||||
| sbc hl,hl
|
||||
| rrd
|
||||
| in l,(c)
|
||||
| out (c),l
|
||||
| adc hl,hl
|
||||
| rld
|
||||
| sbc hl,sp
|
||||
| ld (34),sp
|
||||
| in a,(c)
|
||||
| out (c),a
|
||||
| adc hl,sp
|
||||
| ld sp,(345)
|
||||
|
|
||||
| ldi
|
||||
| cpi
|
||||
| ini
|
||||
| outi
|
||||
| ldd
|
||||
| cpd
|
||||
| ind
|
||||
| outd
|
||||
| ldir
|
||||
| cpir
|
||||
| inir
|
||||
| otir
|
||||
| lddr
|
||||
| cpdr
|
||||
| indr
|
||||
| otdr
|
||||
|
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
}
|
||||
@ -23,6 +23,10 @@ class EmuZ80Run(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimizatio
|
||||
|
||||
private val TooManyCycles: Long = 1000000
|
||||
|
||||
def apply(source: String): MemoryBank = {
|
||||
apply2(source)._2
|
||||
}
|
||||
|
||||
def apply2(source: String): (Timings, MemoryBank) = {
|
||||
Console.out.flush()
|
||||
Console.err.flush()
|
||||
|
||||
Loading…
Reference in New Issue
Block a user