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ZX Spectrum Next CPU support
This commit is contained in:
Karol Stasiak
parent
f7dd78e4c0
commit
d1058b6223
@ -31,6 +31,8 @@ if a line ends with a backslash character, the value continues to the next line.
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* `strictz80` (Z80 without illegal instructions)
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* `z80next` (Z80 core from ZX Spectrum Next)
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* `i8080` (Intel 8080)
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* `i8085` (Intel 8085)
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@ -25,6 +25,8 @@ Only instructions available on the current CPU architecture are available.
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Intel syntax does not support instructions that are unavailable on the 8080.
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Undocumented Z80 instructions are not supported, except for `SLL`.
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Not all ZX Spectrum Next are supported. `JP (C)`, `BSLA` and similar instructions are not supported.
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Labels have to be followed by a colon and they can optionally be on a separate line.
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Indentation is not important:
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@ -52,7 +52,7 @@ The following features are defined based on the chosen CPU and compilation optio
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* `CPUFEATURE_65C02`, `CPUFEATURE_65CE02`, `CPUFEATURE_HUC6280`, `CPUFEATURE_65816_EMULATION`, `CPUFEATURE_65816_NATIVE`,
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`CPUFEATURE_8080`, `CPUFEATURE_8085`, `CPUFEATURE_GAMEBOY`, `CPUFEATURE_Z80`,
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`CPUFEATURE_6502_ILLEGALS`, `CPUFEATURE_8085_ILLEGALS`, `CPUFEATURE_Z80_ILLEGALS` – 1 if given instruction subset is enabled, 0 otherwise
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`CPUFEATURE_6502_ILLEGALS`, `CPUFEATURE_8085_ILLEGALS`, `CPUFEATURE_Z80_ILLEGALS`, `CPUFEATURE_Z80_NEXT` – 1 if given instruction subset is enabled, 0 otherwise
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* `ENCODING_SAME` - 1 if the encodings `default` and `src` are the same, 0 otherwise.
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@ -4,9 +4,15 @@
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#endif
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#pragma zilog_syntax
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#if CPUFEATURE_Z80 || CPUFEATURE_GAMEBOY
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#if CPUFEATURE_Z80_NEXT
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inline asm byte __mul_u8u8u8() {
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? LD E,A
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? MUL
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? LD A, E
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? RET
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}
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#elseif CPUFEATURE_Z80 || CPUFEATURE_GAMEBOY
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//A = A * D
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noinline asm byte __mul_u8u8u8() {
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? LD E,A
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? LD A, 0
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@ -43,7 +43,7 @@ case class CompilationOptions(platform: Platform,
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EmitIntel8085Opcodes, EmitIntel8080Opcodes, UseIxForStack, UseIntelSyntaxForInput, UseIntelSyntaxForOutput)
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if (CpuFamily.forType(platform.cpu) != CpuFamily.I80) invalids ++= Set(
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EmitExtended80Opcodes, EmitZ80Opcodes, EmitSharpOpcodes, EmitEZ80Opcodes,
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EmitExtended80Opcodes, EmitZ80Opcodes, EmitSharpOpcodes, EmitEZ80Opcodes, EmitZ80NextOpcodes,
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UseIyForStack, UseIxForScratch, UseIyForScratch, UseShadowRegistersForInterrupts)
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if (CpuFamily.forType(platform.cpu) != CpuFamily.M6809) invalids ++= Set(
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@ -111,7 +111,7 @@ case class CompilationOptions(platform: Platform,
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}
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case CpuFamily.I80 =>
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if (flags(EmitIllegals)) {
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if (platform.cpu != Z80 && platform.cpu != Intel8085) {
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if (platform.cpu != Z80 && platform.cpu != Intel8085 && platform.cpu != Z80Next) {
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log.error("Illegal opcodes enabled for architecture that doesn't support them")
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}
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}
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@ -160,6 +160,11 @@ case class CompilationOptions(platform: Platform,
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log.error("Sharp LR35902 opcodes enabled for architecture that doesn't support them")
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}
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}
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if (flags(EmitZ80NextOpcodes)) {
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if (platform.cpu != Z80Next) {
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log.error("ZX Spectrum Next opcodes enabled for architecture that doesn't support them")
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}
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}
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if (flags(EmitExtended80Opcodes)) {
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if (platform.cpu != Sharp && !Z80Compatible(platform.cpu)) {
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log.error("Extended 8080-like opcodes enabled for architecture that doesn't support them")
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@ -221,6 +226,7 @@ case class CompilationOptions(platform: Platform,
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"CPUFEATURE_65816_NATIVE" -> toLong(flag(CompilationFlag.EmitNative65816Opcodes)),
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"CPUFEATURE_6502_ILLEGALS" -> toLong(platform.cpuFamily == CpuFamily.M6502 && flag(CompilationFlag.EmitIllegals)),
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"CPUFEATURE_Z80_ILLEGALS" -> toLong(flag(CompilationFlag.EmitZ80Opcodes) && flag(CompilationFlag.EmitIllegals)),
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"CPUFEATURE_Z80_NEXT" -> toLong(flag(CompilationFlag.EmitZ80NextOpcodes)),
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"CPUFEATURE_8085_ILLEGALS" -> toLong(flag(CompilationFlag.EmitIntel8080Opcodes) && flag(CompilationFlag.EmitIllegals)),
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"BIG_ENDIAN" -> toLong(Cpu.isBigEndian(platform.cpu)),
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"LITTLE_ENDIAN" -> toLong(!Cpu.isBigEndian(platform.cpu)),
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@ -276,7 +282,7 @@ object CpuFamily extends Enumeration {
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import Cpu._
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cpu match {
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case Mos | StrictMos | Ricoh | StrictRicoh | Cmos | HuC6280 | CE02 | Sixteen => M6502
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case Intel8080 | Intel8085 | StrictIntel8085 | Sharp | Z80 | StrictZ80 | EZ80 => I80
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case Intel8080 | Intel8085 | StrictIntel8085 | Sharp | Z80 | StrictZ80 | EZ80 | Z80Next => I80
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case Intel8086 | Intel80186 => I86
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case Cpu.Motorola6809 => M6809
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}
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@ -346,6 +352,10 @@ object Cpu extends Enumeration {
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* The Zilog eZ80 processor
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*/
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val EZ80: Cpu.Value = Value
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/**
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* The Z80 core from the ZX Spectrum Next
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*/
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val Z80Next: Cpu.Value = Value
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/**
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* The Sharp LR35902 processor
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*/
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@ -370,11 +380,11 @@ object Cpu extends Enumeration {
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/**
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* Processors that can run code for Zilog Z80
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*/
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val Z80Compatible: Set[Cpu.Value] = Set(Z80, StrictZ80, EZ80)
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val Z80Compatible: Set[Cpu.Value] = Set(Z80, StrictZ80, EZ80, Z80Next)
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/**
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* Processors that can run code for Intel 8080
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*/
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val Intel8080Compatible: Set[Cpu.Value] = Set(Intel8080, Intel8085, StrictIntel8085, Z80, StrictZ80, EZ80)
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val Intel8080Compatible: Set[Cpu.Value] = Set(Intel8080, Intel8085, StrictIntel8085, Z80, StrictZ80, EZ80, Z80Next)
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/**
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* Processors that can run code for Intel 8085
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*/
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@ -415,6 +425,8 @@ object Cpu extends Enumeration {
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i80AlwaysDefaultFlags ++ Set(EmitIntel8080Opcodes, EmitIntel8085Opcodes, UseIntelSyntaxForInput, UseIntelSyntaxForOutput)
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case StrictZ80 | Z80 =>
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i80AlwaysDefaultFlags ++ Set(EmitIntel8080Opcodes, EmitExtended80Opcodes, EmitZ80Opcodes, UseIxForStack, UseShadowRegistersForInterrupts)
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case Z80Next =>
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i80AlwaysDefaultFlags ++ Set(EmitIntel8080Opcodes, EmitExtended80Opcodes, EmitZ80Opcodes, UseIxForStack, UseShadowRegistersForInterrupts, EmitIllegals, EmitZ80NextOpcodes)
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case EZ80 =>
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i80AlwaysDefaultFlags ++ Set(EmitIntel8080Opcodes, EmitExtended80Opcodes, EmitZ80Opcodes, UseIxForStack, UseShadowRegistersForInterrupts, EmitEZ80Opcodes)
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case Sharp =>
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@ -456,6 +468,7 @@ object Cpu extends Enumeration {
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case "strict2a07" => StrictRicoh
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case "z80" => Z80
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case "strictz80" => Z80
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case "zx80next" => Z80Next
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// disabled for now:
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// case "ez80" => EZ80
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case "gameboy" => Sharp
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@ -504,7 +517,7 @@ object CompilationFlag extends Enumeration {
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EmitCmosOpcodes, EmitCmosNopOpcodes, EmitHudsonOpcodes, Emit65CE02Opcodes, EmitEmulation65816Opcodes, EmitNative65816Opcodes,
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PreventJmpIndirectBug, LargeCode, ReturnWordsViaAccumulator, SoftwareStack,
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// compilation options for I80
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EmitIntel8080Opcodes, EmitIntel8085Opcodes, EmitExtended80Opcodes, EmitZ80Opcodes, EmitEZ80Opcodes, EmitSharpOpcodes,
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EmitIntel8080Opcodes, EmitIntel8085Opcodes, EmitExtended80Opcodes, EmitZ80Opcodes, EmitEZ80Opcodes, EmitSharpOpcodes, EmitZ80NextOpcodes,
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UseShadowRegistersForInterrupts,
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UseIxForStack, UseIyForStack,
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UseIxForScratch, UseIyForScratch,
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@ -29,6 +29,8 @@ object ZOpcode extends Enumeration {
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LD_DESP, LD_DEHL, RRHL, RLDE, DSUB, RSTV, LHLX, SHLX,
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//sharp:
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LD_AHLI, LD_AHLD, LD_HLIA, LD_HLDA, SWAP, LDH_DA, LDH_AD, LDH_CA, LDH_AC, LD_HLSP, ADD_SP, STOP,
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// next:
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LDIX, LDWS, LDIRX, LDDX, LDDRX, LDPIRX, OUTINB, MUL, SWAPNIB, MIRROR, NEXTREG, PIXELDN, PIXELAD, SETAE, TEST,
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DISCARD_A, DISCARD_F, DISCARD_HL, DISCARD_BC, DISCARD_DE, DISCARD_IX, DISCARD_IY, CHANGED_MEM,
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LABEL, BYTE = Value
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}
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@ -69,19 +71,25 @@ object ZOpcodeClasses {
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val ChangesBCAlways: Set[ZOpcode.Value] = Set(
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INI, INIR, OUTI, OUTIR, IND, INDR, OUTD, OUTDR,
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LDI, LDIR, LDD, LDDR, CPI, CPIR, CPD, CPDR,
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LDIX, LDIRX, LDDX, LDDRX, LDPIRX,
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EXX, CALL, JR, JP, LABEL, DJNZ)
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val ChangesHLAlways: Set[ZOpcode.Value] = Set(
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INI, INIR, OUTI, OUTIR, IND, INDR, OUTD, OUTDR,
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LDI, LDIR, LDD, LDDR, CPI, CPIR, CPD, CPDR,
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LD_AHLI, LD_AHLD, LD_HLIA, LD_HLDA, LD_HLSP, DSUB,
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RRHL, LHLX,
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LDWS, LDIX, LDIRX, LDDX, LDDRX, LDPIRX, PIXELAD, PIXELDN, OUTINB,
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EXX, EX_DE_HL, CALL, JR, JP, LABEL)
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val ChangesDEAlways: Set[ZOpcode.Value] = Set(
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LDI, LDIR, LDD, LDDR,
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LD_DESP, LD_DEHL, RLDE,
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LDWS, LDIX, LDIRX, LDDX, LDDRX, LDPIRX, MUL,
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EXX, EX_DE_HL, CALL, JR, JP, LABEL)
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val ChangesOnlyRegister: Set[ZOpcode.Value] = Set(INC, DEC, INC_16, DEC_16, POP, EX_SP, IN_C, IN_IMM, RL, RR, RLC, RRC, SLA, SRA, SRL, SLL) ++ SET ++ RES
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val ChangesFirstRegister: Set[ZOpcode.Value] = Set(LD, LD_16, ADD_16, SBC_16)
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val ChangesAAlways: Set[ZOpcode.Value] = Set(DAA, ADD, ADC, SUB, SBC, XOR, OR, AND, LD_AHLI, LD_AHLD, RIM)
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val ChangesAAlways: Set[ZOpcode.Value] = Set(
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DAA, ADD, ADC, SUB, SBC, XOR, OR, AND, LD_AHLI, LD_AHLD, RIM,
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MIRROR, SETAE,
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)
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val NonLinear: Set[ZOpcode.Value] = Set(JP, JR, CALL, LABEL, BYTE, EXX, EX_DE_HL, EX_SP, EXX, RET, RETI, RETN, HALT, RST, RSTV)
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}
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@ -69,6 +69,8 @@ class Z80Assembler(program: Program,
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def requireIntel8085Illegals(): Unit = if (!options.flag(EmitIntel8085Opcodes) || !options.flag(EmitIllegals)) log.error("Unsupported instruction: " + instr)
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def requireNext(): Unit = if (!options.flag(EmitZ80NextOpcodes)) log.error("Unsupported instruction: " + instr)
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def useSharpOpcodes():Boolean = {
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if (!options.flag(EmitSharpOpcodes) && !options.flag(EmitIntel8080Opcodes))
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log.error("Cannot determine which variant to emit : " + instr)
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@ -144,6 +146,47 @@ class Z80Assembler(program: Program,
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, edImplieds(op))
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index + 2
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case ZLine0(op, NoRegisters, _) if nextEdImplieds.contains(op) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, nextEdImplieds(op))
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index + 2
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case ZLine0(ADD_16, TwoRegisters(r@(ZRegister.HL | ZRegister.BC | ZRegister.DE), ZRegister.A), _) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x33 - internalRegisterIndex(r))
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index + 2
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case ZLine0(ADD_16, TwoRegisters(r@(ZRegister.HL | ZRegister.BC | ZRegister.DE), ZRegister.IMM_16), nn) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x36 - internalRegisterIndex(r))
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writeWord(bank, index + 2, nn)
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index + 4
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case ZLine0(PUSH, OneRegister(ZRegister.IMM_16), nn) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x8A)
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writeByte(bank, index + 2, nn.hiByte)
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writeByte(bank, index + 3, nn.loByte)
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index + 4
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case ZLine0(TEST, OneRegister(ZRegister.IMM_8), nn) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x27)
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writeByte(bank, index + 2, nn)
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index + 3
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case ZLine0(NEXTREG, TwoRegisters(ZRegister.IMM_8, ZRegister.IMM_8), nn) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x91)
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writeWord(bank, index + 2, nn)
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index + 4
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case ZLine0(NEXTREG, TwoRegisters(ZRegister.IMM_8, ZRegister.A), nn) =>
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requireNext()
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, 0x92)
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writeByte(bank, index + 2, nn)
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index + 3
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case ZLine0(ADD_16, TwoRegisters(ZRegister.HL, source), _) =>
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writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
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index + 1
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@ -776,6 +819,7 @@ object Z80Assembler {
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val edImplieds: mutable.Map[ZOpcode.Value, Int] = mutable.Map[ZOpcode.Value, Int]()
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val oneRegister: mutable.Map[ZOpcode.Value, One] = mutable.Map[ZOpcode.Value, One]()
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val cbOneRegister: mutable.Map[ZOpcode.Value, One] = mutable.Map[ZOpcode.Value, One]()
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val nextEdImplieds: mutable.Map[ZOpcode.Value, Int] = mutable.Map[ZOpcode.Value, Int]()
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do {
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import ZOpcode._
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@ -846,6 +890,20 @@ object Z80Assembler {
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cbOneRegister(SLA) = One(0x20, 1)
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cbOneRegister(SRA) = One(0x28, 1)
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cbOneRegister(SRL) = One(0x38, 1)
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nextEdImplieds(LDIX) = 0xa4
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nextEdImplieds(LDWS) = 0xa5
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nextEdImplieds(LDIRX) = 0xb4
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nextEdImplieds(LDDX) = 0xb5
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nextEdImplieds(LDDRX) = 0xac
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nextEdImplieds(LDPIRX) = 0xbc
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nextEdImplieds(OUTINB) = 0x90
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nextEdImplieds(MUL) = 0xa4
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nextEdImplieds(SWAPNIB) = 0x23
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nextEdImplieds(MIRROR) = 0x24
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nextEdImplieds(PIXELDN) = 0x93
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nextEdImplieds(PIXELAD) = 0x94
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nextEdImplieds(SETAE) = 0x95
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} while (false)
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}
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@ -452,6 +452,20 @@ case class Z80Parser(filename: String,
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case (r1, e1, (r2, e2)) => merge(LD, LD_16, skipTargetA = false)((r1, e1, r2, e2))
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}
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case "ADD" => (param(allowAbsolute = false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(allowAbsolute = false)).map {
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case (ZRegister.HL, None, (ZRegister.A, None)) if options.flags(CompilationFlag.EmitZ80NextOpcodes) =>
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(ADD_16, TwoRegisters(ZRegister.HL, ZRegister.A), None, zero)
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case (ZRegister.DE, None, (ZRegister.A, None)) if options.flags(CompilationFlag.EmitZ80NextOpcodes) =>
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(ADD_16, TwoRegisters(ZRegister.DE, ZRegister.A), None, zero)
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case (ZRegister.BC, None, (ZRegister.A, None)) if options.flags(CompilationFlag.EmitZ80NextOpcodes) =>
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(ADD_16, TwoRegisters(ZRegister.BC, ZRegister.A), None, zero)
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case (ZRegister.HL, None, (ZRegister.IMM_8, Some(expr))) =>
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(ADD_16, TwoRegisters(ZRegister.HL, ZRegister.IMM_16), None, expr)
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case (ZRegister.DE, None, (ZRegister.IMM_8, Some(expr))) =>
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(ADD_16, TwoRegisters(ZRegister.DE, ZRegister.IMM_16), None, expr)
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case (ZRegister.BC, None, (ZRegister.IMM_8, Some(expr))) =>
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(ADD_16, TwoRegisters(ZRegister.BC, ZRegister.IMM_16), None, expr)
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case (ZRegister.SP, None, (ZRegister.IMM_8, Some(expr))) if options.flags(CompilationFlag.EmitSharpOpcodes) =>
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(ADD_SP, OneRegister(ZRegister.IMM_8), None, expr)
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case (r1, e1, (r2, e2)) => merge(ADD, ADD_16, skipTargetA = true)((r1, e1, r2, e2))
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@ -466,6 +480,28 @@ case class Z80Parser(filename: String,
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case "DSUB" => imm(DSUB)
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case "RSTV" => imm(RSTV)
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case "LDIX" => imm(LDIX)
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case "LDWS" => imm(LDWS)
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case "LDIRX" => imm(LDIRX)
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case "LDDX" => imm(LDDX)
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case "LDDRX" => imm(LDDRX)
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case "LDPIRX" => imm(LDPIRX)
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case "OUTINB" => imm(OUTINB)
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case "SWAPNIB" => imm(SWAPNIB)
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case "PIXELDN" => imm(PIXELDN)
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case "PIXELAD" => imm(PIXELAD)
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case "SETAE" => imm(SETAE)
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case "MUL" => (("D"|"d") ~ HWS ~ "," ~/ HWS ~ ("E" | "e")).?.map { _ => (MUL, NoRegisters, None, zero)}
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case "MIRROR" => ("A"|"a").?.map { _ => (MUL, NoRegisters, None, zero)}
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case "NEXTREG" =>(param(allowAbsolute = false) ~ HWS ~ position("comma").map(_ => ()) ~ "," ~/ HWS ~ param(allowAbsolute = false)).map {
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case (ZRegister.IMM_8, Some(n), (ZRegister.A, None)) => (NEXTREG, TwoRegisters(ZRegister.IMM_8, ZRegister.A), None, n)
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case (ZRegister.IMM_8, Some(n), (ZRegister.IMM_8, Some(v))) => (NEXTREG, TwoRegisters(ZRegister.IMM_8, ZRegister.IMM_8), None, SeparateBytesExpression(v, n))
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case _ =>
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log.error("Invalid parameters for NEXTREG", Some(pos))
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(NOP, NoRegisters, None, zero)
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}
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case "TEST" => one8Register(TEST)
|
||||
|
||||
case _ =>
|
||||
log.error("Unsupported opcode " + opcode, Some(pos))
|
||||
imm(NOP)
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
package millfork.test
|
||||
|
||||
import millfork.Cpu
|
||||
import millfork.test.emu.{EmuUnoptimizedCrossPlatformRun, EmuUnoptimizedIntel8080Run, EmuUnoptimizedIntel8085Run, EmuUnoptimizedSharpRun, EmuUnoptimizedZ80Run}
|
||||
import millfork.test.emu.{EmuUnoptimizedCrossPlatformRun, EmuUnoptimizedIntel8080Run, EmuUnoptimizedIntel8085Run, EmuUnoptimizedSharpRun, EmuUnoptimizedZ80NextRun, EmuUnoptimizedZ80Run}
|
||||
import org.scalatest.{FunSuite, Matchers}
|
||||
|
||||
/**
|
||||
@ -975,4 +975,41 @@ class Z80AssemblySuite extends FunSuite with Matchers {
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
test("Z80 Next instructions (Zilog syntax)") {
|
||||
EmuUnoptimizedZ80NextRun(
|
||||
"""
|
||||
| #pragma zilog_syntax
|
||||
| asm void main () {
|
||||
| ret
|
||||
| ldix
|
||||
| ldws
|
||||
| ldirx
|
||||
| lddx
|
||||
| lddrx
|
||||
| ldpirx
|
||||
| outinb
|
||||
| mul
|
||||
| mul d,e
|
||||
| add hl,a
|
||||
| add de,a
|
||||
| add bc,a
|
||||
| add hl,1
|
||||
| add de,2
|
||||
| add bc,3
|
||||
| swapnib
|
||||
| mirror
|
||||
| mirror a
|
||||
| push $5555
|
||||
| nextreg 1,2
|
||||
| nextreg 1,a
|
||||
| pixeldn
|
||||
| pixelad
|
||||
| setae
|
||||
| test 8
|
||||
| ret
|
||||
| }
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -22,6 +22,8 @@ object EmuUnoptimizedIntel8080Run extends EmuZ80Run(Cpu.Intel8080, Nil, Nil)
|
||||
|
||||
object EmuUnoptimizedIntel8085Run extends EmuZ80Run(Cpu.Intel8085, Nil, Nil)
|
||||
|
||||
object EmuUnoptimizedZ80NextRun extends EmuZ80Run(Cpu.Z80Next, Nil, Nil)
|
||||
|
||||
object EmuUnoptimizedIntel8086Run extends EmuI86Run(Nil, Nil)
|
||||
|
||||
object EmuUnoptimizedSharpRun extends EmuZ80Run(Cpu.Sharp, Nil, Nil)
|
||||
|
||||
@ -83,7 +83,8 @@ class EmuZ80Run(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimizatio
|
||||
CompilationFlag.OptimizeStdlib -> this.inline,
|
||||
CompilationFlag.OptimizeForSize -> this.optimizeForSize,
|
||||
CompilationFlag.SubroutineExtraction -> optimizeForSize,
|
||||
CompilationFlag.EmitIllegals -> (cpu == millfork.Cpu.Z80 || cpu == millfork.Cpu.Intel8085),
|
||||
CompilationFlag.EmitIllegals -> (cpu == millfork.Cpu.Z80 || cpu == millfork.Cpu.Intel8085 || cpu == millfork.Cpu.Z80Next),
|
||||
CompilationFlag.EmitZ80NextOpcodes -> (cpu == millfork.Cpu.Z80Next),
|
||||
CompilationFlag.LenientTextEncoding -> true)
|
||||
val options = CompilationOptions(platform, millfork.Cpu.defaultFlags(cpu).map(_ -> true).toMap ++ extraFlags, None, 0, Map(), JobContext(log, new LabelGenerator))
|
||||
println(cpu)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user