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Preliminary and partial machine code output for Z80
This commit is contained in:
Karol Stasiak
parent
893515b649
commit
dc3425f64e
@ -38,6 +38,14 @@ abstract class AbstractAssembler[T <: AbstractCode](private val program: Program
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mem.banks(bank).output(addr) = value.toByte
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}
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protected def writeByte(bank: String, addr: Int, value: Int): Unit = {
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mem.banks(bank).occupied(addr) = true
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mem.banks(bank).initialized(addr) = true
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mem.banks(bank).readable(addr) = true
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if ((value & 0xff) != value) ???
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mem.banks(bank).output(addr) = value.toByte
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}
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def writeByte(bank: String, addr: Int, value: Constant): Unit = {
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mem.banks(bank).occupied(addr) = true
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mem.banks(bank).initialized(addr) = true
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@ -1,10 +1,11 @@
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package millfork.output
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import millfork.{CompilationOptions, Platform}
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import millfork.assembly.z80.ZLine
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import millfork.assembly.z80._
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import millfork.compiler.z80.Z80Compiler
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import millfork.env.{Environment, NormalFunction}
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import millfork.node.{NiceFunctionProperty, Program}
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import millfork.env._
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import millfork.error.ErrorReporting
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import millfork.node.{NiceFunctionProperty, Program, ZRegister}
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import scala.collection.mutable
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@ -16,9 +17,301 @@ class Z80Assembler(program: Program,
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platform: Platform) extends AbstractAssembler[ZLine](program, rootEnv, platform, Z80InliningCalculator, Z80Compiler) {
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override def performFinalOptimizationPass(f: NormalFunction, actuallyOptimize: Boolean, options: CompilationOptions, code: List[ZLine]): List[ZLine] = code
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private def internalRegisterIndex(reg: ZRegister.Value): Int = reg match {
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case ZRegister.B => 0
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case ZRegister.C => 1
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case ZRegister.D => 2
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case ZRegister.E => 3
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case ZRegister.H => 4
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case ZRegister.L => 5
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case ZRegister.MEM_HL => 6
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case ZRegister.MEM_IX_D => 6
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case ZRegister.MEM_IY_D => 6
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case ZRegister.A => 7
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case ZRegister.BC => 0
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case ZRegister.DE => 1
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case ZRegister.HL => 2
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case ZRegister.AF => 3
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case ZRegister.SP => 3
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}
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private def internalArithmeticIndex(opcode: ZOpcode.Value): Int = {
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import ZOpcode._
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opcode match {
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case ADD => 0x80
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case ADC => 0x88
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case SUB => 0x90
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case SBC => 0x98
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case AND => 0xa0
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case XOR => 0xa8
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case OR => 0xb0
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case CP => 0xb8
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}
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}
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override def emitInstruction(bank: String, options: CompilationOptions, index: Int, instr: ZLine): Int = {
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// TODO
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index
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import millfork.assembly.z80.ZOpcode._
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import Z80Assembler._
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instr match {
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case ZLine(LABEL, NoRegisters, MemoryAddressConstant(Label(labelName)), _) =>
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labelMap(labelName) = index
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index
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case ZLine(BYTE, NoRegisters, param, _) =>
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writeByte(bank, index, param)
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index + 1
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case ZLine(DISCARD_F | DISCARD_HL | DISCARD_BCDEIX | DISCARD_A, NoRegisters, _, _) =>
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index
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case ZLine(LABEL | BYTE | DISCARD_F | DISCARD_HL | DISCARD_BCDEIX | DISCARD_A, _, _, _) =>
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???
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case ZLine(op, NoRegisters, _, _) if implieds.contains(op) =>
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writeByte(bank, index, implieds(op))
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index + 1
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case ZLine(op, NoRegisters, _, _) if edImplieds.contains(op) =>
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writeByte(bank, index, 0xed)
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writeByte(bank, index + 1, edImplieds(op))
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index + 2
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case ZLine(ADD_16, TwoRegisters(ZRegister.HL, source), param, _) =>
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writeByte(bank, index, 9 + 16 * internalRegisterIndex(source))
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index + 1
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case ZLine(LD_16, TwoRegisters(target, ZRegister.IMM_16), param, _) =>
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writeByte(bank, index, 1 + 16 * internalRegisterIndex(target))
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(LD_16, TwoRegisters(ZRegister.HL, ZRegister.MEM_ABS_16), param, _) =>
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writeByte(bank, index, 0x2a)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(LD_16, TwoRegisters(ZRegister.MEM_ABS_16, ZRegister.HL), param, _) =>
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writeByte(bank, index, 0x22)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(op, OneRegister(ZRegister.IMM_8), param, _) if immediates.contains(op) =>
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val o = immediates(op)
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writeByte(bank, index, o)
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writeByte(bank, index + 1, param)
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index + 2
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case ZLine(op, OneRegister(ZRegister.MEM_IX_D), _, _) if oneRegister.contains(op) =>
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val o = oneRegister(op)
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writeByte(bank, index, 0xdd)
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writeByte(bank, index + 1, o.opcode + internalRegisterIndex(ZRegister.MEM_HL) * o.multiplier)
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writeByte(bank, index + 2, instr.parameter)
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index + 3
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case ZLine(op, OneRegister(ZRegister.MEM_IY_D), _, _) if oneRegister.contains(op) =>
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val o = oneRegister(op)
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writeByte(bank, index, 0xfd)
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writeByte(bank, index + 1, o.opcode + internalRegisterIndex(ZRegister.MEM_HL) * o.multiplier)
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writeByte(bank, index + 2, instr.parameter)
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index + 3
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case ZLine(op, OneRegister(ZRegister.IX), _, _) if oneRegister.contains(op) =>
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val o = oneRegister(op)
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writeByte(bank, index, 0xdd)
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writeByte(bank, index + 1, o.opcode + internalRegisterIndex(ZRegister.HL) * o.multiplier)
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writeByte(bank, index + 2, instr.parameter)
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index + 3
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case ZLine(op, OneRegister(ZRegister.IY), _, _) if oneRegister.contains(op) =>
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val o = oneRegister(op)
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writeByte(bank, index, 0xfd)
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writeByte(bank, index + 1, o.opcode + internalRegisterIndex(ZRegister.HL) * o.multiplier)
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writeByte(bank, index + 2, instr.parameter)
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index + 3
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case ZLine(op, OneRegister(reg), _, _) if reg != ZRegister.IMM_8 && oneRegister.contains(op) =>
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val o = oneRegister(op)
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writeByte(bank, index, o.opcode + internalRegisterIndex(reg) * o.multiplier)
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index + 1
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case ZLine(op, OneRegister(reg), _, _) if cbOneRegister.contains(op) =>
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val o = cbOneRegister(op)
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writeByte(bank, index, 0xcb)
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writeByte(bank, index + 1, o.opcode + internalRegisterIndex(reg) * o.multiplier)
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index + 2
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case ZLine(LD, registers, _, _) =>
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registers match {
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case TwoRegisters(reg, ZRegister.IMM_8) =>
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writeByte(bank, index, 6 + 8 * internalRegisterIndex(reg))
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writeByte(bank, index + 1, instr.parameter)
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index + 2
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case TwoRegisters(ZRegister.A, ZRegister.MEM_ABS_8) =>
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writeByte(bank, index, 0x3a)
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writeWord(bank, index + 1, instr.parameter)
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index + 3
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case TwoRegisters(ZRegister.MEM_ABS_8, ZRegister.A) =>
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writeByte(bank, index, 0x32)
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writeWord(bank, index + 1, instr.parameter)
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index + 3
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case TwoRegisters(ZRegister.MEM_BC, ZRegister.A) =>
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writeByte(bank, index, 2)
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index + 1
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case TwoRegisters(ZRegister.MEM_DE, ZRegister.A) =>
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writeByte(bank, index, 0x12)
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index + 1
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case TwoRegisters(ZRegister.A, ZRegister.MEM_BC) =>
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writeByte(bank, index, 0x0a)
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index + 1
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case TwoRegisters(ZRegister.A, ZRegister.MEM_DE) =>
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writeByte(bank, index, 0x1a)
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index + 1
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case TwoRegisters(ZRegister.MEM_IX_D, source) =>
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writeByte(bank, index, 0xdd)
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writeByte(bank, index + 1, 0x40 + internalRegisterIndex(source) + internalRegisterIndex(ZRegister.MEM_HL) * 8)
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writeByte(bank, index + 1, instr.parameter)
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index + 3
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case TwoRegisters(ZRegister.MEM_IY_D, source) =>
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writeByte(bank, index, 0xfd)
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writeByte(bank, index + 1, 0x40 + internalRegisterIndex(source) + internalRegisterIndex(ZRegister.MEM_HL) * 8)
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writeByte(bank, index + 1, instr.parameter)
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index + 3
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case TwoRegisters(target, ZRegister.MEM_IX_D) =>
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writeByte(bank, index, 0xdd)
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writeByte(bank, index, 0x40 + internalRegisterIndex(ZRegister.MEM_HL) + internalRegisterIndex(target) * 8)
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writeByte(bank, index + 1, instr.parameter)
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index + 3
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case TwoRegisters(target, ZRegister.MEM_IY_D) =>
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writeByte(bank, index, 0xfd)
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writeByte(bank, index, 0x40 + internalRegisterIndex(ZRegister.MEM_HL) + internalRegisterIndex(target) * 8)
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writeByte(bank, index + 1, instr.parameter)
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index + 3
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case TwoRegisters(target, source) =>
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writeByte(bank, index, 0x40 + internalRegisterIndex(source) + internalRegisterIndex(target) * 8)
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index + 1
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case TwoRegisters(target, source) =>
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writeByte(bank, index, 0x40 + internalRegisterIndex(source) + internalRegisterIndex(target) * 8)
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index + 1
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}
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case ZLine(CALL, NoRegisters, param, _) =>
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writeByte(bank, index, 0xcd)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagClear(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0xc4)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagClear(ZFlag.C), param, _) =>
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writeByte(bank, index, 0xd4)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagClear(ZFlag.P), param, _) =>
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writeByte(bank, index, 0xe4)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagClear(ZFlag.S), param, _) =>
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writeByte(bank, index, 0xf4)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagSet(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0xcc)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagSet(ZFlag.C), param, _) =>
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writeByte(bank, index, 0xdc)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagSet(ZFlag.P), param, _) =>
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writeByte(bank, index, 0xec)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(CALL, IfFlagSet(ZFlag.S), param, _) =>
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writeByte(bank, index, 0xfc)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, NoRegisters, param, _) =>
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writeByte(bank, index, 0xc3)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagClear(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0xc2)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagClear(ZFlag.C), param, _) =>
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writeByte(bank, index, 0xd2)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagClear(ZFlag.P), param, _) =>
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writeByte(bank, index, 0xe2)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagClear(ZFlag.S), param, _) =>
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writeByte(bank, index, 0xf2)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagSet(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0xca)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagSet(ZFlag.C), param, _) =>
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writeByte(bank, index, 0xda)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagSet(ZFlag.P), param, _) =>
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writeByte(bank, index, 0xea)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(JP, IfFlagSet(ZFlag.S), param, _) =>
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writeByte(bank, index, 0xfa)
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writeWord(bank, index + 1, param)
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index + 3
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case ZLine(RET, IfFlagClear(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0xc0)
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index + 1
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case ZLine(RET, IfFlagClear(ZFlag.C), param, _) =>
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writeByte(bank, index, 0xd0)
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index + 1
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case ZLine(RET, IfFlagClear(ZFlag.P), param, _) =>
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writeByte(bank, index, 0xe0)
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index + 1
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case ZLine(RET, IfFlagClear(ZFlag.S), param, _) =>
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writeByte(bank, index, 0xf0)
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index + 1
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case ZLine(RET, IfFlagSet(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0xc8)
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index + 1
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case ZLine(RET, IfFlagSet(ZFlag.C), param, _) =>
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writeByte(bank, index, 0xd8)
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index + 1
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case ZLine(RET, IfFlagSet(ZFlag.P), param, _) =>
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writeByte(bank, index, 0xe8)
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index + 1
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case ZLine(RET, IfFlagSet(ZFlag.S), param, _) =>
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writeByte(bank, index, 0xf8)
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index + 1
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case ZLine(JR, IfFlagClear(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0x20)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case ZLine(JR, IfFlagClear(ZFlag.C), param, _) =>
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writeByte(bank, index, 0x30)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case ZLine(JR, IfFlagSet(ZFlag.Z), param, _) =>
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writeByte(bank, index, 0x28)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case ZLine(JR, IfFlagSet(ZFlag.C), param, _) =>
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writeByte(bank, index, 0x38)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case ZLine(JR, NoRegisters, param, _) =>
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writeByte(bank, index, 0x18)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case ZLine(DJNZ, NoRegisters, param, _) =>
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writeByte(bank, index, 0x10)
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writeByte(bank, index + 1, AssertByte(param - index - 2))
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index + 2
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case _ =>
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ErrorReporting.fatal("Cannot assemble " + instr)
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index
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}
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}
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override def injectLabels(labelMap: Map[String, Int], code: List[ZLine]): List[ZLine] = code // TODO
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@ -27,6 +320,85 @@ class Z80Assembler(program: Program,
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// do nothing yet
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}
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}
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object Z80Assembler {
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}
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case class One(opcode: Int, multiplier: Int)
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val implieds = mutable.Map[ZOpcode.Value, Int]()
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val immediates = mutable.Map[ZOpcode.Value, Int]()
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val edImplieds = mutable.Map[ZOpcode.Value, Int]()
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val oneRegister = mutable.Map[ZOpcode.Value, One]()
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val cbOneRegister = mutable.Map[ZOpcode.Value, One]()
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do {
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import ZOpcode._
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implieds(NOP) = 0
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implieds(DAA) = 0x27
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implieds(SCF) = 0x37
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implieds(CPL) = 0x37
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implieds(CCF) = 0x3f
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implieds(EX_AF_AF) = 8
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implieds(RET) = 0xc9
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implieds(EXX) = 0xd9
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implieds(EI) = 0xfb
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implieds(DI) = 0xf3
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implieds(HALT) = 0x76
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immediates(ADD) = 0xc6
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immediates(ADC) = 0xce
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immediates(SUB) = 0xd6
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immediates(SBC) = 0xde
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immediates(AND) = 0xe6
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immediates(XOR) = 0xee
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immediates(OR) = 0xf6
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immediates(CP) = 0xfe
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edImplieds(NEG) = 0x44
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edImplieds(RETI) = 0x4d
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edImplieds(RETN) = 0x45
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edImplieds(LDI) = 0xa0
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edImplieds(LDIR) = 0xb0
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edImplieds(CPI) = 0xa1
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edImplieds(CPIR) = 0xb1
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edImplieds(INI) = 0xa2
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edImplieds(INIR) = 0xb2
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edImplieds(OUTI) = 0xa3
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edImplieds(OUTIR) = 0xb3
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edImplieds(LDD) = 0xa8
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edImplieds(LDDR) = 0xb8
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edImplieds(CPD) = 0xa9
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edImplieds(CPDR) = 0xb9
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edImplieds(IND) = 0xaa
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edImplieds(INDR) = 0xba
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edImplieds(OUTD) = 0xab
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edImplieds(OUTDR) = 0xbb
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oneRegister(ADD) = One(0x80, 1)
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oneRegister(ADC) = One(0x88, 1)
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oneRegister(SUB) = One(0x90, 1)
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oneRegister(SBC) = One(0x98, 1)
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oneRegister(AND) = One(0xa0, 1)
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oneRegister(XOR) = One(0xa8, 1)
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oneRegister(OR) = One(0xb0, 1)
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oneRegister(CP) = One(0xb8, 1)
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oneRegister(INC) = One(4, 8)
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oneRegister(DEC) = One(5, 8)
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oneRegister(INC_16) = One(3, 0x10)
|
||||
oneRegister(DEC_16) = One(0xb, 0x10)
|
||||
|
||||
oneRegister(POP) = One(0xc1, 0x10)
|
||||
oneRegister(PUSH) = One(0xc5, 0x10)
|
||||
|
||||
cbOneRegister(RL) = One(0x10, 1)
|
||||
cbOneRegister(RLC) = One(0, 1)
|
||||
cbOneRegister(RR) = One(8, 1)
|
||||
cbOneRegister(RRC) = One(0x18, 1)
|
||||
cbOneRegister(SLA) = One(0x20, 1)
|
||||
cbOneRegister(SRA) = One(0x28, 1)
|
||||
cbOneRegister(SLL) = One(0x30, 1)
|
||||
cbOneRegister(SRL) = One(0x38, 1)
|
||||
} while (false)
|
||||
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user