From f937355c54a7c56e87445d2cd69b9afba7bd1387 Mon Sep 17 00:00:00 2001 From: Karol Stasiak Date: Tue, 7 Aug 2018 17:35:40 +0200 Subject: [PATCH] 6502: Fix word addition if zpreg is larger than 2 --- .../scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala b/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala index 5bfada56..d640e721 100644 --- a/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala +++ b/src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala @@ -67,7 +67,7 @@ object PseudoregisterBuiltIns { } val b = ctx.env.get[Type]("byte") val w = ctx.env.get[Type]("word") - val reg = ctx.env.get[VariableInMemory]("__reg") + val reg = ctx.env.get[VariableInMemory]("__reg.loword") // TODO: smarter on 65816 val op = if (subtract) SBC else ADC val prepareCarry = AssemblyLine.implied(if (subtract) SEC else CLC)