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6502: optimize variable pointers
This commit is contained in:
Karol Stasiak
parent
2a233930e8
commit
ffff51dee9
@ -2662,6 +2662,101 @@ object AlwaysGoodOptimizations {
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val last = code.last
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code.init :+ last.copy(parameter = NumericConstant(addr, 2), addrMode = if (last.addrMode == IndexedZ) Absolute else AbsoluteY)
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},
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(HasOpcode(STX) & MatchX(1) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(5)) ~
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(HasOpcode(STA) & MatchA(0) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(4)) ~
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Where(ctx => {
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ctx.addObject(3, ZeroPage)
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(ctx.get[Constant](4) + 1).quickSimplify == ctx.get[Constant](5)
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}) ~
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(Linear & DoesNotConcernMemoryAt(3, 4) & DoesNotConcernMemoryAt(3, 5)).* ~
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Where(ctx => {
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val lo = ctx.get[Int](0) & 0xff
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val hi = ctx.get[Int](1) & 0xff
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ctx.addObject(2, hi * 256 + lo)
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true
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}) ~
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(Elidable & MatchParameter(4) & HasAddrModeIn(IndexedZ, IndexedY) & MatchAddrMode(9)) ~
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Where(ctx => {
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ctx.get[AddrMode.Value](9) == IndexedY || !ctx.compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)
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}) ~~> { (code, ctx) =>
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val addr = ctx.get[Int](2)
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val last = code.last
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code.init :+ last.copy(parameter = NumericConstant(addr, 2), addrMode = if (last.addrMode == IndexedZ) Absolute else AbsoluteY)
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},
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(HasOpcode(LDA) & MatchImmediate(0)) ~
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(HasOpcode(LDX) & MatchImmediate(1)) ~
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(HasOpcode(STX) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(5)) ~
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(HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(4)) ~
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Where(ctx => {
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ctx.addObject(3, ZeroPage)
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(ctx.get[Constant](4) + 1).quickSimplify == ctx.get[Constant](5)
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}) ~
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(Linear & DoesNotConcernMemoryAt(3, 4) & DoesNotConcernMemoryAt(3, 5)).* ~
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Where(ctx => {
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val lo = ctx.get[Constant](0)
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val hi = ctx.get[Constant](1)
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ctx.addObject(2, (hi.asl(8) + lo).quickSimplify)
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true
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}) ~
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(Elidable & MatchParameter(4) & HasAddrModeIn(IndexedZ, IndexedY) & MatchAddrMode(9)) ~
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Where(ctx => {
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ctx.get[AddrMode.Value](9) == IndexedY || !ctx.compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)
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}) ~~> { (code, ctx) =>
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val addr = ctx.get[Constant](2)
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val last = code.last
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code.init :+ last.copy(parameter = addr, addrMode = if (last.addrMode == IndexedZ) Absolute else AbsoluteY)
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},
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(HasOpcode(LDA) & MatchImmediate(0)) ~
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(HasOpcode(LDX) & MatchImmediate(1)) ~
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(HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(4)) ~
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(HasOpcode(STX) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(5)) ~
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Where(ctx => {
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ctx.addObject(3, ZeroPage)
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(ctx.get[Constant](4) + 1).quickSimplify == ctx.get[Constant](5)
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}) ~
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(Linear & DoesNotConcernMemoryAt(3, 4) & DoesNotConcernMemoryAt(3, 5)).* ~
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Where(ctx => {
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val lo = ctx.get[Constant](0)
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val hi = ctx.get[Constant](1)
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ctx.addObject(2, (hi.asl(8) + lo).quickSimplify)
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true
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}) ~
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(Elidable & MatchParameter(4) & HasAddrModeIn(IndexedZ, IndexedY) & MatchAddrMode(9)) ~
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Where(ctx => {
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ctx.get[AddrMode.Value](9) == IndexedY || !ctx.compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)
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}) ~~> { (code, ctx) =>
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val addr = ctx.get[Constant](2)
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val last = code.last
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code.init :+ last.copy(parameter = addr, addrMode = if (last.addrMode == IndexedZ) Absolute else AbsoluteY)
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},
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(HasOpcode(LDA) & MatchImmediate(0)) ~
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(HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(4)) ~
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(HasOpcode(LDA) & MatchImmediate(1) & HasAddrModeIn(Absolute, ZeroPage)) ~
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(HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & MatchParameter(5)) ~
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Where(ctx => {
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ctx.addObject(3, ZeroPage)
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(ctx.get[Constant](4) + 1).quickSimplify == ctx.get[Constant](5)
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}) ~
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(Linear & DoesNotConcernMemoryAt(3, 4) & DoesNotConcernMemoryAt(3, 5)).* ~
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Where(ctx => {
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val lo = ctx.get[Constant](0)
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val hi = ctx.get[Constant](1)
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ctx.addObject(2, (hi.asl(8) + lo).quickSimplify)
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true
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}) ~
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(Elidable & MatchParameter(4) & HasAddrModeIn(IndexedZ, IndexedY) & MatchAddrMode(9)) ~
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Where(ctx => {
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ctx.get[AddrMode.Value](9) == IndexedY || !ctx.compilationOptions.flag(CompilationFlag.Emit65CE02Opcodes)
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}) ~~> { (code, ctx) =>
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val addr = ctx.get[Constant](2)
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val last = code.last
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code.init :+ last.copy(parameter = addr, addrMode = if (last.addrMode == IndexedZ) Absolute else AbsoluteY)
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},
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)
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val ReplacingArithmeticsWithBitOps = new RuleBasedAssemblyOptimization("Replacing arithmetics with bit ops",
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@ -237,7 +237,20 @@ object ZeropageRegisterOptimizations {
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AssemblyLine.zeropage(ctx.get[Opcode.Value](1), ctx.zreg(zregIndex)),
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AssemblyLine.implied(TSX)))
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}
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})
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}),
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MultipleAssemblyRules((0 to 1).map { zregIndex =>
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(Elidable & HasOpcode(PHA) & DoesntMatterWhatItDoesWithReg(zregIndex)) ~
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(Linear & Not(ConcernsS) & Not(RefersToOrUses("__reg", zregIndex))).*.capture(21) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersToOrUses("__reg", zregIndex)) ~
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(Elidable & HasOpcode(PLA)) ~
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(HasOpcodeIn(LDY, LDX, CLC, SEC, CLD, SED)).*.capture(22) ~
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(Elidable & HasOpcodeIn(ORA, EOR, ADC, AND) & HasAddrModeIn(Absolute, ZeroPage) & RefersToOrUses("__reg", zregIndex) & DoesntMatterWhatItDoesWithReg(zregIndex)) ~~> { (code, ctx) =>
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List(AssemblyLine.zeropage(STA, ctx.zreg(zregIndex)).pos(code.head.source)) ++
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ctx.get[List[AssemblyLine]](21) ++
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ctx.get[List[AssemblyLine]](22) ++
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List(code.last)
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}
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}),
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)
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val PointlessLoad = new RuleBasedAssemblyOptimization("Pointless load from zeropage register",
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@ -311,6 +324,53 @@ object ZeropageRegisterOptimizations {
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})
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)
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private val simplifiableIndexingFiller: AssemblyPattern =
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.N, State.Z) | Linear & Not(ConcernsY) & Not(RefersToOrUses("__reg"))).*
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private val finalIndexingOperation: AssemblyLinePattern =
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HasY(0) & HasAddrMode(IndexedY) & RefersToOrUses("__reg", 0) & DoesntMatterWhatItDoesWith(State.Y) & DoesntMatterWhatItDoesWithReg(0) & DoesntMatterWhatItDoesWithReg(1)
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val SimplifiablePointerIndexing = new RuleBasedAssemblyOptimization("Simplifiable pointer indexing",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(ADC) & HasClear(State.D) & HasClear(State.C) & HasAddrModeIn(Absolute, ZeroPage, Immediate) & Not(RefersToOrUses("__reg"))) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 0)) ~
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(Elidable & HasOpcode(BCC) & MatchParameter(1)) ~
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(Elidable & HasOpcode(INC) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 1)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(1) & IsNotALabelUsedManyTimes & DoesntMatterWhatItDoesWith(State.A, State.V, State.C, State.N, State.Z)) ~
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(simplifiableIndexingFiller ~ finalIndexingOperation).capture(2) ~~> { (code, ctx) =>
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code(1) :: code.head.copy(opcode = LDY) :: ctx.get[List[AssemblyLine]](2).filter(l => l.opcode != LDY)
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},
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(Elidable & HasOpcode(ADC) & HasClear(State.D) & HasClear(State.C) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 0)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 0)) ~
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(Elidable & HasOpcode(BCC) & MatchParameter(1)) ~
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(Elidable & HasOpcode(INC) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 1)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(1) & IsNotALabelUsedManyTimes & DoesntMatterWhatItDoesWith(State.A, State.V, State.C, State.N, State.Z)) ~
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(simplifiableIndexingFiller ~ finalIndexingOperation).capture(2) ~~> { (code, ctx) =>
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AssemblyLine.implied(TAY).pos(code.head.source) :: ctx.get[List[AssemblyLine]](2).filter(l => l.opcode != LDY)
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},
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(Elidable & HasOpcode(ADC) & HasClear(State.D) & HasClear(State.C) & HasAddrModeIn(Absolute, ZeroPage, Immediate) & Not(RefersToOrUses("__reg"))) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 0)) ~
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(Elidable & HasOpcode(TXA)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(0)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 1) & DoesntMatterWhatItDoesWith(State.A, State.V, State.C, State.N, State.Z)) ~
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(simplifiableIndexingFiller ~ finalIndexingOperation).capture(2) ~~> { (code, ctx) =>
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code(1) :: code(4).copy(opcode = STX) :: code.head.copy(opcode = LDY) :: ctx.get[List[AssemblyLine]](2).filter(l => l.opcode != LDY)
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},
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(Elidable & HasOpcode(ADC) & HasClear(State.D) & HasClear(State.C) & HasAddrModeIn(Absolute, ZeroPage, Immediate) & Not(RefersToOrUses("__reg"))) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 0)) ~
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(Absolute, ZeroPage, Immediate) & Not(RefersTo("__reg"))) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(0)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & RefersTo("__reg", 1) & DoesntMatterWhatItDoesWith(State.A, State.V, State.C, State.N, State.Z)) ~
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(simplifiableIndexingFiller ~ finalIndexingOperation).capture(2) ~~> { (code, ctx) =>
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code(1) :: code(2) :: code(4) :: code.head.copy(opcode = LDY) :: ctx.get[List[AssemblyLine]](2).filter(l => l.opcode != LDY)
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},
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)
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val SimplifiableAddingOfOneBit = new RuleBasedAssemblyOptimization("Simplifiable adding of one bit",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(AND) & HasImmediate(1)) ~
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@ -347,6 +407,7 @@ object ZeropageRegisterOptimizations {
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DeadRegStoreFromFlow,
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PointlessLoad,
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SimplifiableAddingOfOneBit,
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SimplifiablePointerIndexing,
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StashInRegInsteadOfStack,
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)
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8
src/main/scala/millfork/env/Constant.scala
vendored
8
src/main/scala/millfork/env/Constant.scala
vendored
@ -333,7 +333,13 @@ case class CompoundConstant(operator: MathOperator.Value, lhs: Constant, rhs: Co
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((l + b) - a).quickSimplify
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case (_, CompoundConstant(MathOperator.Plus, a, b)) if operator == MathOperator.Minus =>
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((l - a) - b).quickSimplify
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case (CompoundConstant(MathOperator.Shl, SubbyteConstant(c1, 1), NumericConstant(8, _)), SubbyteConstant(c2, 0)) if operator == MathOperator.Or && c1 == c2 => c1
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case (CompoundConstant(MathOperator.Shl, SubbyteConstant(c1, 1), NumericConstant(8, _)), SubbyteConstant(c2, 0))
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if operator == MathOperator.Or || operator == MathOperator.Plus && c1 == c2 && c1.requiredSize <= 2 => c1
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case (CompoundConstant(MathOperator.Times, SubbyteConstant(c1, 1), NumericConstant(256, _)), SubbyteConstant(c2, 0))
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if operator == MathOperator.Or || operator == MathOperator.Plus && c1 == c2 && c1.requiredSize <= 2 => c1
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case (CompoundConstant(MathOperator.Times, NumericConstant(256, _), SubbyteConstant(c1, 1)), SubbyteConstant(c2, 0))
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if operator == MathOperator.Or || operator == MathOperator.Plus && c1 == c2 && c1.requiredSize <= 2 => c1
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case (_, CompoundConstant(MathOperator.DecimalMinus, a, b)) if operator == MathOperator.DecimalPlus =>
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CompoundConstant(MathOperator.DecimalMinus, CompoundConstant(MathOperator.DecimalPlus, l, a), b).quickSimplify
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