14 Commits

Author	SHA1	Message	Date
Karol Stasiak	bf47473162	Allow setting the size of the zeropage register from the command line.	2018-08-06 19:15:41 +02:00
Karol Stasiak	fab1cafec3	Z80: Intel syntax support	2018-08-03 13:23:37 +02:00
Karol Stasiak	388ceb8b3a	6502: software BCD, increase default zpreg to 4	2018-08-03 13:06:23 +02:00
Karol Stasiak	e952d89849	Z80: Intel syntax for output.	2018-08-01 21:16:20 +02:00
Karol Stasiak	69f233e378	Z80: Interrupt handlers. Allow using IY as base pointer.	2018-08-01 12:50:05 +02:00
Karol Stasiak	215d8d92b4	Preprocessor. Z80 improvements. Library improvements.	2018-07-12 19:39:25 +02:00
Karol Stasiak	2c8de8b6a5	Text encoding improvements	2018-07-07 00:58:44 +02:00
Karol Stasiak	351d2ac5f9	Documentation update	2018-07-03 23:28:05 +02:00
Karol Stasiak	9512e8e7ae	Really early and very incomplete PC-88 support	2018-07-02 00:31:47 +02:00
Karol Stasiak	35caae6d8b	Unify syntax of command-line switches	2018-07-01 19:19:30 +02:00
Karol Stasiak	2500f842e9	Interprocedural optimization plus some minor fixes: ... – fixed handling LDX/LDY/LDZ when inlining variables into registers – fixed CLA/CLX/CLY instruction generation – refactored optimization definitions	2018-06-25 21:29:04 +02:00
Karol Stasiak	c71af26989	Documentation updates	2018-06-04 16:24:18 +02:00
Karol Stasiak	3296d5a201	Documentation improvements	2018-04-03 00:21:26 +02:00
Karol Stasiak	1a0737e4c9	Rename documentation files	2018-03-28 19:31:10 +02:00