// TODO: bankswitching volatile byte vera_addr_hi @ $9f20 volatile byte vera_addr_mi @ $9f21 volatile byte vera_addr_lo @ $9f22 volatile byte vera_data1 @ $9f23 volatile byte vera_data2 @ $9f24 volatile byte vera_ctrl @ $9f25 volatile byte vera_ien @ $9f26 volatile byte vera_isr @ $9f27 struct vera_layer_setup { byte ctrl0 byte ctrl1 word map_base word tile_base word hscroll word vscroll } asm void set_vera_layer_internal(pointer.vera_layer_setup ax, byte y) { sta __reg stx __reg+1 stz vera_ctrl lda $14 sta vera_addr_hi stz vera_addr_mi sty vera_addr_lo ldy #0 __set_layer_internal_loop: lda (__reg),y sta vera_data1 iny cpy #sizeof(vera_layer_setup) bne __set_layer_internal_loop ? rts } asm void set_vera_layer0(pointer.vera_layer_setup ax) { ? ldy #0 ? jmp set_vera_layer_internal } asm void set_vera_layer1(pointer.vera_layer_setup ax) { ? ldy #0 ? jmp set_vera_layer_internal } inline void vera_poke(int24 address, byte value) { vera_addr_lo = address.b0 vera_addr_mi = address.b1 vera_addr_hi = address.b2 vera_ctrl = 0 vera_data1 = value } inline void vera_fill(int24 address, byte value, word size) { word i vera_addr_lo = address.b0 vera_addr_mi = address.b1 vera_addr_hi = address.b2 | $10 vera_ctrl = 0 for i,0,paralleluntil,size { vera_data1 = value } } void vera_upload_large(int24 address, pointer source, word size) { word i vera_ctrl = 0 vera_addr_lo = address.b0 vera_addr_mi = address.b1 vera_addr_hi = address.b2 | $10 for i,0,paralleluntil,size { vera_data1 = source[i] } } inline void vera_upload(int24 address, pointer source, byte size) { byte i vera_ctrl = 0 vera_addr_lo = address.b0 vera_addr_mi = address.b1 vera_addr_hi = address.b2 | $10 asm { ? ldy #0 __vera_upload_loop: ? lda (__reg),y ? sta vera_data1 ? iny ? cpy size ? bne __vera_upload_loop } } struct vera_sprite_data { word address word x word y byte ctrl0 byte ctrl1 }