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140 lines
2.7 KiB
Plaintext
140 lines
2.7 KiB
Plaintext
#if not(INIT_RW_MEMORY)
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#error The init_rw_memory module cannot be used by the current target
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#endif
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#if ARCH_6502
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#if TINY_RW_MEMORY
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asm void init_rw_memory() {
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? ldx #__rwdata_size.lo // can't be more than $00FC
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? beq __init_rw_memory__skip3
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+ memory_barrier()
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__init_rw_memory__loop3:
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? lda lo(__rwdata_init_start - 1),x
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? sta lo(__rwdata_start - 1),x
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? dex
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? bne __init_rw_memory__loop3
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+ memory_barrier()
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__init_rw_memory__skip3:
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? rts
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}
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#else
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#if ZPREG_SIZE < 4
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#error The init_rw_module requires at least 4 bytes of zeropage pseudoregister
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#endif
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noinline asm void init_rw_memory() {
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? lda #__rwdata_size.hi
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? ora #__rwdata_size.lo
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? beq __init_rw_memory__skip3
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+ memory_barrier()
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? ldx #__rwdata_size.hi
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? beq __init_rw_memory__skip1
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? lda #__rwdata_init_start.lo
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? sta __reg
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? lda #__rwdata_init_start.hi
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? sta __reg+1
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? lda #__rwdata_start.lo
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? sta __reg+2
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? lda #__rwdata_start.hi
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? sta __reg+3
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__init_rw_memory__loop1:
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? ldy #0
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__init_rw_memory__loop2:
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? lda (__reg),y
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? sta (__reg+2),y
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? dey
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? bne __init_rw_memory__loop2
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? inc __reg+1
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? inc __reg+3
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? dex
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? bne __init_rw_memory__loop1
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__init_rw_memory__skip1:
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? ldx #__rwdata_size.lo
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? beq __init_rw_memory__skip3
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__init_rw_memory__loop3:
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? lda __rwdata_init_start + (__rwdata_size & $ff00) - 1,x
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? sta __rwdata_start + (__rwdata_size & $ff00) - 1,x
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? dex
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? bne __init_rw_memory__loop3
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__init_rw_memory__skip3:
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+ memory_barrier()
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rts
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}
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#endif
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#elseif CPUFEATURE_Z80
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#pragma zilog_syntax
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noinline asm void init_rw_memory() {
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ld bc,__rwdata_size
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ld a,b
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or c
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ret z
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+ memory_barrier()
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ld hl,__rwdata_init_start
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ld de,__rwdata_start
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ldir
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+ memory_barrier()
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ret
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}
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#elseif ARCH_I80
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#pragma zilog_syntax
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noinline asm void init_rw_memory() {
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ld bc,__rwdata_size
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ld a,b
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or c
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ret z
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+ memory_barrier()
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ld hl,__rwdata_init_start
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ld de,__rwdata_start
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__init_rw_memory__loop1:
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? ld a,(hl)
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? inc hl
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ld (de),a
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inc de
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dec bc
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? jp nz,__init_rw_memory__loop1
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+ memory_barrier()
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ret
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}
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#elseif ARCH_6809
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noinline asm void init_rw_memory() {
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// TODO: optimal register allocation
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ldd __rwdata_size
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beq __init_rw_memory_end
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+ memory_barrier()
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pshs u
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ldx __rwdata_init_start
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ldu __rwdata_start
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__init_rw_memory__loop1:
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ldb ,x
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stb ,u
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leax 1,x
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cmpx #__rwdata_init_start+__rwdata_size
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? bne __init_rw_memory__loop1
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+ memory_barrier()
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puls u
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__init_rw_memory_end:
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rts
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}
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#else
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#error Unsupported architecture for init_rw_memory
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#endif |