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https://github.com/KarolS/millfork.git
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63ff28e94e
* non-asm macros can now take `const` and `call` parameters * register parameters to asm functions and macros can be given names if annotated explicitly
169 lines
3.5 KiB
Plaintext
169 lines
3.5 KiB
Plaintext
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#if VERA_VERSION == 7
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const int24 VERA_COMPOSER_CTRL = $40040
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const int24 VERA_PALETTE = $40200
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const int24 VERA_LAYER_1 = $40000
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const int24 VERA_LAYER_2 = $40010
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const int24 VERA_SPRITE_CTRL = $40020
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const int24 VERA_SPRITES = $40800
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volatile byte vera_addr_hi @ $9f20
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volatile byte vera_addr_mi @ $9f21
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volatile byte vera_addr_lo @ $9f22
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#elseif VERA_VERSION == 8
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const int24 VERA_COMPOSER_CTRL = $F0000
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const int24 VERA_PALETTE = $F1000
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const int24 VERA_LAYER_1 = $F2000
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const int24 VERA_LAYER_2 = $F3000
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const int24 VERA_SPRITE_CTRL = $F4000
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const int24 VERA_SPRITES = $F5000
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volatile byte vera_addr_hi @ $9f22
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volatile byte vera_addr_mi @ $9f21
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volatile byte vera_addr_lo @ $9f20
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volatile int24 vera_addr @ $9f20
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#else
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#error Unsupported VERA_VERSION
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#endif
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volatile byte vera_data1 @ $9f23
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volatile byte vera_data2 @ $9f24
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volatile byte vera_ctrl @ $9f25
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volatile byte vera_ien @ $9f26
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volatile byte vera_isr @ $9f27
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struct vera_layer_setup {
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byte ctrl0
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byte ctrl1
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word map_base
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word tile_base
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word hscroll
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word vscroll
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}
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asm void set_vera_layer_internal(pointer.vera_layer_setup ax, byte y) {
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sta __reg
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stx __reg+1
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stz vera_ctrl
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#if VERA_VERSION == 7
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lda $14
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sta vera_addr_hi
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stz vera_addr_mi
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sty vera_addr_lo
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#elseif VERA_VERSION == 8
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lda $1F
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sta vera_addr_hi
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sty vera_addr_mi
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stz vera_addr_lo
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#else
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#error Unsupported VERA_VERSION
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#endif
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ldy #0
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__set_layer_internal_loop:
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lda (__reg),y
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sta vera_data1
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iny
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cpy #sizeof(vera_layer_setup)
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bne __set_layer_internal_loop
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? rts
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}
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asm void set_vera_layer1(pointer.vera_layer_setup ax) {
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#if VERA_VERSION == 7
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? ldy #0
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#elseif VERA_VERSION == 8
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? ldy #$20
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#else
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#error Unsupported VERA_VERSION
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#endif
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? jmp set_vera_layer_internal
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}
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asm void set_vera_layer2(pointer.vera_layer_setup ax) {
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#if VERA_VERSION == 7
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? ldy #$10
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#elseif VERA_VERSION == 8
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? ldy #$30
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#else
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#error Unsupported VERA_VERSION
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#endif
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? jmp set_vera_layer_internal
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}
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inline void vera_poke(int24 address, byte value) {
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vera_addr_lo = address.b0
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vera_addr_mi = address.b1
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vera_addr_hi = address.b2
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vera_ctrl = 0
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vera_data1 = value
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}
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inline byte vera_peek(int24 address) {
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vera_addr_lo = address.b0
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vera_addr_mi = address.b1
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vera_addr_hi = address.b2
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vera_ctrl = 0
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return vera_data1
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}
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inline void vera_fill(int24 address, byte value, word size) {
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word i
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vera_addr_lo = address.b0
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vera_addr_mi = address.b1
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vera_addr_hi = address.b2 | $10
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vera_ctrl = 0
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for i,0,paralleluntil,size {
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vera_data1 = value
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}
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}
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void vera_upload_large(int24 address, pointer source, word size) {
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word i
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vera_ctrl = 0
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vera_addr_lo = address.b0
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vera_addr_mi = address.b1
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vera_addr_hi = address.b2 | $10
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for i,0,paralleluntil,size {
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vera_data1 = source[i]
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}
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}
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inline void vera_upload(int24 address, pointer source, byte size) {
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byte i
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vera_ctrl = 0
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vera_addr_lo = address.b0
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vera_addr_mi = address.b1
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vera_addr_hi = address.b2 | $10
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asm {
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? ldy #0
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__vera_upload_loop:
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? lda (source),y
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! sta vera_data1
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? iny
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? cpy size
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? bne __vera_upload_loop
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}
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}
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struct vera_sprite_data {
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word address
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word x
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word y
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byte ctrl0
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byte ctrl1
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}
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inline asm void set_ram_bank(byte register(a) bank) {
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! STA $9F61
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? RTS
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}
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inline asm void set_rom_bank(byte register(a) bank) {
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! STA $9F60
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? RTS
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}
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