2018-10-25 15:02:27 +02:00
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# mos6502
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2019-10-22 09:17:15 +09:00
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[](https://travis-ci.org/mre/mos6502)
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
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2017-10-08 17:31:20 +02:00
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2018-11-04 21:39:15 +01:00
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An emulator for the [MOS 6502 CPU](https://en.wikipedia.org/wiki/MOS_Technology_6502) written in Rust.
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2018-11-04 21:54:09 +01:00
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This started off as a fork of [amw-zero/6502-rs](https://github.com/amw-zero/6502-rs),
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2017-10-08 17:31:20 +02:00
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which seems to be unmaintained at this point.
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2018-11-04 20:40:00 +01:00
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It builds with the latest stable Rust and supports `#[no_std]` targets.
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2018-11-04 20:26:51 +01:00
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## Usage example
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```rust
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extern crate mos6502;
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use mos6502::address::Address;
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2019-10-22 15:15:26 +03:00
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use mos6502::cpu;
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2018-11-04 20:26:51 +01:00
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fn main() {
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2019-10-22 18:53:13 +03:00
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let zero_page_data = [56, 49];
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2018-11-04 20:26:51 +01:00
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let program = [
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2019-10-22 15:15:26 +03:00
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// (F)irst | (S)econd
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// .algo
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0xa5, 0x00, // Load from F to A
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// .algo_
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0x38, // Set carry flag
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0xe5, 0x01, // Substract S from number in A (from F)
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0xf0, 0x07, // Jump to .end if diff is zero
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0x30, 0x08, // Jump to .swap if diff is negative
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0x85, 0x00, // Load A to F
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0x4c, 0x12, 0x00, // Jump to .algo_
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// .end
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0xa5, 0x00, // Load from S to A
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0xff,
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// .swap
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0xa6, 0x00, // load F to X
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0xa4, 0x01, // load S to Y
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0x86, 0x01, // Store X to F
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0x84, 0x00, // Store Y to S
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0x4c, 0x10, 0x00, // Jump to .algo
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2018-11-04 20:26:51 +01:00
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];
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2019-10-22 15:15:26 +03:00
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let mut cpu = cpu::CPU::new();
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2018-11-04 20:26:51 +01:00
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2019-10-22 15:15:26 +03:00
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cpu.memory.set_bytes(Address(0x00), &zero_page_data);
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cpu.memory.set_bytes(Address(0x10), &program);
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cpu.registers.program_counter = Address(0x10);
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2018-11-04 20:26:51 +01:00
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cpu.run();
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2019-10-22 15:15:26 +03:00
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2019-10-22 18:53:13 +03:00
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assert_eq!(7, cpu.registers.accumulator);
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2018-11-04 20:26:51 +01:00
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}
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```
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