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https://github.com/mre/mos6502.git
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Variant with no decimal mode
This commit is contained in:
Sam M W
parent
877f83a6d1
commit
030e6c1d0a
104
src/cpu.rs
104
src/cpu.rs
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@ -196,6 +196,15 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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debug!("add with carry. address: {:?}. value: {}", addr, val);
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self.add_with_carry(val);
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}
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(Instruction::ADCnd, OpInput::UseImmediate(val)) => {
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debug!("add with carry immediate: {}", val);
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self.add_with_no_decimal(val);
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}
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(Instruction::ADCnd, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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debug!("add with carry. address: {:?}. value: {}", addr, val);
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self.add_with_no_decimal(val);
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}
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(Instruction::AND, OpInput::UseImmediate(val)) => {
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self.and(val);
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@ -509,6 +518,16 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.subtract_with_carry(val);
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}
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(Instruction::SBCnd, OpInput::UseImmediate(val)) => {
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debug!("subtract with carry immediate: {}", val);
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self.subtract_with_no_decimal(val);
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}
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(Instruction::SBCnd, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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debug!("subtract with carry. address: {:?}. value: {}", addr, val);
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self.subtract_with_no_decimal(val);
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}
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(Instruction::SEC, OpInput::UseImplied) => {
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self.registers.status.or(Status::PS_CARRY);
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}
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@ -700,7 +719,6 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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}
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fn add_with_carry(&mut self, value: u8) {
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#[cfg(feature = "decimal_mode")]
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fn decimal_adjust(result: u8) -> u8 {
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let bcd1: u8 = if (result & 0x0f) > 0x09 { 0x06 } else { 0x00 };
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@ -719,15 +737,43 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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debug_assert_eq!(a_after, a_before.wrapping_add(c_before).wrapping_add(value));
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#[cfg(feature = "decimal_mode")]
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let result: u8 = if self.registers.status.contains(Status::PS_DECIMAL_MODE) {
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decimal_adjust(a_after)
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} else {
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a_after
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};
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#[cfg(not(feature = "decimal_mode"))]
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let result: u8 = a_after;
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let did_carry = (result) < (a_before)
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|| (a_after == 0 && c_before == 0x01)
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|| (value == 0xff && c_before == 0x01);
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let did_overflow = (a_before > 127 && value > 127 && a_after < 128)
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|| (a_before < 128 && value < 128 && a_after > 127);
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let mask = Status::PS_CARRY | Status::PS_OVERFLOW;
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self.registers.status.set_with_mask(
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mask,
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Status::new(StatusArgs {
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carry: did_carry,
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overflow: did_overflow,
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..StatusArgs::none()
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}),
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);
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self.load_accumulator(result);
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debug!("accumulator: {}", self.registers.accumulator);
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}
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fn add_with_no_decimal(&mut self, value: u8) {
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let a_before: u8 = self.registers.accumulator;
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let c_before: u8 = u8::from(self.registers.status.contains(Status::PS_CARRY));
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let a_after: u8 = a_before.wrapping_add(c_before).wrapping_add(value);
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debug_assert_eq!(a_after, a_before.wrapping_add(c_before).wrapping_add(value));
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let result = a_after;
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let did_carry = (result) < (a_before)
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|| (a_after == 0 && c_before == 0x01)
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@ -757,6 +803,52 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.load_accumulator(a_after);
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}
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fn subtract_with_no_decimal(&mut self, value: u8) {
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// A - M - (1 - C)
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// nc -- 'not carry'
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let nc: u8 = if self.registers.status.contains(Status::PS_CARRY) {
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0
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} else {
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1
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};
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let a_before = self.registers.accumulator;
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let a_after = a_before.wrapping_sub(value).wrapping_sub(nc);
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// The overflow flag is set on two's-complement overflow.
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//
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// range of A is -128 to 127
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// range of - M - (1 - C) is -128 to 128
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// -(127 + 1) to -(-128 + 0)
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//
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let over = (nc == 0 && value > 127) && a_before < 128 && a_after > 127;
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let under =
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(a_before > 127) && (0u8.wrapping_sub(value).wrapping_sub(nc) > 127) && a_after < 128;
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let did_overflow = over || under;
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let mask = Status::PS_CARRY | Status::PS_OVERFLOW;
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let result = a_after;
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// The carry flag is set on unsigned overflow.
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let did_carry = (result) > (a_before);
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self.registers.status.set_with_mask(
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mask,
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Status::new(StatusArgs {
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carry: did_carry,
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overflow: did_overflow,
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..StatusArgs::none()
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}),
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);
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self.load_accumulator(result);
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}
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fn subtract_with_carry(&mut self, value: u8) {
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// A - M - (1 - C)
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@ -798,16 +890,12 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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0x00
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};
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#[cfg(feature = "decimal_mode")]
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let result: u8 = if self.registers.status.contains(Status::PS_DECIMAL_MODE) {
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a_after.wrapping_sub(bcd1).wrapping_sub(bcd2)
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} else {
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a_after
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};
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#[cfg(not(feature = "decimal_mode"))]
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let result = a_after;
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// The carry flag is set on unsigned overflow.
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let did_carry = (result) > (a_before);
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@ -44,39 +44,40 @@
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Instruction {
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ADC, // ADd with Carry................ | NV ...ZC A = A + M + C
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AND, // logical AND (bitwise)......... | N. ...Z. A = A && M
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ASL, // Arithmetic Shift Left......... | N. ...ZC A = M << 1
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BCC, // Branch if Carry Clear......... | .. ..... PC = !C
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BCS, // Branch if Carry Set........... | .. ..... PC = C
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BEQ, // Branch if Equal (to zero?).... | .. ..... PC = Z
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BIT, // BIT test...................... | NV ...Z. = A & M
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BMI, // Branch if Minus............... | .. ..... PC = N
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BNE, // Branch if Not Equal........... | .. ..... PC = !Z
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BPL, // Branch if Positive............ | .. ..... PC = Z
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BRK, // BReaK......................... | .. B.... S PC =
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BVC, // Branch if oVerflow Clear...... | .. ..... PC = !V
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BVS, // Branch if oVerflow Set........ | .. ..... PC = V
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CLC, // CLear Carry flag.............. | .. ....C = 0
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CLD, // Clear Decimal Mode............ | .. .D... = 0
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CLI, // Clear Interrupt Disable....... | .. ..I.. = 0
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CLV, // Clear oVerflow flag........... | .V ..... = 0
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CMP, // Compare....................... | N. ...ZC = A - M
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CPX, // Compare X register............ | N. ...ZC = X - M
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CPY, // Compare Y register............ | N. ...ZC = Y - M
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DEC, // DECrement memory.............. | N. ...Z. M = M - 1
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DEX, // DEcrement X register.......... | N. ...Z. X = X - 1
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DEY, // DEcrement Y register.......... | N. ...Z. Y = Y - 1
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EOR, // Exclusive OR (bitwise)........ | N. ...Z. A = A ^ M
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INC, // INCrement memory.............. | N. ...Z. M = M + 1
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INX, // INcrement X register.......... | N. ...Z. X = X + 1
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INY, // INcrement Y register.......... | N. ...Z. Y = Y + 1
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JMP, // JuMP.......................... | .. ..... S PC =
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JSR, // Jump to SubRoutine............ | .. ..... S PC =
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LDA, // LoaD Accumulator.............. | N. ...Z. A = M
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LDX, // LoaD X register............... | N. ...Z. X = M
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LDY, // LoaD Y register............... | N. ...Z. Y = M
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LSR, // Logical Shift Right........... | N. ...ZC A = A/2
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ADC, // ADd with Carry................ | NV ...ZC A = A + M + C
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ADCnd, // ADd with Carry................ | NV ...ZC A = A + M + C
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AND, // logical AND (bitwise)......... | N. ...Z. A = A && M
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ASL, // Arithmetic Shift Left......... | N. ...ZC A = M << 1
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BCC, // Branch if Carry Clear......... | .. ..... PC = !C
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BCS, // Branch if Carry Set........... | .. ..... PC = C
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BEQ, // Branch if Equal (to zero?).... | .. ..... PC = Z
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BIT, // BIT test...................... | NV ...Z. = A & M
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BMI, // Branch if Minus............... | .. ..... PC = N
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BNE, // Branch if Not Equal........... | .. ..... PC = !Z
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BPL, // Branch if Positive............ | .. ..... PC = Z
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BRK, // BReaK......................... | .. B.... S PC =
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BVC, // Branch if oVerflow Clear...... | .. ..... PC = !V
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BVS, // Branch if oVerflow Set........ | .. ..... PC = V
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CLC, // CLear Carry flag.............. | .. ....C = 0
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CLD, // Clear Decimal Mode............ | .. .D... = 0
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CLI, // Clear Interrupt Disable....... | .. ..I.. = 0
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CLV, // Clear oVerflow flag........... | .V ..... = 0
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CMP, // Compare....................... | N. ...ZC = A - M
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CPX, // Compare X register............ | N. ...ZC = X - M
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CPY, // Compare Y register............ | N. ...ZC = Y - M
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DEC, // DECrement memory.............. | N. ...Z. M = M - 1
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DEX, // DEcrement X register.......... | N. ...Z. X = X - 1
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DEY, // DEcrement Y register.......... | N. ...Z. Y = Y - 1
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EOR, // Exclusive OR (bitwise)........ | N. ...Z. A = A ^ M
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INC, // INCrement memory.............. | N. ...Z. M = M + 1
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INX, // INcrement X register.......... | N. ...Z. X = X + 1
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INY, // INcrement Y register.......... | N. ...Z. Y = Y + 1
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JMP, // JuMP.......................... | .. ..... S PC =
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JSR, // Jump to SubRoutine............ | .. ..... S PC =
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LDA, // LoaD Accumulator.............. | N. ...Z. A = M
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LDX, // LoaD X register............... | N. ...Z. X = M
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LDY, // LoaD Y register............... | N. ...Z. Y = M
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LSR, // Logical Shift Right........... | N. ...ZC A = A/2
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// or N. ...ZC M = M/2
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NOP, // No OPeration.................. | .. ..... =
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ORA, // inclusive OR (bitwise)........ | N. ...Z. A = A | M
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@ -88,21 +89,22 @@ pub enum Instruction {
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// or N. ...ZC M = C M rotated
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ROR, // ROtate Right.................. | N. ...ZC A = C A rotated
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// or N. ...ZC M = C M rotated
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RTI, // ReTurn from Interrupt......... | NV BDIZC PC = M (stack)
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RTS, // ReTurn from Subroutine........ | .. ..... PC = M (stack)
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SBC, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
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SEC, // SEt Carry flag................ | .. ....C = 1
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SED, // SEt Decimal flag.............. | .. .D... = 1
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SEI, // SEt Interrupt disable......... | .. ..I.. = 1
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STA, // STore Accumulator............. | .. ..... M = A
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STX, // STore X register.............. | .. ..... M = X
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STY, // STore Y register.............. | .. ..... M = Y
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TAX, // Transfer Accumulator to X..... | N. ...Z. X = A
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TAY, // Transfer Accumulator to Y..... | N. ...Z. Y = A
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TSX, // Transfer Stack pointer to X... | N. ...Z. X = S
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TXA, // Transfer X to Accumulator..... | N. ...Z. A = X
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TXS, // Transfer X to Stack pointer... | .. ..... S = X
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TYA, // Transfer Y to Accumulator..... | N. ...Z. A = Y
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RTI, // ReTurn from Interrupt......... | NV BDIZC PC = M (stack)
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RTS, // ReTurn from Subroutine........ | .. ..... PC = M (stack)
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SBC, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
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SBCnd, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
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SEC, // SEt Carry flag................ | .. ....C = 1
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SED, // SEt Decimal flag.............. | .. .D... = 1
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SEI, // SEt Interrupt disable......... | .. ..I.. = 1
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STA, // STore Accumulator............. | .. ..... M = A
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STX, // STore X register.............. | .. ..... M = X
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STY, // STore Y register.............. | .. ..... M = Y
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TAX, // Transfer Accumulator to X..... | N. ...Z. X = A
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TAY, // Transfer Accumulator to Y..... | N. ...Z. Y = A
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TSX, // Transfer Stack pointer to X... | N. ...Z. X = S
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TXA, // Transfer X to Accumulator..... | N. ...Z. A = X
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TXS, // Transfer X to Stack pointer... | .. ..... S = X
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TYA, // Transfer Y to Accumulator..... | N. ...Z. A = Y
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}
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#[derive(Copy, Clone)]
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@ -418,6 +420,32 @@ impl crate::Variant for Nmos6502 {
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}
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}
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}
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pub struct Ricoh2a03;
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impl crate::Variant for Ricoh2a03 {
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fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
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match opcode {
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0x61 => Some((Instruction::ADCnd, AddressingMode::IndexedIndirectX)),
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0x65 => Some((Instruction::ADCnd, AddressingMode::ZeroPage)),
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0x69 => Some((Instruction::ADCnd, AddressingMode::Immediate)),
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0x6d => Some((Instruction::ADCnd, AddressingMode::Absolute)),
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0x71 => Some((Instruction::ADCnd, AddressingMode::IndirectIndexedY)),
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0x75 => Some((Instruction::ADCnd, AddressingMode::ZeroPageX)),
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0x79 => Some((Instruction::ADCnd, AddressingMode::AbsoluteY)),
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0x7d => Some((Instruction::ADCnd, AddressingMode::AbsoluteX)),
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0xe1 => Some((Instruction::SBCnd, AddressingMode::IndexedIndirectX)),
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0xe5 => Some((Instruction::SBCnd, AddressingMode::ZeroPage)),
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0xe9 => Some((Instruction::SBCnd, AddressingMode::Immediate)),
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0xed => Some((Instruction::SBCnd, AddressingMode::Absolute)),
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0xf1 => Some((Instruction::SBCnd, AddressingMode::IndirectIndexedY)),
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0xf5 => Some((Instruction::SBCnd, AddressingMode::ZeroPageX)),
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0xf9 => Some((Instruction::SBCnd, AddressingMode::AbsoluteY)),
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0xfd => Some((Instruction::SBCnd, AddressingMode::AbsoluteX)),
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_ => Nmos6502::decode(opcode),
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}
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}
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}
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pub struct RevisionA;
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impl crate::Variant for RevisionA {
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