mirror of https://github.com/mre/mos6502.git
generic argument for CPU represents memory
This commit is contained in:
Sam M W
parent
a8dac6e805
commit
12c901e8aa
178
src/cpu.rs
178
src/cpu.rs
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@ -25,33 +25,40 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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use crate::instruction::{self, DecodedInstr, Instruction, OpInput};
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use crate::instruction::{self, AddressingMode, DecodedInstr, Instruction, OpInput};
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use crate::memory::Bus;
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use crate::memory::Memory;
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use crate::registers::{Registers, StackPointer, Status, StatusArgs};
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fn xextend(x: u8) -> u16 {
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u16::from(x)
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}
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fn arr_to_addr(arr: &[u8]) -> u16 {
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debug_assert!(arr.len() == 2);
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u16::from(arr[0]) + (u16::from(arr[1]) << 8usize)
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}
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#[derive(Clone)]
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pub struct CPU {
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pub struct CPU<M>
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where
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M: Bus,
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{
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pub registers: Registers,
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pub memory: Memory,
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pub memory: M,
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}
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impl Default for CPU {
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fn default() -> Self {
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Self::new()
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}
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}
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impl CPU {
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pub fn new() -> CPU {
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impl<M: Bus> CPU<M> {
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pub fn new(memory: M) -> CPU<M> {
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CPU {
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registers: Registers::new(),
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memory: Memory::new(),
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memory,
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}
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}
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pub fn reset(&mut self) {
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*self = CPU::new();
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//TODO: // should read some bytes from the stack and also get the PC from the reset vector
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}
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pub fn fetch_next_and_decode(&mut self) -> Option<DecodedInstr> {
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@ -77,7 +84,96 @@ impl CPU {
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panic!()
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};
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let am_out = am.process(self, &slice[..extra_bytes as usize]);
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let x = self.registers.index_x;
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let y = self.registers.index_y;
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let memory = &self.memory;
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fn read_address<M: Bus>(mem: &M, addr: u16) -> [u8; 2] {
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let lo = mem.get_byte(addr);
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let hi = mem.get_byte(addr.wrapping_add(1));
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[lo, hi]
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}
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let am_out = match am {
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AddressingMode::Accumulator | AddressingMode::Implied => {
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// Always the same -- no input
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OpInput::UseImplied
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}
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AddressingMode::Immediate => {
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// Use [u8, ..1] specified in instruction as input
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OpInput::UseImmediate(slice[0])
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}
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AddressingMode::ZeroPage => {
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// Use [u8, ..1] from instruction
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// Interpret as zero page address
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// (Output: an 8-bit zero-page address)
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OpInput::UseAddress(u16::from(slice[0]))
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}
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AddressingMode::ZeroPageX => {
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// Use [u8, ..1] from instruction
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// Add to X register (as u8 -- the final address is in 0-page)
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// (Output: an 8-bit zero-page address)
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OpInput::UseAddress(u16::from(slice[0].wrapping_add(x)))
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}
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AddressingMode::ZeroPageY => {
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// Use [u8, ..1] from instruction
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// Add to Y register (as u8 -- the final address is in 0-page)
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// (Output: an 8-bit zero-page address)
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OpInput::UseAddress(u16::from(slice[0].wrapping_add(y)))
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}
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AddressingMode::Relative => {
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// Use [u8, ..1] from instruction
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// (interpret as relative...)
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// (This is sign extended to a 16-but data type, but an unsigned one: u16. It's a
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// little weird, but it's so we can add the PC and the offset easily)
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let offset = slice[0];
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let sign_extend = if offset & 0x80 == 0x80 { 0xffu8 } else { 0x0 };
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let rel = u16::from_le_bytes([offset, sign_extend]);
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OpInput::UseRelative(rel)
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}
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AddressingMode::Absolute => {
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// Use [u8, ..2] from instruction as address
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice))
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}
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AddressingMode::AbsoluteX => {
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// Use [u8, ..2] from instruction as address, add X
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(x)))
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}
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AddressingMode::AbsoluteY => {
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// Use [u8, ..2] from instruction as address, add Y
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(y)))
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}
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AddressingMode::Indirect => {
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// Use [u8, ..2] from instruction as an address. Interpret the
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// two bytes starting at that address as an address.
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// (Output: a 16-bit address)
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let slice = read_address(memory, arr_to_addr(&slice));
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OpInput::UseAddress(arr_to_addr(&slice))
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}
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AddressingMode::IndexedIndirectX => {
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// Use [u8, ..1] from instruction
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// Add to X register with 0-page wraparound, like ZeroPageX.
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// This is where the absolute (16-bit) target address is stored.
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// (Output: a 16-bit address)
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let start = slice[0].wrapping_add(x);
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice))
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}
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AddressingMode::IndirectIndexedY => {
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// Use [u8, ..1] from instruction
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// This is where the absolute (16-bit) target address is stored.
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// Add Y register to this address to get the final address
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// (Output: a 16-bit address)
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(y)))
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}
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};
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// Increment program counter
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self.registers.program_counter =
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@ -112,12 +208,12 @@ impl CPU {
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(Instruction::ASL, OpInput::UseImplied) => {
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// Accumulator mode
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let mut val = self.registers.accumulator as u8;
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CPU::shift_left_with_flags(&mut val, &mut self.registers.status);
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CPU::<M>::shift_left_with_flags(&mut val, &mut self.registers.status);
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self.registers.accumulator = val as i8;
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}
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(Instruction::ASL, OpInput::UseAddress(addr)) => {
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let mut operand: u8 = self.memory.get_byte(addr);
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CPU::shift_left_with_flags(&mut operand, &mut self.registers.status);
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CPU::<M>::shift_left_with_flags(&mut operand, &mut self.registers.status);
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self.memory.set_byte(addr, operand);
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}
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@ -221,16 +317,16 @@ impl CPU {
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(Instruction::DEC, OpInput::UseAddress(addr)) => {
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let mut operand: u8 = self.memory.get_byte(addr);
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CPU::decrement(&mut operand, &mut self.registers.status);
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CPU::<M>::decrement(&mut operand, &mut self.registers.status);
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self.memory.set_byte(addr, operand);
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}
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(Instruction::DEY, OpInput::UseImplied) => {
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CPU::decrement(&mut self.registers.index_y, &mut self.registers.status);
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CPU::<M>::decrement(&mut self.registers.index_y, &mut self.registers.status);
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}
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(Instruction::DEX, OpInput::UseImplied) => {
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CPU::decrement(&mut self.registers.index_x, &mut self.registers.status);
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CPU::<M>::decrement(&mut self.registers.index_x, &mut self.registers.status);
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}
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(Instruction::EOR, OpInput::UseImmediate(val)) => {
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@ -243,14 +339,14 @@ impl CPU {
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(Instruction::INC, OpInput::UseAddress(addr)) => {
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let mut operand: u8 = self.memory.get_byte(addr);
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CPU::increment(&mut operand, &mut self.registers.status);
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CPU::<M>::increment(&mut operand, &mut self.registers.status);
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self.memory.set_byte(addr, operand);
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}
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(Instruction::INX, OpInput::UseImplied) => {
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CPU::increment(&mut self.registers.index_x, &mut self.registers.status);
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CPU::<M>::increment(&mut self.registers.index_x, &mut self.registers.status);
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}
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(Instruction::INY, OpInput::UseImplied) => {
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CPU::increment(&mut self.registers.index_x, &mut self.registers.status);
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CPU::<M>::increment(&mut self.registers.index_x, &mut self.registers.status);
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}
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(Instruction::JMP, OpInput::UseAddress(addr)) => self.jump(addr),
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@ -288,12 +384,12 @@ impl CPU {
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(Instruction::LSR, OpInput::UseImplied) => {
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// Accumulator mode
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let mut val = self.registers.accumulator as u8;
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CPU::shift_right_with_flags(&mut val, &mut self.registers.status);
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CPU::<M>::shift_right_with_flags(&mut val, &mut self.registers.status);
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self.registers.accumulator = val as i8;
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}
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(Instruction::LSR, OpInput::UseAddress(addr)) => {
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let mut operand: u8 = self.memory.get_byte(addr);
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CPU::shift_right_with_flags(&mut operand, &mut self.registers.status);
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CPU::<M>::shift_right_with_flags(&mut operand, &mut self.registers.status);
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self.memory.set_byte(addr, operand);
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}
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@ -332,23 +428,23 @@ impl CPU {
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(Instruction::ROL, OpInput::UseImplied) => {
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// Accumulator mode
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let mut val = self.registers.accumulator as u8;
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CPU::rotate_left_with_flags(&mut val, &mut self.registers.status);
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CPU::<M>::rotate_left_with_flags(&mut val, &mut self.registers.status);
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self.registers.accumulator = val as i8;
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}
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(Instruction::ROL, OpInput::UseAddress(addr)) => {
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let mut operand: u8 = self.memory.get_byte(addr);
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CPU::rotate_left_with_flags(&mut operand, &mut self.registers.status);
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CPU::<M>::rotate_left_with_flags(&mut operand, &mut self.registers.status);
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self.memory.set_byte(addr, operand);
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}
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(Instruction::ROR, OpInput::UseImplied) => {
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// Accumulator mode
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let mut val = self.registers.accumulator as u8;
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CPU::rotate_right_with_flags(&mut val, &mut self.registers.status);
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CPU::<M>::rotate_right_with_flags(&mut val, &mut self.registers.status);
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self.registers.accumulator = val as i8;
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}
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(Instruction::ROR, OpInput::UseAddress(addr)) => {
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let mut operand: u8 = self.memory.get_byte(addr);
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CPU::rotate_right_with_flags(&mut operand, &mut self.registers.status);
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CPU::<M>::rotate_right_with_flags(&mut operand, &mut self.registers.status);
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self.memory.set_byte(addr, operand);
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}
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@ -474,7 +570,7 @@ impl CPU {
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..StatusArgs::none()
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}),
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);
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CPU::set_flags_from_i8(status, *p_val as i8);
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CPU::<M>::set_flags_from_i8(status, *p_val as i8);
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}
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fn shift_right_with_flags(p_val: &mut u8, status: &mut Status) {
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@ -488,7 +584,7 @@ impl CPU {
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..StatusArgs::none()
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}),
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);
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CPU::set_flags_from_i8(status, *p_val as i8);
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CPU::<M>::set_flags_from_i8(status, *p_val as i8);
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}
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fn rotate_left_with_flags(p_val: &mut u8, status: &mut Status) {
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@ -504,7 +600,7 @@ impl CPU {
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..StatusArgs::none()
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}),
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);
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CPU::set_flags_from_i8(status, *p_val as i8);
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CPU::<M>::set_flags_from_i8(status, *p_val as i8);
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}
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fn rotate_right_with_flags(p_val: &mut u8, status: &mut Status) {
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@ -520,21 +616,21 @@ impl CPU {
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..StatusArgs::none()
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}),
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);
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CPU::set_flags_from_i8(status, *p_val as i8);
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CPU::<M>::set_flags_from_i8(status, *p_val as i8);
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}
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fn set_u8_with_flags(mem: &mut u8, status: &mut Status, value: u8) {
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*mem = value;
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CPU::set_flags_from_u8(status, value);
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CPU::<M>::set_flags_from_u8(status, value);
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}
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fn set_i8_with_flags(mem: &mut i8, status: &mut Status, value: i8) {
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*mem = value;
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CPU::set_flags_from_i8(status, value);
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CPU::<M>::set_flags_from_i8(status, value);
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}
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fn load_x_register(&mut self, value: u8) {
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CPU::set_u8_with_flags(
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CPU::<M>::set_u8_with_flags(
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&mut self.registers.index_x,
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&mut self.registers.status,
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value,
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@ -542,7 +638,7 @@ impl CPU {
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}
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fn load_y_register(&mut self, value: u8) {
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CPU::set_u8_with_flags(
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CPU::<M>::set_u8_with_flags(
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&mut self.registers.index_y,
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&mut self.registers.status,
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value,
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@ -550,7 +646,7 @@ impl CPU {
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}
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fn load_accumulator(&mut self, value: i8) {
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CPU::set_i8_with_flags(
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CPU::<M>::set_i8_with_flags(
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&mut self.registers.accumulator,
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&mut self.registers.status,
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value,
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@ -835,7 +931,7 @@ impl CPU {
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}
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}
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impl core::fmt::Debug for CPU {
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impl<M: Bus> core::fmt::Debug for CPU<M> {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(
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f,
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@ -1341,9 +1437,9 @@ mod tests {
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}
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#[cfg(test)]
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fn compare_test_helper<F>(compare: &mut F, load_instruction: Instruction)
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fn compare_test_helper<F, M>(compare: &mut F, load_instruction: Instruction)
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where
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F: FnMut(&mut CPU, u8),
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F: FnMut(&mut CPU<M>, u8),
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{
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let mut cpu = CPU::new();
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@ -25,10 +25,6 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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use crate::cpu::CPU;
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use crate::memory::Bus;
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use crate::memory::Memory;
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// Abbreviations
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//
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// General
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@ -164,100 +160,6 @@ impl AddressingMode {
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AddressingMode::IndirectIndexedY => 1,
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}
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}
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pub fn process(self, cpu: &CPU, arr: &[u8]) -> OpInput {
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debug_assert!(arr.len() == self.extra_bytes() as usize);
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let x = cpu.registers.index_x;
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let y = cpu.registers.index_y;
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let memory = &cpu.memory;
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fn read_address(mem: &Memory, addr: u16) -> [u8; 2] {
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let lo = mem.get_byte(addr);
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let hi = mem.get_byte(addr.wrapping_add(1));
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[lo, hi]
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}
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match self {
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AddressingMode::Accumulator | AddressingMode::Implied => {
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// Always the same -- no input
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OpInput::UseImplied
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}
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AddressingMode::Immediate => {
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// Use [u8, ..1] specified in instruction as input
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OpInput::UseImmediate(arr[0])
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}
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AddressingMode::ZeroPage => {
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// Use [u8, ..1] from instruction
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// Interpret as zero page address
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// (Output: an 8-bit zero-page address)
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OpInput::UseAddress(u16::from(arr[0]))
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}
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AddressingMode::ZeroPageX => {
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// Use [u8, ..1] from instruction
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// Add to X register (as u8 -- the final address is in 0-page)
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// (Output: an 8-bit zero-page address)
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OpInput::UseAddress(u16::from(arr[0].wrapping_add(x)))
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}
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AddressingMode::ZeroPageY => {
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// Use [u8, ..1] from instruction
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// Add to Y register (as u8 -- the final address is in 0-page)
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// (Output: an 8-bit zero-page address)
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OpInput::UseAddress(u16::from(arr[0].wrapping_add(y)))
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}
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AddressingMode::Relative => {
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// Use [u8, ..1] from instruction
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// (interpret as relative...)
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// (This is sign extended to a 16-but data type, but an unsigned one: u16. It's a
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// little weird, but it's so we can add the PC and the offset easily)
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let offset = arr[0];
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let sign_extend = if offset & 0x80 == 0x80 { 0xffu8 } else { 0x0 };
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let rel = u16::from_le_bytes([offset, sign_extend]);
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OpInput::UseRelative(rel)
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}
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AddressingMode::Absolute => {
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// Use [u8, ..2] from instruction as address
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(arr))
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}
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AddressingMode::AbsoluteX => {
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// Use [u8, ..2] from instruction as address, add X
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(arr).wrapping_add(xextend(x)))
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}
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AddressingMode::AbsoluteY => {
|
||||
// Use [u8, ..2] from instruction as address, add Y
|
||||
// (Output: a 16-bit address)
|
||||
OpInput::UseAddress(arr_to_addr(arr).wrapping_add(xextend(y)))
|
||||
}
|
||||
AddressingMode::Indirect => {
|
||||
// Use [u8, ..2] from instruction as an address. Interpret the
|
||||
// two bytes starting at that address as an address.
|
||||
// (Output: a 16-bit address)
|
||||
let slice = read_address(memory, arr_to_addr(arr));
|
||||
OpInput::UseAddress(arr_to_addr(&slice))
|
||||
}
|
||||
AddressingMode::IndexedIndirectX => {
|
||||
// Use [u8, ..1] from instruction
|
||||
// Add to X register with 0-page wraparound, like ZeroPageX.
|
||||
// This is where the absolute (16-bit) target address is stored.
|
||||
// (Output: a 16-bit address)
|
||||
let start = arr[0].wrapping_add(x);
|
||||
let slice = read_address(memory, u16::from(start));
|
||||
OpInput::UseAddress(arr_to_addr(&slice))
|
||||
}
|
||||
AddressingMode::IndirectIndexedY => {
|
||||
// Use [u8, ..1] from instruction
|
||||
// This is where the absolute (16-bit) target address is stored.
|
||||
// Add Y register to this address to get the final address
|
||||
// (Output: a 16-bit address)
|
||||
let start = arr[0];
|
||||
let slice = read_address(memory, u16::from(start));
|
||||
OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(y)))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub type DecodedInstr = (Instruction, OpInput);
|
||||
|
|
@ -776,26 +678,3 @@ pub static OPCODES: [Option<(Instruction, AddressingMode)>; 256] = [
|
|||
/*0xFF*/
|
||||
None,
|
||||
];
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
|
||||
#[test]
|
||||
fn zeropage_wrap_around() {
|
||||
use crate::instruction::AddressingMode;
|
||||
use crate::instruction::OpInput;
|
||||
use crate::instruction::CPU;
|
||||
|
||||
let mut cpu = CPU::new();
|
||||
cpu.registers.index_x = 9;
|
||||
|
||||
assert!(matches!(
|
||||
AddressingMode::ZeroPageX.process(&cpu, &[10]),
|
||||
OpInput::UseAddress(19)
|
||||
));
|
||||
assert!(matches!(
|
||||
AddressingMode::ZeroPageX.process(&cpu, &[250]),
|
||||
OpInput::UseAddress(3)
|
||||
));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue