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This commit is contained in:
Matthias 2022-06-07 19:30:29 +02:00
parent e829122a5a
commit 363dc47755
6 changed files with 33 additions and 66 deletions
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1
.gitignore vendored
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@ -65,3 +65,4 @@ TAGS.vi
\#*\#
src/.DS_Store
tmp.*.rs
.vscode

33
examples/euclidean_algo.rs
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@ -14,24 +14,23 @@ fn main() {
.collect::<Vec<u8>>();
let program = [
// (F)irst | (S)econd
// .algo
0xa5, 0x00, // Load from F to A
// .algo_
0x38, // Set carry flag
0xe5, 0x01, // Substract S from number in A (from F)
0xf0, 0x07, // Jump to .end if diff is zero
0x30, 0x08, // Jump to .swap if diff is negative
0x85, 0x00, // Load A to F
// (F)irst | (S)econd
// .algo
0xa5, 0x00, // Load from F to A
// .algo_
0x38, // Set carry flag
0xe5, 0x01, // Substract S from number in A (from F)
0xf0, 0x07, // Jump to .end if diff is zero
0x30, 0x08, // Jump to .swap if diff is negative
0x85, 0x00, // Load A to F
0x4c, 0x12, 0x00, // Jump to .algo_
// .end
0xa5, 0x00, // Load from S to A
0xff,
// .swap
0xa6, 0x00, // load F to X
0xa4, 0x01, // load S to Y
0x86, 0x01, // Store X to F
0x84, 0x00, // Store Y to S
// .end
0xa5, 0x00, // Load from S to A
0xff, // .swap
0xa6, 0x00, // load F to X
0xa4, 0x01, // load S to Y
0x86, 0x01, // Store X to F
0x84, 0x00, // Store Y to S
0x4c, 0x10, 0x00, // Jump to .algo
];

50
examples/mos6502.rs
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@ -39,25 +39,13 @@ fn main() {
// "Load" a program
let zero_page_data = [
// ZeroPage data start
0x00,
0x02, // ADC ZeroPage target
0x00,
0x04, // ADC ZeroPageX target
0x00,
0x00,
0x00,
0x00,
0x10, // ADC IndexedIndirectX address
0x00, 0x02, // ADC ZeroPage target
0x00, 0x04, // ADC ZeroPageX target
0x00, 0x00, 0x00, 0x00, 0x10, // ADC IndexedIndirectX address
0x80, // ADC IndexedIndirectX address
0x00,
0x00,
0x00,
0x00,
0x00,
0x08, // ADC IndirectIndexedY address
0x00, 0x00, 0x00, 0x00, 0x00, 0x08, // ADC IndirectIndexedY address
0x80, // ADC IndirectIndexedY address
];
@ -99,31 +87,11 @@ fn main() {
];
let data = [
0x00,
0x09, // ADC Absolute target
0x00,
0x00,
0x40, // ADC AbsoluteY target
0x00,
0x00,
0x00,
0x11, // ADC AbsoluteX target
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x12, // ADC IndexedIndirectX target
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x06, // ADC IndirectIndexedY target
0x00, 0x09, // ADC Absolute target
0x00, 0x00, 0x40, // ADC AbsoluteY target
0x00, 0x00, 0x00, 0x11, // ADC AbsoluteX target
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, // ADC IndexedIndirectX target
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, // ADC IndirectIndexedY target
];
cpu.memory.set_bytes(Address(0x0000), &zero_page_data);

10
src/cpu.rs
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@ -1366,11 +1366,11 @@ mod tests {
}
}
}
}
}
#[test]
fn stack_underflow() {
let mut cpu = CPU::new();
let _val: u8 = cpu.pull_from_stack();
#[test]
fn stack_underflow() {
let mut cpu = CPU::new();
let _val: u8 = cpu.pull_from_stack();
}
}

1
src/lib.rs
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@ -40,4 +40,3 @@ pub mod cpu;
pub mod instruction;
pub mod memory;
pub mod registers;

4
src/registers.rs
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@ -152,11 +152,11 @@ impl StackPointer {
}
pub fn decrement(&mut self) {
self.0 = self.0.wrapping_sub(1);
self.0 = self.0.wrapping_sub(1);
}
pub fn increment(&mut self) {
self.0 = self.0.wrapping_add(1);
self.0 = self.0.wrapping_add(1);
}
}