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a bit more commenting for the Instruction enum, and Addr vs AddrDiff distinction
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@ -25,6 +25,8 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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extern crate std;
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// Abbreviations
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//
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// General
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@ -76,19 +78,49 @@ impl Machine {
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}
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}
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#[deriving(PartialEq, Eq, PartialOrd, Ord)]
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pub struct StackPointer(u8);
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pub static STACK_POINTER_IN_MEMORY_LO : u16 = 0x0100;
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pub static STACK_POINTER_IN_MEMORY_HI : u16 = 0x01FF;
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#[deriving(PartialEq, Eq, PartialOrd, Ord)]
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pub struct Addr(u16);
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pub struct MemoryAddr(u16);
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#[deriving(PartialEq, Eq, PartialOrd, Ord)]
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pub struct AddrDiff(u16);
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pub fn stack_pointer_to_addr(StackPointer(x) : StackPointer) -> MemoryAddr
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{
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MemoryAddr(x as u16 + STACK_POINTER_IN_MEMORY_HI)
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// The idea here is that it doesn't make sense to add two addresses, but it
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// does make sense to add an address and an "address-difference". (If this
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// is too annoying to work with we should let it go.)
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impl Add<AddrDiff, Addr> for Addr {
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fn add(&self, &AddrDiff(rhs): &AddrDiff) -> Addr {
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let &Addr(lhs) = self;
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// We probably don't want to overflow when doing arithmetic in our own
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// code.
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debug_assert!({
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match lhs.checked_add(&rhs) {
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None => false,
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_ => true
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}
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});
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return Addr(lhs + rhs);
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}
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}
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#[deriving(Show)]
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pub static STACK_POINTER_IN_MEMORY_LO: Addr = Addr(0x0100);
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pub static STACK_POINTER_IN_MEMORY_HI: Addr = Addr(0x01FF);
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pub fn stack_pointer_to_addr(StackPointer(x) : StackPointer) -> Addr
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{
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STACK_POINTER_IN_MEMORY_LO + AddrDiff(x as u16)
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}
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// We can probably come up with a better way to represent address ranges
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pub static IRQ_INTERRUPT_VECTOR_LO: Addr = Addr(0xFFFE);
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pub static IRQ_INTERRUPT_VECTOR_HI: Addr = Addr(0xFFFE);
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#[deriving(Show, PartialEq, Eq)]
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pub enum Instruction
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// i/o vars should be listed as follows:
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// NV BDIZC A X Y SP PC M
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@ -104,24 +136,24 @@ pub enum Instruction
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, BMI // Branch if Minus............... | .. ..... PC = N
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, BNE // Branch if Not Equal........... | .. ..... PC = !Z
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, BPL // Branch if Positive............ | .. ..... PC = Z
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, BRK // BReaK......................... | .. .....
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, BVC // Branch if oVerflow Clear...... | .. .....
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, BVS // Branch if oVerflow Set........ | .. .....
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, CLC // CLear Carry flag.............. | .. .....
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, CLD // Clear Decimal Mode............ | .. .....
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, CLI // Clear Interrupt Disable....... | .. .....
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, CLV // Clear oVerflow flag........... | .. .....
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, CMP // Compare....................... | .. .....
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, CPX // Compare X register............ | .. .....
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, CPY // Compare Y register............ | .. .....
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, DEC // DECrement memory.............. | .. .....
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, DEX // DEcrement X register.......... | .. .....
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, DEY // DEcrement Y register.......... | .. .....
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, EOR // Exclusive OR.................. | .. .....
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, INC // INCrement memory.............. | .. .....
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, INX // INcrement X register.......... | .. .....
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, INY // INcrement Y register.......... | .. .....
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, JMP // JuMP.......................... | .. .....
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, BRK // BReaK......................... | .. B.... SP PC =
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, BVC // Branch if oVerflow Clear...... | .. ..... PC = !V
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, BVS // Branch if oVerflow Set........ | .. ..... PC = V
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, CLC // CLear Carry flag.............. | .. ....C = 0
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, CLD // Clear Decimal Mode............ | .. .D... = 0
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, CLI // Clear Interrupt Disable....... | .. ..I.. = 0
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, CLV // Clear oVerflow flag........... | .V ..... = 0
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, CMP // Compare....................... | N. ...ZC = A - M
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, CPX // Compare X register............ | N. ...ZC = X - M
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, CPY // Compare Y register............ | N. ...ZC = Y - M
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, DEC // DECrement memory.............. | N. ...Z. M = M - 1
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, DEX // DEcrement X register.......... | N. ...Z. X = X - 1
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, DEY // DEcrement Y register.......... | N. ...Z. Y = Y - 1
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, EOR // Exclusive OR (bitwise)........ | N. ...Z. A = A ^ M
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, INC // INCrement memory.............. | N. ...Z. M = M + 1
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, INX // INcrement X register.......... | N. ...Z. X = X + 1
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, INY // INcrement Y register.......... | N. ...Z. Y = Y + 1
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, JMP // JuMP.......................... | .. ..... PC =
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, JSR // Jump to SubRoutine............ | .. .....
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, LDA // LoaD Accumulator.............. | .. .....
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, LDX // LoaD X register............... | .. .....
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