From 453735ba5e366f164b1890724937b095272ca6e0 Mon Sep 17 00:00:00 2001
From: Sam M W <you@example.com>
Date: Sat, 27 Apr 2024 14:04:54 +0100
Subject: [PATCH] trb tsb

---
 src/cpu.rs         | 32 ++++++++++++++++++++++++++++++++
 src/instruction.rs | 10 ++++++++++
 2 files changed, 42 insertions(+)

diff --git a/src/cpu.rs b/src/cpu.rs
index fb91a13..4e0a230 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -653,6 +653,38 @@ impl<M: Bus, V: Variant> CPU<M, V> {
                 let val = self.registers.accumulator;
                 self.load_y_register(val);
             }
+            (Instruction::TRB, OpInput::UseAddress(addr)) => {
+                let val = self.memory.get_byte(addr);
+
+                // The zero flag is set based on the result of the 'and'.
+                self.registers.status.set_with_mask(
+                    Status::PS_ZERO,
+                    Status::new(StatusArgs {
+                        zero: 0 == (self.registers.accumulator & val),
+                        ..StatusArgs::none()
+                    }),
+                );
+
+                // The 1's in the accumulator set the corresponding bits in the operand
+                let res = self.registers.accumulator | val;
+                self.memory.set_byte(addr, res);
+            }
+            (Instruction::TSB, OpInput::UseAddress(addr)) => {
+                let val = self.memory.get_byte(addr);
+
+                // The zero flag is set based on the result of the 'and'.
+                self.registers.status.set_with_mask(
+                    Status::PS_ZERO,
+                    Status::new(StatusArgs {
+                        zero: 0 == (self.registers.accumulator & val),
+                        ..StatusArgs::none()
+                    }),
+                );
+
+                // The 1's in the accumulator clear the corresponding bits in the operand
+                let res = (self.registers.accumulator ^ 0xff) & val;
+                self.memory.set_byte(addr, res);
+            }
             (Instruction::TSX, OpInput::UseImplied) => {
                 let StackPointer(val) = self.registers.stack_pointer;
                 self.load_x_register(val);
diff --git a/src/instruction.rs b/src/instruction.rs
index 0be6ba4..acf768e 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -210,6 +210,12 @@ pub enum Instruction {
     // Transfer Accumulator to Y
     TAY,
 
+    // Test and Reset Bits
+    TRB,
+
+    // Test and Set Bits
+    TSB,
+
     // Transfer Stack pointer to X
     TSX,
 
@@ -623,6 +629,10 @@ impl crate::Variant for Cmos6502 {
             0xfa => Some((Instruction::PLX, AddressingMode::Implied)),
             0x5a => Some((Instruction::PHY, AddressingMode::Implied)),
             0xda => Some((Instruction::PHX, AddressingMode::Implied)),
+            0x04 => Some((Instruction::TSB, AddressingMode::ZeroPage)),
+            0x14 => Some((Instruction::TRB, AddressingMode::ZeroPage)),
+            0x0c => Some((Instruction::TSB, AddressingMode::Absolute)),
+            0x1c => Some((Instruction::TRB, AddressingMode::Absolute)),
             _ => Nmos6502::decode(opcode),
         }
     }