diff --git a/src/cpu.rs b/src/cpu.rs
index 1301203..30a8a56 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -322,6 +322,11 @@ impl<M: Bus, V: Variant> CPU<M, V> {
                 self.branch_if_positive(addr);
             }
 
+            (Instruction::BRA, OpInput::UseRelative(rel)) => {
+                let addr = self.registers.program_counter.wrapping_add(rel);
+                self.branch(addr);
+            }
+
             (Instruction::BRK, OpInput::UseImplied) => {
                 for b in self.registers.program_counter.wrapping_sub(1).to_be_bytes() {
                     self.push_on_stack(b);
@@ -1011,6 +1016,10 @@ impl<M: Bus, V: Variant> CPU<M, V> {
         }
     }
 
+    fn branch(&mut self, addr: u16) {
+        self.registers.program_counter = addr;
+    }
+
     fn branch_if_positive(&mut self, addr: u16) {
         if !self.registers.status.contains(Status::PS_NEGATIVE) {
             self.registers.program_counter = addr;
diff --git a/src/instruction.rs b/src/instruction.rs
index 4fada33..d25e670 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -55,6 +55,7 @@ pub enum Instruction {
     BMI,   // Branch if Minus............... | .. .....         PC   = N
     BNE,   // Branch if Not Equal........... | .. .....         PC   = !Z
     BPL,   // Branch if Positive............ | .. .....         PC   = Z
+    BRA,   // Unconditional BRAnch.......... | .. B....       S PC   =
     BRK,   // BReaK......................... | .. B....       S PC   =
     BVC,   // Branch if oVerflow Clear...... | .. .....         PC   = !V
     BVS,   // Branch if oVerflow Set........ | .. .....         PC   = V
@@ -495,6 +496,7 @@ impl crate::Variant for Cmos6502 {
         // TODO: We obviously need to add the other CMOS instructions here.
         match opcode {
             0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
+            0x80 => Some((Instruction::BRA, AddressingMode::Relative)),
             _ => Nmos6502::decode(opcode),
         }
     }