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622 lines
20 KiB
Coq
622 lines
20 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.11 2004/05/07 11:02:26 rherveille Exp $
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//
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// $Date: 2004/05/07 11:02:26 $
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// $Revision: 1.11 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: i2c_master_bit_ctrl.v,v $
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// Revision 1.11 2004/05/07 11:02:26 rherveille
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// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
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//
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// Revision 1.10 2003/08/09 07:01:33 rherveille
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// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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// Fixed a potential bug in the byte controller's host-acknowledge generation.
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//
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// Revision 1.9 2003/03/10 14:26:37 rherveille
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// Fixed cmd_ack generation item (no bug).
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//
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// Revision 1.8 2003/02/05 00:06:10 rherveille
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// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
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//
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// Revision 1.7 2002/12/26 16:05:12 rherveille
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// Small code simplifications
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//
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// Revision 1.6 2002/12/26 15:02:32 rherveille
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// Core is now a Multimaster I2C controller
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//
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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//
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Fixed some reported minor start/stop generation timing issuess.
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//
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// Revision 1.3 2002/06/15 07:37:03 rherveille
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// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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//
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// Revision 1.2 2001/11/05 11:59:25 rherveille
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// Fixed wb_ack_o generation bug.
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// Fixed bug in the byte_controller statemachine.
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// Added headers.
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//
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//
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/////////////////////////////////////
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// Bit controller section
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/////////////////////////////////////
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//
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// Translate simple commands into SCL/SDA transitions
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// Each command has 5 states, A/B/C/D/idle
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//
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// start: SCL ~~~~~~~~~~\____
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// SDA ~~~~~~~~\______
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// x | A | B | C | D | i
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//
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// repstart SCL ____/~~~~\___
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// SDA __/~~~\______
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// x | A | B | C | D | i
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//
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// stop SCL ____/~~~~~~~~
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// SDA ==\____/~~~~~
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// x | A | B | C | D | i
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//
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//- write SCL ____/~~~~\____
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// SDA ==X=========X=
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// x | A | B | C | D | i
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//
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//- read SCL ____/~~~~\____
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// SDA XXXX=====XXXX
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// x | A | B | C | D | i
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//
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// Timing: Normal mode Fast mode
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///////////////////////////////////////////////////////////////////////
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// Fscl 100KHz 400KHz
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// Th_scl 4.0us 0.6us High period of SCL
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// Tl_scl 4.7us 1.3us Low period of SCL
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// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
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// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "i2c_master_defines.v"
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module i2c_master_bit_ctrl(
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clk, rst, nReset,
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clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
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scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
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);
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//
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// inputs & outputs
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//
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input clk;
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input rst;
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input nReset;
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input ena; // core enable signal
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input [15:0] clk_cnt; // clock prescale value
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input [5:0] cmd;
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output cmd_ack; // command complete acknowledge
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reg cmd_ack;
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output busy; // i2c bus busy
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reg busy;
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output al; // i2c bus arbitration lost
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reg al;
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input din;
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output dout;
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reg dout;
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// I2C lines
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input scl_i; // i2c clock line input
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output scl_o; // i2c clock line output
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output scl_oen; // i2c clock line output enable (active low)
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reg scl_oen;
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input sda_i; // i2c data line input
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output sda_o; // i2c data line output
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output sda_oen; // i2c data line output enable (active low)
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reg sda_oen;
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//
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// variable declarations
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//
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg dscl_oen; // delayed scl_oen
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reg sda_chk; // check SDA output (Multi-master arbitration)
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reg clk_en; // clock generation signals
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wire slave_wait;
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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// state machine variable
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reg [24:0] c_state;
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//
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// module body
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//
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// delay scl_oen
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always @(posedge clk)
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dscl_oen <= #1 scl_oen;
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assign slave_wait = dscl_oen && !sSCL;
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// generate clk enable signal
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always @(posedge clk or negedge nReset)
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if(~nReset)
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begin
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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end
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else if (rst)
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begin
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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end
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else if ( ~|cnt || ~ena)
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if (~slave_wait)
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begin
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cnt <= #1 clk_cnt;
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clk_en <= #1 1'b1;
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end
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else
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begin
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cnt <= #1 cnt;
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clk_en <= #1 1'b0;
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end
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else
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begin
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cnt <= #1 cnt - 16'h1;
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clk_en <= #1 1'b0;
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end
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// generate bus status controller
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reg dSCL, dSDA;
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reg sta_condition;
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reg sto_condition;
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// synchronize SCL and SDA inputs
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// reduce metastability risc
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always @(posedge clk or negedge nReset)
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if (~nReset)
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begin
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sSCL <= #1 1'b1;
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sSDA <= #1 1'b1;
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dSCL <= #1 1'b1;
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dSDA <= #1 1'b1;
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end
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else if (rst)
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begin
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sSCL <= #1 1'b1;
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sSDA <= #1 1'b1;
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dSCL <= #1 1'b1;
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dSDA <= #1 1'b1;
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end
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else
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begin
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sSCL <= #1 scl_i;
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sSDA <= #1 sda_i;
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dSCL <= #1 sSCL;
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dSDA <= #1 sSDA;
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end
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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always @(posedge clk or negedge nReset)
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if (~nReset)
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begin
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sta_condition <= #1 1'b0;
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sto_condition <= #1 1'b0;
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end
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else if (rst)
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begin
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sta_condition <= #1 1'b0;
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sto_condition <= #1 1'b0;
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end
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else
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begin
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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end
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// generate i2c bus busy signal
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always @(posedge clk or negedge nReset)
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if(!nReset)
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busy <= #1 1'b0;
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else if (rst)
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busy <= #1 1'b0;
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else
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busy <= #1 (sta_condition | busy) & ~sto_condition;
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// generate arbitration lost signal
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// aribitration lost when:
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// 1) master drives SDA high, but the i2c bus is low
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// 2) stop detected while not requested
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reg cmd_stop;
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always @(posedge clk or negedge nReset)
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if (~nReset)
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cmd_stop <= #1 1'b0;
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else if (rst)
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cmd_stop <= #1 1'b0;
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else if (clk_en)
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cmd_stop <= #1 (cmd & (`I2C_CMD_STOP|`SPI_CMD_WRITE|`SPI_CMD_READ)) != 6'b000000;
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always @(posedge clk or negedge nReset)
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if (~nReset)
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al <= #1 1'b0;
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else if (rst)
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al <= #1 1'b0;
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else
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
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// generate dout signal (store SDA on rising edge of SCL)
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always @(posedge clk)
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if(sSCL & ~dSCL)
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dout <= #1 sSDA;
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// generate statemachine
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// nxt_state decoder
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parameter [24:0] idle = 25'b0_0000_0000_0000_0000_0000_0000;
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parameter [24:0] start_a = 25'b0_0000_0000_0000_0000_0000_0001;
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parameter [24:0] start_b = 25'b0_0000_0000_0000_0000_0000_0010;
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parameter [24:0] start_c = 25'b0_0000_0000_0000_0000_0000_0100;
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parameter [24:0] start_d = 25'b0_0000_0000_0000_0000_0000_1000;
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parameter [24:0] start_e = 25'b0_0000_0000_0000_0000_0001_0000;
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parameter [24:0] stop_a = 25'b0_0000_0000_0000_0000_0010_0000;
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parameter [24:0] stop_b = 25'b0_0000_0000_0000_0000_0100_0000;
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parameter [24:0] stop_c = 25'b0_0000_0000_0000_0000_1000_0000;
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parameter [24:0] stop_d = 25'b0_0000_0000_0000_0001_0000_0000;
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parameter [24:0] rd_a = 25'b0_0000_0000_0000_0010_0000_0000;
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parameter [24:0] rd_b = 25'b0_0000_0000_0000_0100_0000_0000;
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parameter [24:0] rd_c = 25'b0_0000_0000_0000_1000_0000_0000;
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parameter [24:0] rd_d = 25'b0_0000_0000_0001_0000_0000_0000;
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parameter [24:0] wr_a = 25'b0_0000_0000_0010_0000_0000_0000;
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parameter [24:0] wr_b = 25'b0_0000_0000_0100_0000_0000_0000;
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parameter [24:0] wr_c = 25'b0_0000_0000_1000_0000_0000_0000;
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parameter [24:0] wr_d = 25'b0_0000_0001_0000_0000_0000_0000;
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parameter [24:0] spi_rd_a = 25'b0_0000_0010_0000_0000_0000_0000;
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parameter [24:0] spi_rd_b = 25'b0_0000_0100_0000_0000_0000_0000;
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parameter [24:0] spi_rd_c = 25'b0_0000_1000_0000_0000_0000_0000;
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parameter [24:0] spi_rd_d = 25'b0_0001_0000_0000_0000_0000_0000;
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parameter [24:0] spi_wr_a = 25'b0_0010_0000_0000_0000_0000_0000;
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parameter [24:0] spi_wr_b = 25'b0_0100_0000_0000_0000_0000_0000;
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parameter [24:0] spi_wr_c = 25'b0_1000_0000_0000_0000_0000_0000;
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parameter [24:0] spi_wr_d = 25'b1_0000_0000_0000_0000_0000_0000;
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always @(posedge clk or negedge nReset)
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if (!nReset)
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begin
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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sda_chk <= #1 1'b0;
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end
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else if (rst | al)
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begin
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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sda_chk <= #1 1'b0;
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end
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else
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begin
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cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
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if (clk_en)
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case (c_state)
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// idle state
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idle:
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begin
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case (cmd)
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`I2C_CMD_START:
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c_state <= #1 start_a;
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`I2C_CMD_STOP:
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c_state <= #1 stop_a;
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`I2C_CMD_WRITE:
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c_state <= #1 wr_a;
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`I2C_CMD_READ:
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c_state <= #1 rd_a;
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`SPI_CMD_WRITE:
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c_state <= #1 spi_wr_a;
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`SPI_CMD_READ:
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c_state <= #1 spi_rd_a;
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default:
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c_state <= #1 idle;
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endcase
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_chk <= #1 1'b0; // don't check SDA output
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end
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// start
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start_a:
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begin
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c_state <= #1 start_b;
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 1'b1; // set SDA high
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sda_chk <= #1 1'b0; // don't check SDA output
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end
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start_b:
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begin
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c_state <= #1 start_c;
|
||
|
scl_oen <= #1 1'b1; // set SCL high
|
||
|
sda_oen <= #1 1'b1; // keep SDA high
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
start_c:
|
||
|
begin
|
||
|
c_state <= #1 start_d;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 1'b0; // set SDA low
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
start_d:
|
||
|
begin
|
||
|
c_state <= #1 start_e;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 1'b0; // keep SDA low
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
start_e:
|
||
|
begin
|
||
|
c_state <= #1 idle;
|
||
|
cmd_ack <= #1 1'b1;
|
||
|
scl_oen <= #1 1'b0; // set SCL low
|
||
|
sda_oen <= #1 1'b0; // keep SDA low
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
// stop
|
||
|
stop_a:
|
||
|
begin
|
||
|
c_state <= #1 stop_b;
|
||
|
scl_oen <= #1 1'b0; // keep SCL low
|
||
|
sda_oen <= #1 1'b0; // set SDA low
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
stop_b:
|
||
|
begin
|
||
|
c_state <= #1 stop_c;
|
||
|
scl_oen <= #1 1'b1; // set SCL high
|
||
|
sda_oen <= #1 1'b0; // keep SDA low
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
stop_c:
|
||
|
begin
|
||
|
c_state <= #1 stop_d;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 1'b0; // keep SDA low
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
stop_d:
|
||
|
begin
|
||
|
c_state <= #1 idle;
|
||
|
cmd_ack <= #1 1'b1;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 1'b1; // set SDA high
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
// read
|
||
|
rd_a:
|
||
|
begin
|
||
|
c_state <= #1 rd_b;
|
||
|
scl_oen <= #1 1'b0; // keep SCL low
|
||
|
sda_oen <= #1 1'b1; // tri-state SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
rd_b:
|
||
|
begin
|
||
|
c_state <= #1 rd_c;
|
||
|
scl_oen <= #1 1'b1; // set SCL high
|
||
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
rd_c:
|
||
|
begin
|
||
|
c_state <= #1 rd_d;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
rd_d:
|
||
|
begin
|
||
|
c_state <= #1 idle;
|
||
|
cmd_ack <= #1 1'b1;
|
||
|
scl_oen <= #1 1'b0; // set SCL low
|
||
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
// write
|
||
|
wr_a:
|
||
|
begin
|
||
|
c_state <= #1 wr_b;
|
||
|
scl_oen <= #1 1'b0; // keep SCL low
|
||
|
sda_oen <= #1 din; // set SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
||
|
end
|
||
|
|
||
|
wr_b:
|
||
|
begin
|
||
|
c_state <= #1 wr_c;
|
||
|
scl_oen <= #1 1'b1; // set SCL high
|
||
|
sda_oen <= #1 din; // keep SDA
|
||
|
sda_chk <= #1 1'b1; // check SDA output
|
||
|
end
|
||
|
|
||
|
wr_c:
|
||
|
begin
|
||
|
c_state <= #1 wr_d;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 din;
|
||
|
sda_chk <= #1 1'b1; // check SDA output
|
||
|
end
|
||
|
|
||
|
wr_d:
|
||
|
begin
|
||
|
c_state <= #1 idle;
|
||
|
cmd_ack <= #1 1'b1;
|
||
|
scl_oen <= #1 1'b0; // set SCL low
|
||
|
sda_oen <= #1 din;
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
||
|
end
|
||
|
|
||
|
// read (last SPI bit)
|
||
|
spi_rd_a:
|
||
|
begin
|
||
|
c_state <= #1 spi_rd_b;
|
||
|
scl_oen <= #1 1'b0; // set SCL low
|
||
|
sda_oen <= #1 1'b1; // tri-state SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
spi_rd_b:
|
||
|
begin
|
||
|
c_state <= #1 spi_rd_c;
|
||
|
scl_oen <= #1 1'b0; // keep SCL low
|
||
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
spi_rd_c:
|
||
|
begin
|
||
|
c_state <= #1 spi_rd_d;
|
||
|
scl_oen <= #1 1'b1; // set SCL high
|
||
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
spi_rd_d:
|
||
|
begin
|
||
|
c_state <= #1 idle;
|
||
|
cmd_ack <= #1 1'b1;
|
||
|
scl_oen <= #1 1'b1; // tri-state SCL
|
||
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
// write (last SPI bit)
|
||
|
spi_wr_a:
|
||
|
begin
|
||
|
c_state <= #1 spi_wr_b;
|
||
|
scl_oen <= #1 1'b0; // set SCL low
|
||
|
sda_oen <= #1 1'b1; // keep SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
spi_wr_b:
|
||
|
begin
|
||
|
c_state <= #1 spi_wr_c;
|
||
|
scl_oen <= #1 1'b0; // keep SCL low
|
||
|
sda_oen <= #1 din; // set SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
spi_wr_c:
|
||
|
begin
|
||
|
c_state <= #1 spi_wr_d;
|
||
|
scl_oen <= #1 1'b1; // keep SCL high
|
||
|
sda_oen <= #1 din; // keep SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
spi_wr_d:
|
||
|
begin
|
||
|
c_state <= #1 idle;
|
||
|
cmd_ack <= #1 1'b1;
|
||
|
scl_oen <= #1 1'b1; // tri-state SCL
|
||
|
sda_oen <= #1 1'b1; // tri-state SDA
|
||
|
sda_chk <= #1 1'b0; // don't check SDA output
|
||
|
end
|
||
|
|
||
|
default:
|
||
|
c_state <= #1 idle;
|
||
|
|
||
|
endcase
|
||
|
end
|
||
|
|
||
|
|
||
|
// assign scl and sda output (always gnd)
|
||
|
assign scl_o = 1'b0;
|
||
|
assign sda_o = 1'b0;
|
||
|
|
||
|
endmodule
|