mirror of https://github.com/marqs85/ossc.git
update qsys+bsp build logic and instructions
This commit is contained in:
marqs
parent
055a794b5e
commit
0905620b4d
44
README.md
44
README.md
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@ -31,8 +31,7 @@ SW toolchain build procedure
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git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
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cd riscv-gnu-toolchain
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./configure --prefix=/opt/riscv --enable-multilib
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make
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make install
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sudo make # sudo needed if installing under default /opt/riscv location
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~~~~
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2. Compile custom binary to IHEX converter:
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~~~~
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@ -40,6 +39,25 @@ gcc tools/bin2hex.c -o tools/bin2hex
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~~~~
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Building RTL (bitstream)
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--------------------------
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1. Initialize pulpino submodules (once after cloning ossc project or when submoduled have been updated)
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~~~~
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git submodule update --init --recursive ip/pulpino_qsys
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~~~~
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2. Load the project (ossc.qpf) in Quartus
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3. Generate QSYS output files (only needed before first compilation or when QSYS structure has been modified)
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* Open Platform Designer (Tools -> Platform Designer)
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* Load platform configuration (sys.qsys)
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* Generate output (Generate -> Generate HDL, Generate)
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* Close Platform Designer
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* Run "touch software/sys_controller_bsp/bsp_timestamp" to acknowledge QSYS update
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3. Generate the FPGA bitstream (Processing -> Start Compilation)
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4. Ensure that there are no severe timing violations by looking into Timing Analyzer report
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NOTE: If the software image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) was not up to date at the time of compilation, bitstream can be quickly rebuilt with updated hex by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
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Building software image
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--------------------------
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1. Enter software root directory:
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@ -55,28 +73,16 @@ OPTIONS may include following definitions:
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* ENABLE_AUDIO=y (Includes audio setup code for v1.6 PCB / DIY audio add-on board)
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TARGET is typically one of the following:
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* all (Default target. Compiles an ELF for direct downloading to CPU during testing)
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* generate_hex (Generates a memory initialization file required for bitstream)
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* all (Default target. Compiles an ELF file)
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* generate_hex (Generates a memory initialization file required for bitstream and direct download)
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* clean (cleans ELF and intermediate files. Should be invoked every time OPTIONS are changed between compilations, expect with generate_hex where it is done automatically)
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3. Optionally test updated SW by directly downloading ELF to CPU via JTAG
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3. Optionally test updated SW by directly downloading memory image to block RAM via JTAG
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~~~~
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make rv-reprogram
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~~~~
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Building RTL (bitstream)
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--------------------------
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1. Initialize pulpino submodules (once after cloning ossc project)
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~~~~
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git submodule update --init --recursive ip/pulpino_qsys
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~~~~
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2. Load the project (ossc.qpf) in Quartus
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3. Generate the FPGA bitstream (Processing -> Start Compilation). NOTE: make sure software hex image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) is up to date before generating bitstream.
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4. Ensure that there are no severe timing violations by looking into Timing Analyzer report
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If only software image is updated, bitstream can be quickly rebuilt by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
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Installing firmware via JTAG
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--------------------------
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The bitstream can be either directly programmed into FPGA (volatile method, suitable for quick testing), or into serial flash chip where it is automatically loaded every time FPGA is subsequently powered on (nonvolatile method, suitable for long-term use).
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@ -108,11 +114,11 @@ Debugging
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--------------------------
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1. Rebuild the software in debug mode:
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~~~~
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make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"
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make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex
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~~~~
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NOTE: Fw update functionality via SD card is disabled in debug builds due to code space limitations. If audio support is enabled on debug build, other functionality needs to be disabled as well.
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2. Program CPU via JTAG and open terminal for UART
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2. Download memory image via JTAG and open terminal for UART
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~~~~
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make rv-reprogram && nios2-terminal
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~~~~
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10
ossc.qsf
10
ossc.qsf
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@ -227,14 +227,15 @@ set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 3
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
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set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
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set_global_assignment -name SDC_FILE ossc.sdc
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set_global_assignment -name QSYS_FILE sys.qsys
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set_global_assignment -name VERILOG_FILE rtl/ossc.v
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set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
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set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
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set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
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set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
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set_global_assignment -name QIP_FILE rtl/linebuf.qip
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set_global_assignment -name QIP_FILE rtl/pll_2x.qip
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set_global_assignment -name QIP_FILE rtl/pll_3x.qip
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@ -242,8 +243,7 @@ set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref_pre.qip
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set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref.qip
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set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
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set_global_assignment -name QIP_FILE rtl/mux5.qip
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set_global_assignment -name SDC_FILE ossc.sdc
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -426,7 +426,7 @@ $(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP))
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.PHONY: all
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all: build_pre_process
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all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR)
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all: Makefile bsp_timestamp $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR)
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all: build_post_process
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@ -465,23 +465,39 @@ ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE))
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$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.)
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endif
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Makefile: $(wildcard $(SETTINGS_FILE))
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@$(ECHO) Makefile not up to date.
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@$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
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@$(ECHO)
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@$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
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@$(ECHO)
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@exit 1
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#Makefile: $(wildcard $(SETTINGS_FILE))
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# @$(ECHO) Makefile not up to date.
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# @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
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# @$(ECHO)
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# @$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
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# @$(ECHO)
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# @exit 1
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ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE))
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$(warning Warning: SOPC File $(SOPC_FILE) could not be found.)
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endif
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public.mk: $(wildcard $(SOPC_FILE))
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@$(ECHO) Makefile not up to date.
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@$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
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#public.mk: $(wildcard $(SOPC_FILE))
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# @$(ECHO) Makefile not up to date.
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# @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
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# @$(ECHO)
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# @$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
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# @$(ECHO)
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# @exit 1
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bsp_timestamp: $(wildcard $(SOPC_FILE))
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@$(ECHO) BSP not up to date.
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@$(ECHO) $(SOPC_FILE) has been modified since the BSP was last updated.
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@$(ECHO)
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@$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
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@$(ECHO) "If you have not customized QSYS platform:"
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@$(ECHO) " 1. Open sys.qsys in Quartus Platform Designer, generate platform"
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@$(ECHO) " files (Generate -> Generate HDL, Generate) and run compilation"
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@$(ECHO) " 2. Run \"touch bsp_timestamp\" in BSP dir"
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@$(ECHO)
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@$(ECHO) "If you have customized and regenerated QSYS platform:"
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@$(ECHO) " 1. Update system.h, public.mk, Makefile etc. BSP files manually"
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@$(ECHO) " to match your updates"
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@$(ECHO) " 2. Run \"touch bsp_timestamp\" in BSP dir"
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@$(ECHO)
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@exit 1
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Binary file not shown.
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
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<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
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<!-- 2018.10.08.00:13:33 -->
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<!-- 2018.10.10.22:28:26 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1538946813</value>
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<value>1539199706</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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