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update qsys+bsp build logic and instructions

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marqs 2018-10-11 00:04:32 +03:00
parent 055a794b5e
commit 0905620b4d
5 changed files with 60 additions and 38 deletions
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44
README.md
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@ -31,8 +31,7 @@ SW toolchain build procedure
git clone --recursive https://github.com/riscv/riscv-gnu-toolchain git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain cd riscv-gnu-toolchain
./configure --prefix=/opt/riscv --enable-multilib ./configure --prefix=/opt/riscv --enable-multilib
make sudo make # sudo needed if installing under default /opt/riscv location
make install
~~~~ ~~~~
2. Compile custom binary to IHEX converter: 2. Compile custom binary to IHEX converter:
~~~~ ~~~~
@ -40,6 +39,25 @@ gcc tools/bin2hex.c -o tools/bin2hex
~~~~ ~~~~
Building RTL (bitstream)
--------------------------
1. Initialize pulpino submodules (once after cloning ossc project or when submoduled have been updated)
~~~~
git submodule update --init --recursive ip/pulpino_qsys
~~~~
2. Load the project (ossc.qpf) in Quartus
3. Generate QSYS output files (only needed before first compilation or when QSYS structure has been modified)
* Open Platform Designer (Tools -> Platform Designer)
* Load platform configuration (sys.qsys)
* Generate output (Generate -> Generate HDL, Generate)
* Close Platform Designer
* Run "touch software/sys_controller_bsp/bsp_timestamp" to acknowledge QSYS update
3. Generate the FPGA bitstream (Processing -> Start Compilation)
4. Ensure that there are no severe timing violations by looking into Timing Analyzer report
NOTE: If the software image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) was not up to date at the time of compilation, bitstream can be quickly rebuilt with updated hex by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
Building software image Building software image
-------------------------- --------------------------
1. Enter software root directory: 1. Enter software root directory:
@ -55,28 +73,16 @@ OPTIONS may include following definitions:
* ENABLE_AUDIO=y (Includes audio setup code for v1.6 PCB / DIY audio add-on board) * ENABLE_AUDIO=y (Includes audio setup code for v1.6 PCB / DIY audio add-on board)
TARGET is typically one of the following: TARGET is typically one of the following:
* all (Default target. Compiles an ELF for direct downloading to CPU during testing) * all (Default target. Compiles an ELF file)
* generate_hex (Generates a memory initialization file required for bitstream) * generate_hex (Generates a memory initialization file required for bitstream and direct download)
* clean (cleans ELF and intermediate files. Should be invoked every time OPTIONS are changed between compilations, expect with generate_hex where it is done automatically) * clean (cleans ELF and intermediate files. Should be invoked every time OPTIONS are changed between compilations, expect with generate_hex where it is done automatically)
3. Optionally test updated SW by directly downloading ELF to CPU via JTAG 3. Optionally test updated SW by directly downloading memory image to block RAM via JTAG
~~~~ ~~~~
make rv-reprogram make rv-reprogram
~~~~ ~~~~
Building RTL (bitstream)
--------------------------
1. Initialize pulpino submodules (once after cloning ossc project)
~~~~
git submodule update --init --recursive ip/pulpino_qsys
~~~~
2. Load the project (ossc.qpf) in Quartus
3. Generate the FPGA bitstream (Processing -> Start Compilation). NOTE: make sure software hex image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) is up to date before generating bitstream.
4. Ensure that there are no severe timing violations by looking into Timing Analyzer report
If only software image is updated, bitstream can be quickly rebuilt by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
Installing firmware via JTAG Installing firmware via JTAG
-------------------------- --------------------------
The bitstream can be either directly programmed into FPGA (volatile method, suitable for quick testing), or into serial flash chip where it is automatically loaded every time FPGA is subsequently powered on (nonvolatile method, suitable for long-term use). The bitstream can be either directly programmed into FPGA (volatile method, suitable for quick testing), or into serial flash chip where it is automatically loaded every time FPGA is subsequently powered on (nonvolatile method, suitable for long-term use).
@ -108,11 +114,11 @@ Debugging
-------------------------- --------------------------
1. Rebuild the software in debug mode: 1. Rebuild the software in debug mode:
~~~~ ~~~~
make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex
~~~~ ~~~~
NOTE: Fw update functionality via SD card is disabled in debug builds due to code space limitations. If audio support is enabled on debug build, other functionality needs to be disabled as well. NOTE: Fw update functionality via SD card is disabled in debug builds due to code space limitations. If audio support is enabled on debug build, other functionality needs to be disabled as well.
2. Program CPU via JTAG and open terminal for UART 2. Download memory image via JTAG and open terminal for UART
~~~~ ~~~~
make rv-reprogram && nios2-terminal make rv-reprogram && nios2-terminal
~~~~ ~~~~

10
ossc.qsf
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@ -227,14 +227,15 @@ set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name SEED 3 set_global_assignment -name SEED 3
set_global_assignment -name VERILOG_FILE rtl/videogen.v set_global_assignment -name VERILOG_FILE rtl/videogen.v
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
set_global_assignment -name SDC_FILE ossc.sdc
set_global_assignment -name QSYS_FILE sys.qsys
set_global_assignment -name VERILOG_FILE rtl/ossc.v set_global_assignment -name VERILOG_FILE rtl/ossc.v
set_global_assignment -name VERILOG_FILE rtl/scanconverter.v set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
set_global_assignment -name VERILOG_FILE rtl/lat_tester.v set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
set_global_assignment -name QIP_FILE rtl/linebuf.qip set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name QIP_FILE rtl/pll_2x.qip set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/pll_3x.qip set_global_assignment -name QIP_FILE rtl/pll_3x.qip
@ -242,8 +243,7 @@ set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref_pre.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref.qip set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
set_global_assignment -name QIP_FILE rtl/mux5.qip set_global_assignment -name QIP_FILE rtl/mux5.qip
set_global_assignment -name SDC_FILE ossc.sdc
set_global_assignment -name CDF_FILE output_files/Chain1.cdf set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

40
software/sys_controller_bsp/Makefile
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@ -426,7 +426,7 @@ $(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP))
.PHONY: all .PHONY: all
all: build_pre_process all: build_pre_process
all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) all: Makefile bsp_timestamp $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR)
all: build_post_process all: build_post_process
@ -465,23 +465,39 @@ ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE))
$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) $(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.)
endif endif
Makefile: $(wildcard $(SETTINGS_FILE)) #Makefile: $(wildcard $(SETTINGS_FILE))
@$(ECHO) Makefile not up to date. # @$(ECHO) Makefile not up to date.
@$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. # @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
@$(ECHO) # @$(ECHO)
@$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir. # @$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
@$(ECHO) # @$(ECHO)
@exit 1 # @exit 1
ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE))
$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) $(warning Warning: SOPC File $(SOPC_FILE) could not be found.)
endif endif
public.mk: $(wildcard $(SOPC_FILE)) #public.mk: $(wildcard $(SOPC_FILE))
@$(ECHO) Makefile not up to date. # @$(ECHO) Makefile not up to date.
@$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. # @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
# @$(ECHO)
# @$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
# @$(ECHO)
# @exit 1
bsp_timestamp: $(wildcard $(SOPC_FILE))
@$(ECHO) BSP not up to date.
@$(ECHO) $(SOPC_FILE) has been modified since the BSP was last updated.
@$(ECHO) @$(ECHO)
@$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir. @$(ECHO) "If you have not customized QSYS platform:"
@$(ECHO) " 1. Open sys.qsys in Quartus Platform Designer, generate platform"
@$(ECHO) " files (Generate -> Generate HDL, Generate) and run compilation"
@$(ECHO) " 2. Run \"touch bsp_timestamp\" in BSP dir"
@$(ECHO)
@$(ECHO) "If you have customized and regenerated QSYS platform:"
@$(ECHO) " 1. Update system.h, public.mk, Makefile etc. BSP files manually"
@$(ECHO) " to match your updates"
@$(ECHO) " 2. Run \"touch bsp_timestamp\" in BSP dir"
@$(ECHO) @$(ECHO)
@exit 1 @exit 1

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software/sys_controller_bsp/libhal_bsp.a
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4
sys.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS"> <EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 17.1 590 (Future versions may contain additional information.) --> <!-- Format version 17.1 590 (Future versions may contain additional information.) -->
<!-- 2018.10.08.00:13:33 --> <!-- 2018.10.10.22:28:26 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1538946813</value> <value>1539199706</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>