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simplify timing constraints

This commit is contained in:
marqs 2018-03-06 23:53:48 +02:00
parent bd1d58660c
commit 0ab31b30b4
8 changed files with 449 additions and 309 deletions
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2
ossc.qsf
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@ -241,6 +241,8 @@ set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
set_global_assignment -name QIP_FILE rtl/mux5.qip
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

88
ossc.sdc
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@ -9,14 +9,40 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
### Scanconverter clock constraints ###
create_clock -period 108MHz -name pclk_direct [get_ports PCLK_in]
create_clock -period 33MHz -name pclk_indirect [get_ports PCLK_in] -add
create_clock -period 108MHz -name pclk_1x [get_ports PCLK_in]
create_clock -period 33MHz -name pclk_2x_source [get_ports PCLK_in] -add
create_clock -period 33MHz -name pclk_3x_source [get_ports PCLK_in] -add
create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
#derive_pll_clocks
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
create_generated_clock -master_clock pclk_2x_source -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_3x_source -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_4x_source -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
create_generated_clock -master_clock pclk_5x_source -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
# retrieve post-map/post-fix clkmux source and output pins dynamically
set clkmux_source [get_pins -nowarn scanconverter_inst|mux5_inst|LPM_MUX_component|auto_generated|muxlut_*clkctrl|inclk[0]]
set clkmux_output [get_pins -nowarn scanconverter_inst|mux5_inst|LPM_MUX_component|auto_generated|muxlut_*clkctrl|outclk]
if {[get_collection_size $clkmux_source] != 1} {
set clkmux_source [get_pins scanconverter_inst|mux5_inst|LPM_MUX_component|auto_generated|muxlut_result*|dataa]
set clkmux_output [get_pins scanconverter_inst|mux5_inst|LPM_MUX_component|auto_generated|muxlut_result*|combout]
}
# create postmux clocks which clock postprocess pipeline
create_generated_clock -master_clock pclk_1x -source $clkmux_source -multiply_by 1 -name pclk_1x_postmux $clkmux_output
create_generated_clock -master_clock pclk_2x -source $clkmux_source -multiply_by 1 -name pclk_2x_postmux $clkmux_output -add
create_generated_clock -master_clock pclk_3x -source $clkmux_source -multiply_by 1 -name pclk_3x_postmux $clkmux_output -add
create_generated_clock -master_clock pclk_4x -source $clkmux_source -multiply_by 1 -name pclk_4x_postmux $clkmux_output -add
create_generated_clock -master_clock pclk_5x -source $clkmux_source -multiply_by 1 -name pclk_5x_postmux $clkmux_output -add
# create output clocks that drive PCLK output pin
set pclk_out_port [get_ports HDMI_TX_PCLK]
create_generated_clock -master_clock pclk_1x -source $clkmux_source -multiply_by 1 -name pclk_1x_out $pclk_out_port
create_generated_clock -master_clock pclk_2x -source $clkmux_source -multiply_by 1 -name pclk_2x_out $pclk_out_port -add
create_generated_clock -master_clock pclk_3x -source $clkmux_source -multiply_by 1 -name pclk_3x_out $pclk_out_port -add
create_generated_clock -master_clock pclk_4x -source $clkmux_source -multiply_by 1 -name pclk_4x_out $pclk_out_port -add
create_generated_clock -master_clock pclk_5x -source $clkmux_source -multiply_by 1 -name pclk_5x_out $pclk_out_port -add
derive_clock_uncertainty
@ -24,52 +50,32 @@ derive_clock_uncertainty
set TVP_dmin 0
set TVP_dmax 1.5
set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
set_input_delay -clock pclk_direct -min $TVP_dmin $critinputs
set_input_delay -clock pclk_direct -max $TVP_dmax $critinputs
set_input_delay -clock pclk_indirect -min $TVP_dmin $critinputs -add_delay
set_input_delay -clock pclk_indirect -max $TVP_dmax $critinputs -add_delay
foreach_in_collection c [get_clocks "pclk_1x pclk_*_source"] {
set_input_delay -clock $c -min $TVP_dmin $critinputs -add_delay
set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
}
# output delay constraints
set IT_Tsu 1.0
set IT_Th -0.5
set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_direct -min $IT_Th $critoutputs_hdmi
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_direct -max $IT_Tsu $critoutputs_hdmi
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -max $IT_Tsu $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -min $IT_Th $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -max $IT_Tsu $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -min $IT_Th $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -max $IT_Tsu $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -min $IT_Th $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -max $IT_Tsu $critoutputs_hdmi -add_delay
foreach_in_collection c [get_clocks pclk_*_out] {
set_output_delay -clock $c -min $IT_Th $critoutputs_hdmi -add
set_output_delay -clock $c -max $IT_Tsu $critoutputs_hdmi -add
}
set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
### CPU/scanconverter clock relations ###
# Set direct pixel clock as exclusive group
set_clock_groups -exclusive -group {pclk_direct}
# Treat CPU clock asynchronous to pixel clocks
set_clock_groups -asynchronous -group {clk27}
# Ignore following clock transfers
set_false_path -from [get_clocks pclk_2x] -to [get_clocks {pclk_indirect pclk_3x pclk_4x pclk_5x}]
set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_indirect pclk_2x pclk_4x pclk_5x}]
set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_indirect pclk_2x pclk_3x pclk_5x}]
set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_indirect pclk_2x pclk_3x pclk_4x}]
# Ignore paths which would result from pclk_act switchover during postprocess chain
set pclk_act_regs [get_registers {scanconverter:scanconverter_inst|R_out* \
scanconverter:scanconverter_inst|G_out* \
scanconverter:scanconverter_inst|B_out* \
scanconverter:scanconverter_inst|HSYNC_out \
scanconverter:scanconverter_inst|VSYNC_out \
scanconverter:scanconverter_inst|DE_out \
scanconverter:scanconverter_inst|*_pp*}]
set_false_path -from [get_clocks {pclk_indirect}] -to $pclk_act_regs
set_false_path -from [get_clocks {pclk_indirect}] -to [get_ports HDMI_TX_*]
set_clock_groups -asynchronous -group \
{clk27} \
{pclk_1x pclk_1x_postmux pclk_1x_out} \
{pclk_2x_source pclk_2x pclk_2x_postmux pclk_2x_out} \
{pclk_3x_source pclk_3x pclk_3x_postmux pclk_3x_out} \
{pclk_4x_source pclk_4x pclk_4x_postmux pclk_4x_out} \
{pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
# Ignore paths from registers which are updated only at leading edge of vsync
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]

6
rtl/mux5.qip Normal file
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@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mux5.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mux5_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mux5_bb.v"]

117
rtl/mux5.v Normal file
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@ -0,0 +1,117 @@
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: mux5.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mux5 (
data0,
data1,
data2,
data3,
data4,
sel,
result);
input data0;
input data1;
input data2;
input data3;
input data4;
input [2:0] sel;
output result;
wire [0:0] sub_wire0;
wire sub_wire7 = data4;
wire sub_wire6 = data3;
wire sub_wire5 = data2;
wire sub_wire4 = data1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire result = sub_wire1;
wire sub_wire2 = data0;
wire [4:0] sub_wire3 = {sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire2};
lpm_mux LPM_MUX_component (
.data (sub_wire3),
.sel (sel),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 5,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 1,
LPM_MUX_component.lpm_widths = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
// Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
// Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
// Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2"
// Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3"
// Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4"
// Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
// Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
// Retrieval info: CONNECT: @data 0 0 1 0 data0 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 1 data1 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 2 data2 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 3 data3 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 4 data4 0 0 0 0
// Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
// Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5_bb.v TRUE
// Retrieval info: LIB_FILE: lpm

43
rtl/scanconverter.v
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@ -33,6 +33,12 @@
`define V_MULTMODE_4X 3'd3
`define V_MULTMODE_5X 3'd4
`define PCLK_MUX_1X 3'd0
`define PCLK_MUX_2X 3'd1
`define PCLK_MUX_3X 3'd2
`define PCLK_MUX_4X 3'd3
`define PCLK_MUX_5X 3'd4
`define H_MULTMODE_FULLWIDTH 2'h0
`define H_MULTMODE_ASPECTFIX 2'h1
`define H_MULTMODE_OPTIMIZED 2'h2
@ -91,7 +97,7 @@ module scanconverter (
wire pclk_act;
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
wire pclk_2x_lock, pclk_3x_lock;
wire linebuf_rdclock;
wire [2:0] pclk_mux_sel;
//RGB signals&registers: 8 bits per component -> 16.7M colors
wire [7:0] R_act, G_act, B_act;
@ -278,8 +284,7 @@ case (V_MULTMODE)
line_id_act = {2'b00, vcnt_1x[0]};
hcnt_act = hcnt_1x;
vcnt_act = vcnt_1x;
pclk_act = pclk_1x;
linebuf_rdclock = 0;
pclk_mux_sel = `PCLK_MUX_1X;
linebuf_hoffset = 0;
col_id_act = {2'b00, hcnt_1x[0]};
rlpf_trigger_act = 1'b1;
@ -294,16 +299,15 @@ case (V_MULTMODE)
line_id_act = {1'b0, line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x};
hcnt_act = hcnt_2x;
vcnt_act = vcnt_2x;
linebuf_rdclock = pclk_2x;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
pclk_act = pclk_2x;
pclk_mux_sel = `PCLK_MUX_2X;
linebuf_hoffset = hcnt_2x;
col_id_act = {2'b00, hcnt_2x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED: begin
pclk_act = pclk_1x; //special case: pclk bypass to enable 2x native sampling
pclk_mux_sel = `PCLK_MUX_1X; //special case: pclk bypass to enable 2x native sampling
linebuf_hoffset = hcnt_2x_opt;
col_id_act = {2'b00, hcnt_2x[1]};
rlpf_trigger_act = (hcnt_2x_opt_ctr == H_OPT_SCALE-1'b1);
@ -321,24 +325,21 @@ case (V_MULTMODE)
vcnt_act = vcnt_3x;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
pclk_act = pclk_3x;
linebuf_rdclock = pclk_3x;
pclk_mux_sel = `PCLK_MUX_3X;
linebuf_hoffset = hcnt_3x;
hcnt_act = hcnt_3x;
col_id_act = {2'b00, hcnt_3x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_ASPECTFIX: begin
pclk_act = pclk_4x;
linebuf_rdclock = pclk_4x;
pclk_mux_sel = `PCLK_MUX_4X;
linebuf_hoffset = hcnt_4x_aspfix;
hcnt_act = hcnt_4x_aspfix;
col_id_act = {2'b00, hcnt_4x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED: begin
pclk_act = pclk_3x;
linebuf_rdclock = pclk_3x;
pclk_mux_sel = `PCLK_MUX_3X;
linebuf_hoffset = hcnt_3x_opt;
hcnt_act = hcnt_3x;
col_id_act = hcnt_3x_opt_ctr;
@ -356,8 +357,7 @@ case (V_MULTMODE)
line_id_act = {1'b0, line_out_idx_4x};
hcnt_act = hcnt_4x;
vcnt_act = vcnt_4x;
pclk_act = pclk_4x;
linebuf_rdclock = pclk_4x;
pclk_mux_sel = `PCLK_MUX_4X;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
linebuf_hoffset = hcnt_4x;
@ -381,8 +381,7 @@ case (V_MULTMODE)
line_id_act = {2'b00, line_out_idx_5x};
hcnt_act = hcnt_5x;
vcnt_act = vcnt_5x;
pclk_act = pclk_5x;
linebuf_rdclock = pclk_5x;
pclk_mux_sel = `PCLK_MUX_5X;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
linebuf_hoffset = hcnt_5x_hscomp;
@ -422,13 +421,23 @@ wire [11:0] linebuf_wraddr = hcnt_1x-H_AVIDSTART;
linebuf linebuf_rgb (
.data({R_in_L, G_in_L, B_in_L}),
.rdaddress ( {~line_idx, linebuf_rdaddr[10:0]} ),
.rdclock ( linebuf_rdclock ),
.rdclock ( pclk_act ),
.wraddress( {line_idx, linebuf_wraddr[10:0]} ),
.wrclock ( pclk_1x ),
.wren ( !linebuf_wraddr[11] ),
.q ( {R_lbuf, G_lbuf, B_lbuf} )
);
mux5 mux5_inst (
.data0 ( pclk_1x ),
.data1 ( pclk_2x ),
.data2 ( pclk_3x ),
.data3 ( pclk_4x ),
.data4 ( pclk_5x ),
.sel ( pclk_mux_sel ),
.result ( pclk_act )
);
//Postprocess pipeline
//
// Latency with respect to h_cnt/v_cnt before 1st stage:

494
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

@ -1,6 +1,6 @@
:020000020000FC
:2000000000402074084008140800683A0000000000000000000000000000000000000000FE
:2000080006C02074DEE80014068020B4D68304140080207410A5611400C0207418E67214C3
:2000080006C02074DEE80014068020B4D6830A140080207410A5671400C0207418E67F14AA
:2000100010C00326100000151080010410FFFD360816AD800816BB80003FFF06DEFFFB0417
:2000180000BFE084D880000500800084D880004500800344D880008500800484DFC0041543
:20002000D88000C531803FCCD8C005173000022600BFE004000001060080100439C03FCC99
@ -26,7 +26,7 @@
:2000C000DFC00417DCC00317DC800217DC400117DC000017DEC00504F800283ADEFFFF0433
:2000C8000140FA04DFC00015081620C01009883ADFC00017DEC001040816BE41DEFFFF04F6
:2000D000000B883A010003C4DFC0001508102900000B883A01001844DFC00017DEC0010403
:2000D80008102901DEFFFD04DC000015040020B4842577048140008301000144DFC00215BB
:2000D80008102901DEFFFD04DC000015040020B484257D048140008301000144DFC00215B5
:2000E000DC40011508102900808000838100030300FFFEC41004D1FA20C6703A044001040A
:2000E8001085883A1085883A1884B03A01400F448809883A8080030508102900010000444F
:2000F000081031C08809883A014007440810290001400C04010018440810290001402C84E7
@ -40,7 +40,7 @@
:20013000050000441021883A9D00021E0486000400000106048C000401400044010003C440
:2001380008102900000B883A01000CC408102900900AD23A01000D04048020B40810290036
:20014000000B883A01000D440810290081403FCC01000C0408102900800AD23A01000C443A
:2001480094A5770429403FCC08102900800AD43A01000C8408102900000B883A010003C42F
:2001480094A57D0429403FCC08102900800AD43A01000C8408102900000B883A010003C429
:2001500008102900000B883A0100314408102900954002159D000226040002840000010688
:200158000400008400800044940001C5908001058C403FCC050000448D0002260005883A2F
:2001600000000106008003C401003804908001450140300408102900047FFF040100164407
@ -76,7 +76,7 @@
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4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 24, 2018 7:18:24 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1519492704534</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Mar 6, 2018 11:46:21 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1520372781076</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
<!-- 2018.02.24.18:26:12 -->
<!-- 2018.03.06.23:39:06 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1519489572</value>
<value>1520372346</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>