From 2319a6f8bd63b7c7c3a978274cc582f0bc679575 Mon Sep 17 00:00:00 2001 From: marqs Date: Tue, 28 Apr 2020 18:48:35 +0300 Subject: [PATCH] misc tool updates --- ossc_rtl.project | 38 +++++++++++++++++---------------- ossc_sw_bsp.project | 2 +- rtl/char_array.qip | 2 +- rtl/char_array.v | 9 ++++---- rtl/char_rom.qip | 2 +- rtl/char_rom.v | 9 ++++---- rtl/linebuf.qip | 2 +- rtl/linebuf.v | 9 ++++---- rtl/lpm_mult_4_hybr_ref.qip | 2 +- rtl/lpm_mult_4_hybr_ref.v | 9 ++++---- rtl/lpm_mult_4_hybr_ref_pre.qip | 2 +- rtl/lpm_mult_4_hybr_ref_pre.v | 9 ++++---- rtl/lpm_mult_4_sl.qip | 2 +- rtl/lpm_mult_4_sl.v | 9 ++++---- software/ossc_sw.project | 2 +- tools.project | 10 +++++---- 16 files changed, 64 insertions(+), 54 deletions(-) diff --git a/ossc_rtl.project b/ossc_rtl.project index a73e942..8a2ef14 100644 --- a/ossc_rtl.project +++ b/ossc_rtl.project @@ -1,5 +1,5 @@ - + @@ -24,6 +24,23 @@ + + + + + + + + + + + + + + + + + @@ -41,6 +58,7 @@ + @@ -79,6 +97,7 @@ + @@ -111,21 +130,4 @@ - - - - - - - - - - - - - - - - - diff --git a/ossc_sw_bsp.project b/ossc_sw_bsp.project index 195496d..77441f9 100644 --- a/ossc_sw_bsp.project +++ b/ossc_sw_bsp.project @@ -1,5 +1,5 @@ - + diff --git a/rtl/char_array.qip b/rtl/char_array.qip index 46ce66f..25972b5 100644 --- a/rtl/char_array.qip +++ b/rtl/char_array.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "19.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"] diff --git a/rtl/char_array.v b/rtl/char_array.v index ddb6284..7749333 100644 --- a/rtl/char_array.v +++ b/rtl/char_array.v @@ -14,13 +14,13 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition // ************************************************************ -//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Copyright (C) 2019 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic +//and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject @@ -30,7 +30,8 @@ //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. // synopsys translate_off diff --git a/rtl/char_rom.qip b/rtl/char_rom.qip index 4569a40..87a6fab 100644 --- a/rtl/char_rom.qip +++ b/rtl/char_rom.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "19.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"] diff --git a/rtl/char_rom.v b/rtl/char_rom.v index b280cf6..bf23e62 100644 --- a/rtl/char_rom.v +++ b/rtl/char_rom.v @@ -14,13 +14,13 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition // ************************************************************ -//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Copyright (C) 2019 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic +//and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject @@ -30,7 +30,8 @@ //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. // synopsys translate_off diff --git a/rtl/linebuf.qip b/rtl/linebuf.qip index 736388a..7a46411 100644 --- a/rtl/linebuf.qip +++ b/rtl/linebuf.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "19.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"] diff --git a/rtl/linebuf.v b/rtl/linebuf.v index c4605cb..d6769c9 100644 --- a/rtl/linebuf.v +++ b/rtl/linebuf.v @@ -14,13 +14,13 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition // ************************************************************ -//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Copyright (C) 2019 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic +//and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject @@ -30,7 +30,8 @@ //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. // synopsys translate_off diff --git a/rtl/lpm_mult_4_hybr_ref.qip b/rtl/lpm_mult_4_hybr_ref.qip index 12a44a4..dbdec75 100644 --- a/rtl/lpm_mult_4_hybr_ref.qip +++ b/rtl/lpm_mult_4_hybr_ref.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "19.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_bb.v"] diff --git a/rtl/lpm_mult_4_hybr_ref.v b/rtl/lpm_mult_4_hybr_ref.v index 118e639..4034a62 100644 --- a/rtl/lpm_mult_4_hybr_ref.v +++ b/rtl/lpm_mult_4_hybr_ref.v @@ -14,13 +14,13 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition // ************************************************************ -//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Copyright (C) 2019 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic +//and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject @@ -30,7 +30,8 @@ //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. // synopsys translate_off diff --git a/rtl/lpm_mult_4_hybr_ref_pre.qip b/rtl/lpm_mult_4_hybr_ref_pre.qip index 04f0083..6401ea6 100644 --- a/rtl/lpm_mult_4_hybr_ref_pre.qip +++ b/rtl/lpm_mult_4_hybr_ref_pre.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "19.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"] diff --git a/rtl/lpm_mult_4_hybr_ref_pre.v b/rtl/lpm_mult_4_hybr_ref_pre.v index 2bbca20..22b6b3e 100644 --- a/rtl/lpm_mult_4_hybr_ref_pre.v +++ b/rtl/lpm_mult_4_hybr_ref_pre.v @@ -14,13 +14,13 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition // ************************************************************ -//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Copyright (C) 2019 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic +//and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject @@ -30,7 +30,8 @@ //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. // synopsys translate_off diff --git a/rtl/lpm_mult_4_sl.qip b/rtl/lpm_mult_4_sl.qip index b659848..59d9ec6 100644 --- a/rtl/lpm_mult_4_sl.qip +++ b/rtl/lpm_mult_4_sl.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "19.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"] diff --git a/rtl/lpm_mult_4_sl.v b/rtl/lpm_mult_4_sl.v index abff035..5547bcf 100644 --- a/rtl/lpm_mult_4_sl.v +++ b/rtl/lpm_mult_4_sl.v @@ -14,13 +14,13 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition // ************************************************************ -//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Copyright (C) 2019 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic +//and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject @@ -30,7 +30,8 @@ //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. // synopsys translate_off diff --git a/software/ossc_sw.project b/software/ossc_sw.project index 952f87c..bb97e38 100644 --- a/software/ossc_sw.project +++ b/software/ossc_sw.project @@ -1,5 +1,5 @@ - + diff --git a/tools.project b/tools.project index ca422ca..c109df3 100644 --- a/tools.project +++ b/tools.project @@ -1,6 +1,9 @@ - + + + + - - - @@ -39,6 +39,7 @@ + @@ -77,6 +78,7 @@ +