From 434186d64ef032a7d3b5965e4405a0b954cbe339 Mon Sep 17 00:00:00 2001 From: marqs Date: Mon, 23 Jan 2017 00:56:17 +0200 Subject: [PATCH] Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes --- rtl/ossc.v | 5 +- rtl/scanconverter.v | 352 +-- .../mem_init/sys_onchip_memory2_0.hex | 2038 ++++++++--------- software/sys_controller/ossc/av_controller.c | 90 +- software/sys_controller/ossc/av_controller.h | 35 +- software/sys_controller/ossc/avconfig.c | 6 + software/sys_controller/ossc/avconfig.h | 10 +- software/sys_controller/ossc/controls.c | 2 +- software/sys_controller/ossc/firmware.h | 2 +- software/sys_controller/ossc/menu.c | 18 +- software/sys_controller/tvp7002/tvp7002.c | 16 +- software/sys_controller/tvp7002/tvp7002.h | 4 +- software/sys_controller/tvp7002/video_modes.c | 120 +- software/sys_controller/tvp7002/video_modes.h | 101 +- software/sys_controller_bsp/libhal_bsp.a | Bin 104226 -> 104226 bytes software/sys_controller_bsp/settings.bsp | 36 +- software/sys_controller_bsp/system.h | 53 +- sys.qsys | 86 +- sys.sopcinfo | 951 +++++++- 19 files changed, 2485 insertions(+), 1440 deletions(-) diff --git a/rtl/ossc.v b/rtl/ossc.v index a1f04c6..498e99b 100644 --- a/rtl/ossc.v +++ b/rtl/ossc.v @@ -58,6 +58,7 @@ wire h_unstable; wire [2:0] pclk_lock; wire [2:0] pll_lock_lost; wire [31:0] h_info; +wire [31:0] hscale_info; wire [31:0] v_info; wire [10:0] lines_out; wire [1:0] fpga_vsyncgen; @@ -198,7 +199,8 @@ sys sys_inst( .pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}), .pio_2_horizontal_info_out_export (h_info), .pio_3_vertical_info_out_export (v_info), - .pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}) + .pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}), + .pio_5_hscale_info_out_export (hscale_info), ); scanconverter scanconverter_inst ( @@ -212,6 +214,7 @@ scanconverter scanconverter_inst ( .B_in (B_in_L), .h_info (h_info), .v_info (v_info), + .hscale_info (hscale_info), .R_out (R_out), .G_out (G_out), .B_out (B_out), diff --git a/rtl/scanconverter.v b/rtl/scanconverter.v index 571b8ae..30276ec 100644 --- a/rtl/scanconverter.v +++ b/rtl/scanconverter.v @@ -22,14 +22,15 @@ `define HI 1'b1 `define LO 1'b0 -`define LINEMULT_DISABLE 2'h0 -`define LINEMULT_DOUBLE 2'h1 -`define LINEMULT_TRIPLE 2'h2 +`define V_MULTMODE_1X 3'd0 +`define V_MULTMODE_2X 3'd1 +`define V_MULTMODE_3X 3'd2 +`define V_MULTMODE_4X 3'd3 +`define V_MULTMODE_5X 3'd4 -`define LINETRIPLE_M0 2'h0 -`define LINETRIPLE_M1 2'h1 -`define LINETRIPLE_M2 2'h2 -`define LINETRIPLE_M3 2'h3 +`define H_MULTMODE_FULLWIDTH 2'h0 +`define H_MULTMODE_ASPECTFIX 2'h1 +`define H_MULTMODE_OPTIMIZED 2'h2 `define SCANLINES_OFF 2'h0 `define SCANLINES_H 2'h1 @@ -63,6 +64,7 @@ module scanconverter ( input PCLK_in, input [31:0] h_info, input [31:0] v_info, + input [31:0] hscale_info, output reg [7:0] R_out, output reg [7:0] G_out, output reg [7:0] B_out, @@ -77,17 +79,16 @@ module scanconverter ( output [10:0] lines_out ); -wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_3x_h1x, pclk_3x_h4x, pclk_3x_h5x; -wire pclk_out_1x, pclk_out_2x, pclk_out_3x, pclk_out_4x, pclk_out_3x_h4x, pclk_out_3x_h5x; +wire pclk_1x, pclk_2x, pclk_3x, pclk_4x; wire linebuf_rdclock; wire pclk_act; wire [1:0] slid_act; -wire pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock; +wire pclk_2x_lock, pclk_3x_lock; wire HSYNC_act, VSYNC_act; -reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_3x_h1x, HSYNC_pp1; +reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_pp1; reg VSYNC_1x, VSYNC_2x, VSYNC_pp1; reg [11:0] HSYNC_start; @@ -99,42 +100,46 @@ reg DATA_enable_pp1; wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written wire [11:0] hcnt_act; -reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_3x_h1x, hcnt_3x_h4x, hcnt_3x_h5x; +reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_3x_opt; + +reg [2:0] hcnt_3x_opt_ctr; wire [10:0] vcnt_act; reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, lines_1x, lines_2x; //max. 2047 -reg [9:0] vcnt_3x, vcnt_3x_h1x, lines_3x, lines_3x_h1x; //max. 1023 +reg [9:0] vcnt_3x, vcnt_3x_h1x, lines_3x; //max. 1023 -reg h_enable_3x_prev4x, h_enable_3x_prev3x_h4x, h_enable_3x_prev3x_h5x; -reg [1:0] hcnt_3x_h4x_ctr; -reg [1:0] hcnt_3x_h5x_ctr; +reg h_enable_3x_prev4x; -reg pclk_1x_prev3x, pclk_1x_prev3x_h1x; -reg [1:0] pclk_3x_cnt, pclk_3x_h1x_cnt; +reg pclk_1x_prev3x; +reg [1:0] pclk_3x_cnt; // Data enable reg h_enable_1x, v_enable_1x; reg h_enable_2x, v_enable_2x; -reg h_enable_3x, h_enable_3x_h1x, v_enable_3x, v_enable_3x_h1x; +reg h_enable_3x, v_enable_3x; reg prev_hs, prev_vs; reg [11:0] hmax[0:1]; reg line_idx; -reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_3x_h1x; +reg [1:0] line_out_idx_2x, line_out_idx_3x; -reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x, warn_pll_lock_lost_3x_lowfreq; +reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x; reg [10:0] H_ACTIVE; //max. 2047 reg [7:0] H_BACKPORCH; //max. 255 reg [10:0] V_ACTIVE; //max. 2047 reg [5:0] V_BACKPORCH; //max. 63 -reg [1:0] V_SCANLINES; +reg [1:0] V_SCANLINEMODE; reg [1:0] V_SCANLINEID; -reg [7:0] V_SCANLINESTR; +reg [7:0] H_SCANLINESTR; reg [5:0] V_MASK; -reg [1:0] H_LINEMULT; -reg [1:0] H_L3MODE; +reg [2:0] V_MULTMODE; +reg [1:0] H_MULTMODE; reg [5:0] H_MASK; +reg [9:0] H_OPT_STARTOFF; +reg [2:0] H_OPT_SCALE; +reg [2:0] H_OPT_SAMPLE_MULT; +reg [2:0] H_OPT_SAMPLE_SEL; //8 bits per component -> 16.7M colors reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1; @@ -142,15 +147,7 @@ wire [7:0] R_lbuf, G_lbuf, B_lbuf; wire [7:0] R_act, G_act, B_act; assign pclk_1x = PCLK_in; -assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock}; - -//Output sampled at the rising edge of active pclk -assign pclk_out_1x = PCLK_in; -assign pclk_out_2x = pclk_2x; -assign pclk_out_3x = pclk_3x; -assign pclk_out_4x = pclk_4x; -assign pclk_out_3x_h4x = pclk_3x_h4x; -assign pclk_out_3x_h5x = pclk_3x_h5x; +assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, 1'b0}; //Scanline generation function [7:0] apply_scanlines; @@ -207,13 +204,13 @@ function [7:0] apply_mask; //Non-critical signals and inactive clock combinations filtered out in SDC always @(*) begin - case (H_LINEMULT) - `LINEMULT_DISABLE: begin + case (V_MULTMODE) + `V_MULTMODE_1X: begin R_act = R_1x; G_act = G_1x; B_act = B_1x; DATA_enable_act = (h_enable_1x & v_enable_1x); - PCLK_out = pclk_out_1x; + PCLK_out = pclk_1x; HSYNC_act = HSYNC_1x; VSYNC_act = VSYNC_1x; lines_out = lines_1x; @@ -224,12 +221,12 @@ begin hcnt_act = hcnt_1x; vcnt_act = vcnt_1x; end - `LINEMULT_DOUBLE: begin + `V_MULTMODE_2X: begin R_act = R_lbuf; G_act = G_lbuf; B_act = B_lbuf; DATA_enable_act = (h_enable_2x & v_enable_2x); - PCLK_out = pclk_out_2x; + PCLK_out = pclk_2x; HSYNC_act = HSYNC_2x; VSYNC_act = VSYNC_2x; lines_out = lines_2x; @@ -240,104 +237,89 @@ begin hcnt_act = hcnt_2x; vcnt_act = vcnt_2x>>1; end - `LINEMULT_TRIPLE: begin + `V_MULTMODE_3X: begin R_act = R_lbuf; G_act = G_lbuf; B_act = B_lbuf; + HSYNC_act = HSYNC_3x; VSYNC_act = VSYNC_1x; - case (H_L3MODE) - `LINETRIPLE_M0: begin - DATA_enable_act = (h_enable_3x & v_enable_3x); - PCLK_out = pclk_out_3x; - HSYNC_act = HSYNC_3x; - lines_out = {1'b0, lines_3x}; + DATA_enable_act = (h_enable_3x & v_enable_3x); + lines_out = {1'b0, lines_3x}; + slid_act = line_out_idx_3x; + vcnt_act = vcnt_3x/2'h3; //divider generated + case (H_MULTMODE) + `H_MULTMODE_FULLWIDTH: begin + PCLK_out = pclk_3x; linebuf_rdclock = pclk_3x; linebuf_hoffset = hcnt_3x; pclk_act = pclk_3x; - slid_act = line_out_idx_3x; hcnt_act = hcnt_3x; - vcnt_act = vcnt_3x/2'h3; //divider generated end - `LINETRIPLE_M1: begin - DATA_enable_act = (h_enable_3x & v_enable_3x); - PCLK_out = pclk_out_4x; - HSYNC_act = HSYNC_3x; - lines_out = {1'b0, lines_3x}; + `H_MULTMODE_ASPECTFIX: begin + PCLK_out = pclk_4x; linebuf_rdclock = pclk_4x; linebuf_hoffset = hcnt_4x; pclk_act = pclk_4x; - slid_act = line_out_idx_3x; hcnt_act = hcnt_4x; - vcnt_act = vcnt_3x/2'h3; //divider generated end - `LINETRIPLE_M2: begin - DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x); - PCLK_out = pclk_out_3x_h4x; - HSYNC_act = HSYNC_3x_h1x; - lines_out = {1'b0, lines_3x_h1x}; - linebuf_rdclock = pclk_3x_h4x; - linebuf_hoffset = hcnt_3x_h4x; - pclk_act = pclk_3x_h4x; - slid_act = line_out_idx_3x_h1x; - hcnt_act = hcnt_3x_h4x; - vcnt_act = vcnt_3x_h1x/2'h3; //divider generated + `H_MULTMODE_OPTIMIZED: begin + PCLK_out = pclk_3x; + linebuf_rdclock = pclk_3x; + linebuf_hoffset = hcnt_3x_opt; + pclk_act = pclk_3x; + hcnt_act = hcnt_3x; end - `LINETRIPLE_M3: begin - DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x); - PCLK_out = pclk_out_3x_h5x; - HSYNC_act = HSYNC_3x_h1x; - lines_out = {1'b0, lines_3x_h1x}; - linebuf_rdclock = pclk_3x_h5x; - linebuf_hoffset = hcnt_3x_h5x; - pclk_act = pclk_3x_h5x; - slid_act = line_out_idx_3x_h1x; - hcnt_act = hcnt_3x_h5x; - vcnt_act = vcnt_3x_h1x/2'h3; //divider generated + default: begin + PCLK_out = pclk_3x; + linebuf_rdclock = pclk_3x; + linebuf_hoffset = hcnt_3x; + pclk_act = pclk_3x; + hcnt_act = hcnt_3x; end endcase end default: begin - R_act = 0; - G_act = 0; - B_act = 0; - DATA_enable_act = 0; - PCLK_out = 0; - HSYNC_act = 0; + R_act = R_1x; + G_act = G_1x; + B_act = B_1x; + DATA_enable_act = (h_enable_1x & v_enable_1x); + PCLK_out = pclk_1x; + HSYNC_act = HSYNC_1x; VSYNC_act = VSYNC_1x; - lines_out = 0; + lines_out = lines_1x; linebuf_rdclock = 0; linebuf_hoffset = 0; - pclk_act = 0; - slid_act = 0; - hcnt_act = 0; - vcnt_act = 0; + pclk_act = pclk_1x; + slid_act = {1'b0, vcnt_1x[0]}; + hcnt_act = hcnt_1x; + vcnt_act = vcnt_1x; end endcase end pll_2x pll_linedouble ( - .areset ( (H_LINEMULT != `LINEMULT_DOUBLE) ), + .areset ( (V_MULTMODE != `V_MULTMODE_2X) ), .inclk0 ( PCLK_in ), .c0 ( pclk_2x ), .locked ( pclk_2x_lock ) ); pll_3x pll_linetriple ( - .areset ( ((H_LINEMULT != `LINEMULT_TRIPLE) | H_L3MODE[1]) ), + .areset ( (V_MULTMODE != `V_MULTMODE_3X) ), .inclk0 ( PCLK_in ), .c0 ( pclk_3x ), // sampling clock for 240p: 1280 or 960 samples & MODE0: 1280 output pixels from 1280 input samples (16:9) .c1 ( pclk_4x ), // MODE1: 1280 output pixels from 960 input samples (960 drawn -> 4:3 aspect) .locked ( pclk_3x_lock ) ); -pll_3x_lowfreq pll_linetriple_lowfreq ( +/*pll_3x_lowfreq pll_linetriple_lowfreq ( .areset ( (H_LINEMULT != `LINEMULT_TRIPLE) | ~H_L3MODE[1]), .inclk0 ( PCLK_in ), .c0 ( pclk_3x_h1x ), // sampling clock for 240p: 320 or 256 samples .c1 ( pclk_3x_h4x ), // MODE2: 1280 output pixels from 320 input samples (960 drawn -> 4:3 aspect) .c2 ( pclk_3x_h5x ), // MODE3: 1280 output pixels from 256 input samples (1024 drawn -> 5:4 aspect) .locked ( pclk_3x_lowfreq_lock ) -); +);*/ //TODO: add secondary buffers for interlaced signals with alternative field order linebuf linebuf_rgb ( @@ -377,9 +359,9 @@ begin VSYNC_pp1 <= VSYNC_act; DATA_enable_pp1 <= DATA_enable_act; - R_out <= apply_scanlines(V_SCANLINES, R_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x); - G_out <= apply_scanlines(V_SCANLINES, G_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x); - B_out <= apply_scanlines(V_SCANLINES, B_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x); + R_out <= apply_scanlines(V_SCANLINEMODE, R_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x); + G_out <= apply_scanlines(V_SCANLINEMODE, G_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x); + B_out <= apply_scanlines(V_SCANLINEMODE, B_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x); HSYNC_out <= HSYNC_pp1; VSYNC_out <= VSYNC_pp1; DATA_enable <= DATA_enable_pp1; @@ -394,7 +376,6 @@ begin warn_h_unstable <= 1'b0; warn_pll_lock_lost <= 1'b0; warn_pll_lock_lost_3x <= 1'b0; - warn_pll_lock_lost_3x_lowfreq <= 1'b0; end else begin @@ -403,25 +384,20 @@ begin else if (warn_h_unstable != 0) warn_h_unstable <= warn_h_unstable + 1'b1; - if ((H_LINEMULT == `LINEMULT_DOUBLE) & ~pclk_2x_lock) + if ((V_MULTMODE == `V_MULTMODE_2X) & ~pclk_2x_lock) warn_pll_lock_lost <= 1; else if (warn_pll_lock_lost != 0) warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1; - if ((H_LINEMULT == `LINEMULT_TRIPLE) & ~H_L3MODE[1] & ~pclk_3x_lock) + if ((V_MULTMODE == `V_MULTMODE_3X) & ~pclk_3x_lock) warn_pll_lock_lost_3x <= 1; else if (warn_pll_lock_lost_3x != 0) warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1; - - if ((H_LINEMULT == `LINEMULT_TRIPLE) & H_L3MODE[1] & ~pclk_3x_lowfreq_lock) - warn_pll_lock_lost_3x_lowfreq <= 1; - else if (warn_pll_lock_lost_3x_lowfreq != 0) - warn_pll_lock_lost_3x_lowfreq <= warn_pll_lock_lost_3x_lowfreq + 1'b1; end end assign h_unstable = (warn_h_unstable != 0); -assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), (warn_pll_lock_lost_3x_lowfreq != 0)}; +assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), 1'b0}; //Buffer the inputs using input pixel clock and generate 1x signals always @(posedge pclk_1x or negedge reset_n) @@ -437,17 +413,21 @@ begin FID_prev <= 0; fpga_vsyncgen <= 0; lines_1x <= 0; + H_MULTMODE <= 0; + V_MULTMODE <= 0; H_ACTIVE <= 0; H_BACKPORCH <= 0; - H_LINEMULT <= 0; - H_L3MODE <= 0; H_MASK <= 0; V_ACTIVE <= 0; V_BACKPORCH <= 0; - V_SCANLINES <= 0; - V_SCANLINEID <= 0; - V_SCANLINESTR <= 0; V_MASK <= 0; + V_SCANLINEMODE <= 0; + V_SCANLINEID <= 0; + H_SCANLINESTR <= 0; + H_OPT_STARTOFF <= 0; + H_OPT_SAMPLE_MULT <= 0; + H_OPT_SAMPLE_SEL <= 0; + H_OPT_SCALE <= 0; prev_hs <= 0; prev_vs <= 0; HSYNC_start <= 0; @@ -495,17 +475,24 @@ begin end //Read configuration data from CPU - H_ACTIVE <= h_info[20:10]; // Horizontal active length from by the CPU - 11bits (0...2047) + H_MULTMODE <= h_info[27:26]; // Horizontal scaling mode + V_MULTMODE <= v_info[26:24]; // Line multiply mode + + H_ACTIVE <= h_info[19:9]; // Horizontal active length from by the CPU - 11bits (0...2047) H_BACKPORCH <= h_info[7:0]; // Horizontal backporch length from by the CPU - 8bits (0...255) - H_LINEMULT <= h_info[31:30]; // Horizontal line multiply mode - H_L3MODE <= h_info[29:28]; // Horizontal line triple mode - H_MASK <= h_info[27:22]; + H_MASK <= h_info[25:20]; V_ACTIVE <= v_info[17:7]; // Vertical active length from by the CPU, 11bits (0...2047) V_BACKPORCH <= v_info[5:0]; // Vertical backporch length from by the CPU, 6bits (0...64) - V_SCANLINES <= v_info[31:30]; - V_SCANLINEID <= v_info[29:28]; - V_SCANLINESTR <= ((v_info[27:24]+8'h01)<<4)-1'b1; V_MASK <= v_info[23:18]; + + H_SCANLINESTR <= ((h_info[31:28]+8'h01)<<4)-1'b1; + V_SCANLINEMODE <= v_info[31:30]; + V_SCANLINEID <= v_info[29:28]; + + H_OPT_STARTOFF <= hscale_info[9:0]; + H_OPT_SAMPLE_MULT <= hscale_info[12:10]; + H_OPT_SAMPLE_SEL <= hscale_info[15:13]; + H_OPT_SCALE <= hscale_info[18:16]; end prev_hs <= HSYNC_in; @@ -609,6 +596,8 @@ begin pclk_3x_cnt <= 0; pclk_1x_prev3x <= 0; line_out_idx_3x <= 0; + hcnt_3x_opt <= 0; + hcnt_3x_opt_ctr <= 0; end else begin @@ -616,14 +605,30 @@ begin begin hcnt_3x <= 0; line_out_idx_3x <= 0; + hcnt_3x_opt <= H_OPT_SAMPLE_SEL; + hcnt_3x_opt_ctr <= 0; end else if (hcnt_3x == hmax[~line_idx]) //line_idx_prev? begin hcnt_3x <= 0; line_out_idx_3x <= line_out_idx_3x + 1'b1; + hcnt_3x_opt <= H_OPT_SAMPLE_SEL; + hcnt_3x_opt_ctr <= 0; end else - hcnt_3x <= hcnt_3x + 1'b1; + begin + hcnt_3x <= hcnt_3x + 1'b1; + if (hcnt_3x >= H_OPT_STARTOFF) + begin + if (hcnt_3x_opt_ctr == H_OPT_SCALE-1'b1) + begin + hcnt_3x_opt <= hcnt_3x_opt + H_OPT_SAMPLE_MULT; + hcnt_3x_opt_ctr <= 0; + end + else + hcnt_3x_opt_ctr <= hcnt_3x_opt_ctr + 1'b1; + end + end if (hcnt_3x == 0) vcnt_3x <= vcnt_3x + 1'b1; @@ -633,7 +638,7 @@ begin vcnt_3x <= 0; lines_3x <= vcnt_3x; end - + HSYNC_3x <= ~(hcnt_3x >= HSYNC_start); //TODO: VSYNC_3x h_enable_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE)); @@ -670,115 +675,4 @@ begin end - -//Generate 3x_h1x signals for linetriple M2 and M3 -always @(posedge pclk_3x_h1x or negedge reset_n) -begin - if (!reset_n) - begin - hcnt_3x_h1x <= 0; - vcnt_3x_h1x <= 0; - lines_3x_h1x <= 0; - HSYNC_3x_h1x <= 0; - h_enable_3x_h1x <= 0; - v_enable_3x_h1x <= 0; - pclk_3x_h1x_cnt <= 0; - pclk_1x_prev3x_h1x <= 0; - line_out_idx_3x_h1x <= 0; - end - else - begin - if ((pclk_3x_h1x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x - begin - hcnt_3x_h1x <= 0; - line_out_idx_3x_h1x <= 0; - end - else if (hcnt_3x_h1x == hmax[~line_idx]) //line_idx_prev? - begin - hcnt_3x_h1x <= 0; - line_out_idx_3x_h1x <= line_out_idx_3x_h1x + 1'b1; - end - else - hcnt_3x_h1x <= hcnt_3x_h1x + 1'b1; - - if (hcnt_3x_h1x == 0) - vcnt_3x_h1x <= vcnt_3x_h1x + 1'b1; - - if ((pclk_3x_h1x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x - begin - vcnt_3x_h1x <= 0; - lines_3x_h1x <= vcnt_3x_h1x; - end - - HSYNC_3x_h1x <= ~(hcnt_3x_h1x >= HSYNC_start); - //TODO: VSYNC_3x_h1x - h_enable_3x_h1x <= ((hcnt_3x_h1x >= H_BACKPORCH) & (hcnt_3x_h1x < H_BACKPORCH + H_ACTIVE)); - v_enable_3x_h1x <= ((vcnt_3x_h1x >= (3*V_BACKPORCH)) & (vcnt_3x_h1x < (3*(V_BACKPORCH + V_ACTIVE)))); //multiplier generated!!! - - //read pclk_1x to examine when edges are synced (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg) - if (((pclk_1x_prev3x_h1x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_h1x_cnt == 2'h2)) - pclk_3x_h1x_cnt <= 0; - else - pclk_3x_h1x_cnt <= pclk_3x_h1x_cnt + 1'b1; - - pclk_1x_prev3x_h1x <= pclk_1x; - end -end - - - -//Generate 3x_h4x signals for for linetriple M2 -always @(posedge pclk_3x_h4x or negedge reset_n) -begin - if (!reset_n) - begin - hcnt_3x_h4x <= 0; - hcnt_3x_h4x_ctr <= 0; - h_enable_3x_prev3x_h4x <= 0; - end - else - begin - // Can we sync reliably to h_enable_3x??? - if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h4x == 0)) - hcnt_3x_h4x <= hcnt_3x_h1x - (160/3); - else if (hcnt_3x_h4x_ctr == 2'h0) - hcnt_3x_h4x <= hcnt_3x_h4x + 1'b1; - - if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h4x == 0)) - hcnt_3x_h4x_ctr <= 2'h1; - else if (hcnt_3x_h4x_ctr == 2'h2) - hcnt_3x_h4x_ctr <= 2'h0; - else - hcnt_3x_h4x_ctr <= hcnt_3x_h4x_ctr + 1'b1; - - h_enable_3x_prev3x_h4x <= h_enable_3x_h1x; - end -end - -//Generate 3x_h5x signals for for linetriple M3 -always @(posedge pclk_3x_h5x or negedge reset_n) -begin - if (!reset_n) - begin - hcnt_3x_h5x <= 0; - hcnt_3x_h5x_ctr <= 0; - h_enable_3x_prev3x_h5x <= 0; - end - else - begin - // Can we sync reliably to h_enable_3x??? - if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h5x == 0)) - hcnt_3x_h5x <= hcnt_3x_h1x - (128/4); - else if (hcnt_3x_h5x_ctr == 2'h0) - hcnt_3x_h5x <= hcnt_3x_h5x + 1'b1; - - if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h5x == 0)) - hcnt_3x_h5x_ctr <= 2'h2; - else - hcnt_3x_h5x_ctr <= hcnt_3x_h5x_ctr + 1'b1; - - h_enable_3x_prev3x_h5x <= h_enable_3x_h1x; - end -end - endmodule diff --git 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input, video_format format) status = (status < MODE_CHANGE) ? MODE_CHANGE : status; } - if ((tc.linemult_target != cm.cc.linemult_target) || (tc.l3_mode != cm.cc.l3_mode)) + if ((tc.pm_240p != cm.cc.pm_240p) || + (tc.pm_384p != cm.cc.pm_384p) || + (tc.pm_480i != cm.cc.pm_480i) || + (tc.pm_480p != cm.cc.pm_480p) || + (tc.l3_mode != cm.cc.l3_mode) || + (tc.l4_mode != cm.cc.l4_mode) || + (tc.l5_mode != cm.cc.l5_mode)) status = (status < MODE_CHANGE) ? MODE_CHANGE : status; - if ((tc.s480p_mode != cm.cc.s480p_mode) && (video_modes[cm.id].flags & (MODE_DTV480P|MODE_VGA480P))) + if ((tc.s480p_mode != cm.cc.s480p_mode) && ((video_modes[cm.id].group == GROUP_DTV480P) || (video_modes[cm.id].group == GROUP_VGA480P))) status = (status < MODE_CHANGE) ? MODE_CHANGE : status; if (update_cur_vm) { @@ -278,7 +285,7 @@ status_t get_status(tvp_input_t input, video_format format) tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4)); tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4)); - tvp_writereg(TVP_HSOUTWIDTH, video_modes[cm.id].h_synclen); + tvp_writereg(TVP_HSOUTWIDTH, cm.sample_mult*video_modes[cm.id].h_synclen); status = (status < INFO_CHANGE) ? INFO_CHANGE : status; } @@ -294,12 +301,13 @@ status_t get_status(tvp_input_t input, video_format format) (tc.sl_id != cm.cc.sl_id) || (tc.h_mask != cm.cc.h_mask) || (tc.v_mask != cm.cc.v_mask) || - (tc.edtv_l2x != cm.cc.edtv_l2x) || - (tc.interlace_pt != cm.cc.interlace_pt)) + (tc.l3m3_hmult != cm.cc.l3m3_hmult)) status = (status < INFO_CHANGE) ? INFO_CHANGE : status; - if (tc.sampler_phase != cm.cc.sampler_phase) - tvp_set_hpll_phase(tc.sampler_phase); + if (tc.sampler_phase != cm.cc.sampler_phase) { + cm.sample_sel = tvp_set_hpll_phase(tc.sampler_phase, cm.sample_mult); + status = (status < INFO_CHANGE) ? INFO_CHANGE : status; + } if (tc.sync_vth != cm.cc.sync_vth) tvp_set_sog_thold(tc.sync_vth); @@ -342,54 +350,58 @@ status_t get_status(tvp_input_t input, video_format format) return status; } -// h_info: [31:30] [29:28] [27:22] [21] [20:10] [9:8] [7:0] -// | H_LINEMULT[1:0] | H_L3MODE[1:0] | H_MASK[5:0] | | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] | +// h_info: [31:28] [27:26] [25:20] [19:9] [8] [7:0] +// | H_SCANLINESTR[3:0] | H_MULTMODE[1:0] | H_MASK[5:0] | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] | +// +// v_info: [31:30] [29:28] [27] [26:24] [23:18] [17:7] [6] [5:0] +// | V_SCANLINEMODE[1:0] | V_SCANLINEID | | V_MULTMODE[2:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] | +// +// hscale_info: [31:19] [18:16] [15:13] [12:10] [9:0] +// | | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] // -// v_info: [31] [30] [29:28] [27:24] [23:18] [17:7] [6] [5:0] -// | V_SCANLINES | V_SCANLINEDIR | V_SCANLINEID | V_SCANLINESTR[3:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] | void set_videoinfo() { alt_u8 slid_target; alt_u8 sl_mode_fpga; + alt_u8 h_opt_scale = 0; + alt_u16 h_opt_startoffs = 0; - if (video_modes[cm.id].flags & MODE_L3ENABLE_MASK) { - cm.linemult = 2; + if (cm.fpga_vmultmode == FPGA_V_MULTMODE_3X) slid_target = cm.cc.sl_id ? (cm.cc.sl_type == 1 ? 1 : 2) : 0; - } else if ((video_modes[cm.id].flags & MODE_L2ENABLE) || (cm.cc.edtv_l2x && (video_modes[cm.id].type & VIDEO_EDTV))) { - cm.linemult = 1; + else slid_target = cm.cc.sl_id; - } else { - cm.linemult = 0; - slid_target = cm.cc.sl_id; - } if (cm.cc.sl_mode == 2) { //manual sl_mode_fpga = 1+cm.cc.sl_type; } else if (cm.cc.sl_mode == 1) { //auto if (video_modes[cm.id].flags & MODE_INTERLACED) - sl_mode_fpga = 3; - else if (video_modes[cm.id].flags & (MODE_L2ENABLE|MODE_L3ENABLE_MASK)) - sl_mode_fpga = 1; + sl_mode_fpga = cm.fpga_vmultmode ? FPGA_SCANLINEMODE_ALT : FPGA_SCANLINEMODE_OFF; + else if (cm.fpga_vmultmode) + sl_mode_fpga = FPGA_SCANLINEMODE_H; else - sl_mode_fpga = 0; + sl_mode_fpga = FPGA_SCANLINEMODE_OFF; } else { - sl_mode_fpga = 0; + sl_mode_fpga = FPGA_SCANLINEMODE_OFF; } - if ((cm.cc.interlace_pt) && (video_modes[cm.id].flags & MODE_INTERLACED)) { - cm.linemult = 0; - sl_mode_fpga = 0; + switch (cm.target_lm) { + case MODE_L3_320_COL: + h_opt_scale = 3; + break; + case MODE_L3_256_COL: + h_opt_scale = cm.cc.l3m3_hmult; + break; + default: + break; } - IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.linemult<<30) | (cm.cc.l3_mode<<28) | (cm.cc.h_mask)<<22 | (video_modes[cm.id].h_active<<10) | video_modes[cm.id].h_backporch); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (slid_target<<28) | (cm.cc.sl_str<<24) | (cm.cc.v_mask<<18) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch); + h_opt_startoffs = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2) + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*video_modes[cm.id].h_backporch) / cm.sample_mult); + h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult; + printf("h_opt_startoffs: %u\n", h_opt_startoffs); - if (video_modes[cm.id].type & VIDEO_EDTV) - HDMITX_SetPixelRepetition(cm.cc.edtv_l2x, 0); - else if (video_modes[cm.id].flags & MODE_INTERLACED) - HDMITX_SetPixelRepetition(cm.cc.interlace_pt, (cm.cc.tx_mode==TX_HDMI)); - else - HDMITX_SetPixelRepetition(0, 0); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.cc.sl_str<<28) | (cm.fpga_hmultmode<<26) | (cm.cc.h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*video_modes[cm.id].h_backporch); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (slid_target<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs); } // Configure TVP7002 and scan converter logic based on the video mode @@ -422,7 +434,7 @@ void program_mode() lcd_write_status(); //printf ("Get mode id with %u %u %f\n", totlines, progressive, hz); - cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask, cm.cc.linemult_target, cm.cc.l3_mode, cm.cc.s480p_mode); + cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask); if (cm.id == -1) { printf ("Error: no suitable mode found, defaulting to 240p\n"); @@ -435,8 +447,12 @@ void program_mode() printf("Mode %s selected - hsync width: %upx\n", video_modes[cm.id].name, (unsigned)h_synclen_px); - tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, (alt_u8)h_synclen_px, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold); + tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, (alt_u8)h_synclen_px, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold, cm.sample_mult); set_lpf(cm.cc.video_lpf); + cm.sample_sel = tvp_set_hpll_phase(cm.cc.sampler_phase, cm.sample_mult); + + HDMITX_SetPixelRepetition(cm.hdmitx_pixelrep, (cm.cc.tx_mode==TX_HDMI) ? cm.hdmitx_pixr_ifr : 0); + set_videoinfo(); #ifdef DIY_AUDIO diff --git a/software/sys_controller/ossc/av_controller.h b/software/sys_controller/ossc/av_controller.h index 671a606..abd0090 100644 --- a/software/sys_controller/ossc/av_controller.h +++ b/software/sys_controller/ossc/av_controller.h @@ -23,9 +23,7 @@ #include "avconfig.h" #include "sysconfig.h" -#define HDMITX_MODE_MASK 0x00040000 - -//sys_ctrl bits +// sys_ctrl bits #define SD_SPI_SS_N (1<<7) #define LCD_CS_N (1<<6) #define LCD_RS (1<<5) @@ -33,6 +31,29 @@ #define VIDGEN_OFF (1<<1) #define AV_RESET_N (1<<0) +// HDMI_TX definitions +#define HDMITX_MODE_MASK 0x00040000 + +#define HDMITX_PIXELREP_DISABLE 0 +#define HDMITX_PIXELREP_2X 1 +#define HDMITX_PIXELREP_4X 2 + +// FPGA macros +#define FPGA_V_MULTMODE_1X 0 +#define FPGA_V_MULTMODE_2X 1 +#define FPGA_V_MULTMODE_3X 2 +#define FPGA_V_MULTMODE_4X 3 +#define FPGA_V_MULTMODE_5X 4 + +#define FPGA_H_MULTMODE_FULLWIDTH 0 +#define FPGA_H_MULTMODE_ASPECTFIX 1 +#define FPGA_H_MULTMODE_OPTIMIZED 2 + +#define FPGA_SCANLINEMODE_OFF 0 +#define FPGA_SCANLINEMODE_H 1 +#define FPGA_SCANLINEMODE_V 2 +#define FPGA_SCANLINEMODE_ALT 3 + static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr", "Last used" }; typedef enum { @@ -71,7 +92,13 @@ typedef struct { alt_u8 macrovis; alt_8 id; alt_u8 sync_active; - alt_u8 linemult; + alt_u8 fpga_vmultmode; + alt_u8 fpga_hmultmode; + alt_u8 hdmitx_pixelrep; + alt_u8 hdmitx_pixr_ifr; + alt_u8 sample_mult; + alt_u8 sample_sel; + mode_flags target_lm; avinput_t avinput; // Current configuration avconfig_t cc; diff --git a/software/sys_controller/ossc/avconfig.c b/software/sys_controller/ossc/avconfig.c index a55c2fe..83be8d3 100644 --- a/software/sys_controller/ossc/avconfig.c +++ b/software/sys_controller/ossc/avconfig.c @@ -41,6 +41,12 @@ avconfig_t tc; // Default configuration const avconfig_t tc_default = { + .l3_mode = 1, + .l5_mode = 1, + .pm_240p = 1, + .pm_384p = 1, + .pm_480i = 1, + .l3m3_hmult = 4, .sampler_phase = DEFAULT_SAMPLER_PHASE, .sync_vth = DEFAULT_SYNC_VTH, .linelen_tol = DEFAULT_LINELEN_TOL, diff --git a/software/sys_controller/ossc/avconfig.h b/software/sys_controller/ossc/avconfig.h index 3c2b33e..866f8f1 100644 --- a/software/sys_controller/ossc/avconfig.h +++ b/software/sys_controller/ossc/avconfig.h @@ -35,7 +35,6 @@ #define SL_MODE_MAX 2 #define SL_TYPE_MAX 2 -#define LM_MODE_MAX 1 typedef struct { alt_u8 sl_mode; @@ -44,6 +43,13 @@ typedef struct { alt_u8 sl_id; alt_u8 linemult_target; alt_u8 l3_mode; + alt_u8 l4_mode; + alt_u8 l5_mode; + alt_u8 pm_240p; + alt_u8 pm_384p; + alt_u8 pm_480i; + alt_u8 pm_480p; + alt_u8 l3m3_hmult; alt_u8 h_mask; alt_u8 v_mask; alt_u8 tx_mode; @@ -61,8 +67,6 @@ typedef struct { alt_u8 audio_dw_sampl; alt_u8 audio_swap_lr; #endif - alt_u8 edtv_l2x; - alt_u8 interlace_pt; alt_u8 def_input; color_setup_t col; } __attribute__((packed)) avconfig_t; diff --git a/software/sys_controller/ossc/controls.c b/software/sys_controller/ossc/controls.c index aae9227..4ed5eb9 100644 --- a/software/sys_controller/ossc/controls.c +++ b/software/sys_controller/ossc/controls.c @@ -155,7 +155,7 @@ void parse_control() case RC_SL_TYPE: tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0; break; case RC_SL_MINUS: tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0; break; case RC_SL_PLUS: tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX; break; - case RC_LM_MODE: tc.linemult_target = (tc.linemult_target < LM_MODE_MAX) ? (tc.linemult_target + 1) : 0; break; + //case RC_LM_MODE: tc.linemult_target = (tc.linemult_target < LM_MODE_MAX) ? (tc.linemult_target + 1) : 0; break; case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : 0; break; case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : SAMPLER_PHASE_MAX; break; case RC_PROF_HOTKEY: diff --git a/software/sys_controller/ossc/firmware.h b/software/sys_controller/ossc/firmware.h index e6aa1fe..4fd18d4 100644 --- a/software/sys_controller/ossc/firmware.h +++ b/software/sys_controller/ossc/firmware.h @@ -24,7 +24,7 @@ #include "sysconfig.h" #define FW_VER_MAJOR 0 -#define FW_VER_MINOR 75 +#define FW_VER_MINOR 76 #ifdef DIY_AUDIO #define FW_SUFFIX1 "a" diff --git a/software/sys_controller/ossc/menu.c b/software/sys_controller/ossc/menu.c index 6547c91..b378898 100644 --- a/software/sys_controller/ossc/menu.c +++ b/software/sys_controller/ossc/menu.c @@ -49,6 +49,12 @@ static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" }; static const char *s480p_mode_desc[] = { LNG("Auto","ｼﾞﾄﾞｳ"), "DTV 480p", "VESA 640x480@60" }; static const char *sync_lpf_desc[] = { LNG("Off","ｵﾌ"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)") }; static const char *l3_mode_desc[] = { LNG("Generic 16:9","ﾊﾝﾖｳ 16:9"), LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") }; +static const char *l4_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") }; +//static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x", "Line5x" }; +static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x" }; +static const char *pm_384p_desc[] = { "Passthru", "Line2x" }; +static const char *pm_480i_desc[] = { "Passthru", "Line2x" }; +static const char *pm_480p_desc[] = { "Passthru", "Line2x" }; static const char *tx_mode_desc[] = { "HDMI", "DVI" }; static const char *sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｼﾞﾄﾞｳ"), LNG("Manual","ｼｭﾄﾞｳ") }; static const char *sl_type_desc[] = { LNG("Horizontal","ｽｲﾍｲ"), LNG("Vertical","ｽｲﾁｮｸ"), LNG("Alternating","ｺｳｺﾞ") }; @@ -101,10 +107,14 @@ MENU(menu_sync, P99_PROTECT({ \ })) MENU(menu_output, P99_PROTECT({ \ - { LNG("240p/288p lineX3","240p/288pﾗｲﾝX3"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.linemult_target, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, - { LNG("Linetriple mode","ﾗｲﾝﾄﾘﾌﾟﾙﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } }, - { LNG("480p/576p lineX2","480p/576pﾗｲﾝX2"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.edtv_l2x, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, - { LNG("480i/576i passtr","480i/576iﾊﾟｽｽﾙｰ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.interlace_pt, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, + { "240p/288p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } }, + { "384p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } }, + { "480i/576i proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } }, + { "480p/576p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } }, + { "Line3x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } }, + { "Line4x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l4_mode_desc) } } }, + { "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } }, + { "256x240 L3_Hmult", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.l3m3_hmult, OPT_NOWRAP, 1, 5, value_disp } } }, { LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } }, { LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } }, })) diff --git a/software/sys_controller/tvp7002/tvp7002.c b/software/sys_controller/tvp7002/tvp7002.c index ad57bc7..01b3451 100644 --- a/software/sys_controller/tvp7002/tvp7002.c +++ b/software/sys_controller/tvp7002/tvp7002.c @@ -163,7 +163,7 @@ void tvp_init() tvp_sel_csc(&csc_coeffs[0]); // Set default phase - tvp_set_hpll_phase(0x10); + tvp_set_hpll_phase(0x10, 1); // Set min LPF tvp_set_lpf(0); @@ -298,11 +298,17 @@ void tvp_set_sync_lpf(alt_u8 val) printf("Sync LPF value set to 0x%x\n", (3-val)); } -void tvp_set_hpll_phase(alt_u8 val) +alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult) { + alt_u8 sample_sel; alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0x07; + + sample_sel = (val*sample_mult)/32; + val = val*sample_mult % 32; tvp_writereg(TVP_HPLLPHASE, (val<<3)|status); - printf("Phase value set to 0x%x\n", val); + printf("Phase selection: %u/%u (FPGA), %u/32 (TVP)\n", sample_sel+1, sample_mult, val+1); + + return sample_sel; } void tvp_set_sog_thold(alt_u8 val) @@ -337,7 +343,7 @@ void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen) } } -void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold) +void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sample_mult) { // Clamp position and ALC tvp_set_clamp_position(type, h_syncinlen); @@ -367,7 +373,7 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, tvp_set_hpllcoast(pre_coast, post_coast); // Hsync output width - tvp_writereg(TVP_HSOUTWIDTH, video_modes[modeid].h_synclen); + tvp_writereg(TVP_HSOUTWIDTH, sample_mult*video_modes[modeid].h_synclen); } void tvp_source_sel(tvp_input_t input, video_format fmt) diff --git a/software/sys_controller/tvp7002/tvp7002.h b/software/sys_controller/tvp7002/tvp7002.h index 083f451..6a784ca 100644 --- a/software/sys_controller/tvp7002/tvp7002.h +++ b/software/sys_controller/tvp7002/tvp7002.h @@ -94,13 +94,13 @@ void tvp_set_lpf(alt_u8 val); void tvp_set_sync_lpf(alt_u8 val); -void tvp_set_hpll_phase(alt_u8 val); +alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult); void tvp_set_sog_thold(alt_u8 val); void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen); -void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold); +void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sample_mult); void tvp_source_sel(tvp_input_t input, video_format fmt); diff --git a/software/sys_controller/tvp7002/video_modes.c b/software/sys_controller/tvp7002/video_modes.c index 6d95ac9..ffced2c 100644 --- a/software/sys_controller/tvp7002/video_modes.c +++ b/software/sys_controller/tvp7002/video_modes.c @@ -20,43 +20,131 @@ #include #include #include "system.h" +#include "av_controller.h" #include "video_modes.h" #define LINECNT_MAX_TOLERANCE 30 +extern avmode_t cm; + const mode_data_t video_modes_default[] = VIDEO_MODES_DEF; mode_data_t video_modes[VIDEO_MODES_CNT]; /* TODO: rewrite, check hz etc. */ -alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask, alt_u8 linemult_target, alt_u8 l3_mode, alt_u8 s480p_mode) +alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask) { alt_8 i; alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t); video_type mode_type; + mode_flags valid_lm[] = { MODE_PT, MODE_L2, (MODE_L3_GEN_16_9< GROUP_VGA480P) { + printf("WARNING: Corrupted mode (id %d)\n", i); + continue; } - if ((typemask & mode_type) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) { - if (linemult_target && (video_modes[i].flags & MODE_L3ENABLE_MASK) && ((video_modes[i].flags & MODE_L3ENABLE_MASK) == (1<>gk#4 zxU;6+@86~E)@HZgYbbsDNG7OYp&@4$K**=!`=0$>b1&;?^SuLLD6o?Iojx7MS% zc?twIo>XwbHDRg%hTLfhgnSAHTC%kU14BL?@NVlvL1D=0Msb}9TCB!_gnSPC)@yGT zKs>49rZZ7d%NPpcxxota*bzyU`&O`S_?9fO`I+a7CnbX?61enA0BDOgt`{x2ht6@Y zxFu|6vfv6}_FAtLXmNF0h=?uDEb=1BKGSgtqx@{nm?50s_MInDzxDXUnBG806aCWG>k8(U+&- zhOtT-Wl*fLyXh?a5=i02cwo0oaU@d=hmF^q{OF8182S*@m{8);sMBj` C!c`Ff delta 701 zcmYjOQAm?f6z2T@=C;&1CQaD7|0)}!q7_k;MQhB5NC-)NDQZy&!ODvEAQeJRLPn9b z`*0tGARi)D2zro98mqLoD9d3+poKmJ86*i-`qF>T-9u0RcfbFf?|kPw1A`R2@4mR{Trymf3e5lBWEqdOKAshILh!q22HU(4-D6J z3PViq0t;VUJ6Go7U2h0k80}tl3C|I`E}n~;wg%%xmca2l&4#99ebTfQEi`$)l7m+~#g zJn-2`yNHzlB;>Ce*hvjCUJLzdN?860KnKl}*&y5|e{vgxHJ8$p$p}=^L1a1xGfv`C zd*BPDAWt5GlJ00qz+#nhX35rLP|$+G hal default - Jan 7, 2017 11:01:41 PM - 1483822901087 + Jan 23, 2017 12:33:30 AM + 1485124410921 ./ settings.bsp ../../sys.sopcinfo @@ -910,20 +910,20 @@ 40960 memory - - i2c_opencores_1 - 0x00821000 - 0x0082101F - 32 - - timer_0 - 0x00821020 - 0x0082103F + 0x00821000 - 0x0082101F 32 timer epcq_controller_0_avl_csr + 0x00821020 - 0x0082103F + 32 + + + + i2c_opencores_1 0x00821040 - 0x0082105F 32 @@ -935,38 +935,44 @@ - pio_4 + pio_5 0x00821080 - 0x0082108F 16 - pio_3 + pio_4 0x00821090 - 0x0082109F 16 - pio_2 + pio_3 0x008210A0 - 0x008210AF 16 - pio_1 + pio_2 0x008210B0 - 0x008210BF 16 - pio_0 + pio_1 0x008210C0 - 0x008210CF 16 + + pio_0 + 0x008210D0 - 0x008210DF + 16 + + jtag_uart_0 - 0x008210D0 - 0x008210D7 + 0x008210E0 - 0x008210E7 8 printable diff --git a/software/sys_controller_bsp/system.h b/software/sys_controller_bsp/system.h index 83d75d2..6330ba0 100644 --- a/software/sys_controller_bsp/system.h +++ b/software/sys_controller_bsp/system.h @@ -4,7 +4,7 @@ * Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys' * SOPC Builder design path: ../../sys.sopcinfo * - * Generated: Sat Dec 31 11:45:57 EET 2016 + * Generated: Sat Jan 21 12:40:58 EET 2017 */ /* @@ -175,19 +175,19 @@ #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_STDERR "/dev/jtag_uart_0" -#define ALT_STDERR_BASE 0x8210d0 +#define ALT_STDERR_BASE 0x8210e0 #define ALT_STDERR_DEV jtag_uart_0 #define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_PRESENT #define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN "/dev/jtag_uart_0" -#define ALT_STDIN_BASE 0x8210d0 +#define ALT_STDIN_BASE 0x8210e0 #define ALT_STDIN_DEV jtag_uart_0 #define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_PRESENT #define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDOUT "/dev/jtag_uart_0" -#define ALT_STDOUT_BASE 0x8210d0 +#define ALT_STDOUT_BASE 0x8210e0 #define ALT_STDOUT_DEV jtag_uart_0 #define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_PRESENT @@ -201,7 +201,7 @@ */ #define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod -#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821040 +#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821020 #define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS64" #define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2 #define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0 @@ -265,7 +265,7 @@ */ #define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores -#define I2C_OPENCORES_1_BASE 0x821000 +#define I2C_OPENCORES_1_BASE 0x821040 #define I2C_OPENCORES_1_IRQ 4 #define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0 #define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1" @@ -279,7 +279,7 @@ */ #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart -#define JTAG_UART_0_BASE 0x8210d0 +#define JTAG_UART_0_BASE 0x8210e0 #define JTAG_UART_0_IRQ 1 #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_0_NAME "/dev/jtag_uart_0" @@ -326,7 +326,7 @@ */ #define ALT_MODULE_CLASS_pio_0 altera_avalon_pio -#define PIO_0_BASE 0x8210c0 +#define PIO_0_BASE 0x8210d0 #define PIO_0_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_0_CAPTURE 0 @@ -353,7 +353,7 @@ */ #define ALT_MODULE_CLASS_pio_1 altera_avalon_pio -#define PIO_1_BASE 0x8210b0 +#define PIO_1_BASE 0x8210c0 #define PIO_1_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_1_CAPTURE 0 @@ -380,7 +380,7 @@ */ #define ALT_MODULE_CLASS_pio_2 altera_avalon_pio -#define PIO_2_BASE 0x8210a0 +#define PIO_2_BASE 0x8210b0 #define PIO_2_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_2_CAPTURE 0 @@ -407,7 +407,7 @@ */ #define ALT_MODULE_CLASS_pio_3 altera_avalon_pio -#define PIO_3_BASE 0x821090 +#define PIO_3_BASE 0x8210a0 #define PIO_3_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_3_CAPTURE 0 @@ -434,7 +434,7 @@ */ #define ALT_MODULE_CLASS_pio_4 altera_avalon_pio -#define PIO_4_BASE 0x821080 +#define PIO_4_BASE 0x821090 #define PIO_4_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_4_CAPTURE 0 @@ -455,6 +455,33 @@ #define PIO_4_TYPE "altera_avalon_pio" +/* + * pio_5 configuration + * + */ + +#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio +#define PIO_5_BASE 0x821080 +#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_5_CAPTURE 0 +#define PIO_5_DATA_WIDTH 32 +#define PIO_5_DO_TEST_BENCH_WIRING 0 +#define PIO_5_DRIVEN_SIM_VALUE 0 +#define PIO_5_EDGE_TYPE "NONE" +#define PIO_5_FREQ 27000000 +#define PIO_5_HAS_IN 0 +#define PIO_5_HAS_OUT 1 +#define PIO_5_HAS_TRI 0 +#define PIO_5_IRQ -1 +#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_5_IRQ_TYPE "NONE" +#define PIO_5_NAME "/dev/pio_5" +#define PIO_5_RESET_VALUE 0 +#define PIO_5_SPAN 16 +#define PIO_5_TYPE "altera_avalon_pio" + + /* * timer_0 configuration * @@ -462,7 +489,7 @@ #define ALT_MODULE_CLASS_timer_0 altera_avalon_timer #define TIMER_0_ALWAYS_RUN 0 -#define TIMER_0_BASE 0x821020 +#define TIMER_0_BASE 0x821000 #define TIMER_0_COUNTER_SIZE 32 #define TIMER_0_FIXED_PERIOD 0 #define TIMER_0_FREQ 27000000 diff --git a/sys.qsys b/sys.qsys index 11a2019..bcab066 100644 --- a/sys.qsys +++ b/sys.qsys @@ -29,7 +29,7 @@ { datum baseAddress { - value = "8523840"; + value = "8523808"; type = "String"; } } @@ -69,7 +69,7 @@ { datum baseAddress { - value = "8523776"; + value = "8523840"; type = "String"; } } @@ -85,7 +85,7 @@ { datum baseAddress { - value = "8523984"; + value = "8524000"; type = "String"; } } @@ -157,7 +157,7 @@ { datum baseAddress { - value = "8523968"; + value = "8523984"; type = "String"; } } @@ -173,7 +173,7 @@ { datum baseAddress { - value = "8523952"; + value = "8523968"; type = "String"; } } @@ -189,7 +189,7 @@ { datum baseAddress { - value = "8523936"; + value = "8523952"; type = "String"; } } @@ -205,7 +205,7 @@ { datum baseAddress { - value = "8523920"; + value = "8523936"; type = "String"; } } @@ -218,6 +218,22 @@ } } element pio_4.s1 + { + datum baseAddress + { + value = "8523920"; + type = "String"; + } + } + element pio_5 + { + datum _sortIndex + { + value = "16"; + type = "int"; + } + } + element pio_5.s1 { datum baseAddress { @@ -237,7 +253,7 @@ { datum baseAddress { - value = "8523808"; + value = "8523776"; type = "String"; } } @@ -298,6 +314,11 @@ internal="pio_4.external_connection" type="conduit" dir="end" /> + @@ -387,7 +408,7 @@ - ]]> + ]]> @@ -659,6 +680,20 @@ + + + + + + + + + + + + + + @@ -677,7 +712,7 @@ start="nios2_qsys_0.data_master" end="jtag_uart_0.avalon_jtag_slave"> - + - + - + - + - + - + - + - + - + + + + + + + + - + java.lang.Integer - 1483178399 + 1485124053 false true false @@ -378,6 +378,12 @@ parameters are a RESULT of the module parameters. --> clk timer_0.clk + + false + pio_5 + clk + pio_5.clk + false onchip_memory2_0 @@ -5432,7 +5438,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -6103,7 +6109,7 @@ parameters are a RESULT of the module parameters. --> jtag_uart_0 avalon_jtag_slave jtag_uart_0.avalon_jtag_slave - 8523984 + 8524000 8 @@ -6119,7 +6125,7 @@ parameters are a RESULT of the module parameters. --> i2c_opencores_1 avalon_slave_0 i2c_opencores_1.avalon_slave_0 - 8523776 + 8523840 32 @@ -6127,7 +6133,7 @@ parameters are a RESULT of the module parameters. --> epcq_controller_0 avl_csr epcq_controller_0.avl_csr - 8523840 + 8523808 32 @@ -6159,7 +6165,7 @@ parameters are a RESULT of the module parameters. --> pio_0 s1 pio_0.s1 - 8523968 + 8523984 16 @@ -6167,7 +6173,7 @@ parameters are a RESULT of the module parameters. --> pio_1 s1 pio_1.s1 - 8523952 + 8523968 16 @@ -6175,7 +6181,7 @@ parameters are a RESULT of the module parameters. --> pio_2 s1 pio_2.s1 - 8523936 + 8523952 16 @@ -6183,7 +6189,7 @@ parameters are a RESULT of the module parameters. --> pio_3 s1 pio_3.s1 - 8523920 + 8523936 16 @@ -6191,7 +6197,7 @@ parameters are a RESULT of the module parameters. --> pio_4 s1 pio_4.s1 - 8523904 + 8523920 16 @@ -6199,9 +6205,17 @@ parameters are a RESULT of the module parameters. --> timer_0 s1 timer_0.s1 - 8523808 + 8523776 32 + + false + pio_5 + s1 + pio_5.s1 + 8523904 + 16 + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 32 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 27000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + embeddedsw.dts.group + gpio + + + embeddedsw.dts.name + pio + + + embeddedsw.dts.params.altr,gpio-bank-width + 32 + + + embeddedsw.dts.params.resetvalue + 0 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 32 + false + true + true + true + + + long + 27000000 + false + true + false + true + CLOCK_RATE + clk + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 27000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 32 + export + + + java.math.BigInteger - 0x008210d0 + 0x008210e0 false true true @@ -13131,7 +13919,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821000 + 0x00821040 false true true @@ -13182,7 +13970,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821040 + 0x00821020 false true true @@ -13386,7 +14174,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210c0 + 0x008210d0 false true true @@ -13437,7 +14225,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210b0 + 0x008210c0 false true true @@ -13488,7 +14276,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210a0 + 0x008210b0 false true true @@ -13539,7 +14327,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821090 + 0x008210a0 false true true @@ -13590,7 +14378,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821080 + 0x00821090 false true true @@ -13641,7 +14429,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821020 + 0x00821000 false true true @@ -13676,6 +14464,57 @@ parameters are a RESULT of the module parameters. --> timer_0 s1 + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00821080 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_qsys_0 + data_master + pio_5 + s1 + timer_0 clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk + pio_5 + clk + timer_0 reset + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk_reset + pio_5 + reset + 16.1 - 12 + 13 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -14859,7 +15752,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 12 + 13 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -14867,7 +15760,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 13 + 14 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -14891,7 +15784,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 7 + 8 conduit_end com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -14987,7 +15880,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 5 + 6 altera_avalon_pio com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule @@ -15003,7 +15896,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 15 + 16 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -15011,7 +15904,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 12 + 13 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -15035,7 +15928,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 12 + 13 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection