From 4f36278cb73a64441efbf91315e6186d24a94d6b Mon Sep 17 00:00:00 2001 From: marqs Date: Thu, 18 May 2017 23:35:43 +0300 Subject: [PATCH] Sync processing rewritten and some issues fixed * add 480i/576i line3x/4x * clean up RTL and SDC * update AVI infoframe properly * add HDMI IT content option --- ossc.qsf | 3 + ossc.sdc | 73 +- rtl/ossc.v | 106 +- rtl/scanconverter.v | 965 ++++---- rtl/videogen.v | 102 +- software/sys_controller/it6613/HDMI_TX.c | 22 +- software/sys_controller/it6613/HDMI_TX.h | 2 +- software/sys_controller/it6613/it6613_drv.c | 23 +- software/sys_controller/it6613/it6613_drv.h | 2 +- .../mem_init/sys_onchip_memory2_0.hex | 2086 ++++++++--------- software/sys_controller/ossc/av_controller.c | 95 +- software/sys_controller/ossc/avconfig.c | 1 + software/sys_controller/ossc/avconfig.h | 1 + software/sys_controller/ossc/controls.c | 6 +- software/sys_controller/ossc/firmware.h | 2 +- software/sys_controller/ossc/menu.c | 10 +- software/sys_controller/tvp7002/tvp7002.c | 5 +- software/sys_controller/tvp7002/tvp7002.h | 2 +- software/sys_controller/tvp7002/video_modes.c | 43 +- software/sys_controller/tvp7002/video_modes.h | 64 +- software/sys_controller_bsp/libhal_bsp.a | Bin 104226 -> 104226 bytes software/sys_controller_bsp/settings.bsp | 24 +- software/sys_controller_bsp/system.h | 57 +- sys.qsys | 88 +- sys.sopcinfo | 1025 +++++++- 25 files changed, 2814 insertions(+), 1993 deletions(-) diff --git a/ossc.qsf b/ossc.qsf index 9c635b4..2dc74b4 100644 --- a/ossc.qsf +++ b/ossc.qsf @@ -235,4 +235,7 @@ set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp +set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/ossc.sdc b/ossc.sdc index f5bb37a..d6a7281 100644 --- a/ossc.sdc +++ b/ossc.sdc @@ -10,16 +10,13 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*} ### Scanconverter clock constraints ### create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in] -create_clock -period 27MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add -create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add -create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add -create_clock -period 27MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add +create_clock -period 27MHz -name pclk_sdtv [get_ports PCLK_in] -add #derive_pll_clocks -create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]} -create_generated_clock -master_clock pclk_sdtv_L3 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]} -create_generated_clock -master_clock pclk_sdtv_L4 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]} -create_generated_clock -master_clock pclk_sdtv_L5 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]} +create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]} +create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]} +create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]} +create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]} derive_clock_uncertainty @@ -29,14 +26,8 @@ set TVP_dmax 1.5 set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}] set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs -set_input_delay -clock pclk_sdtv_L2 -min $TVP_dmin $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L2 -max $TVP_dmax $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L3 -min $TVP_dmin $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L3 -max $TVP_dmax $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L4 -min $TVP_dmin $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L4 -max $TVP_dmax $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L5 -min $TVP_dmin $critinputs -add_delay -set_input_delay -clock pclk_sdtv_L5 -max $TVP_dmax $critinputs -add_delay +set_input_delay -clock pclk_sdtv -min $TVP_dmin $critinputs -add_delay +set_input_delay -clock pclk_sdtv -max $TVP_dmax $critinputs -add_delay # output delay constraints (TODO: add vsync) set IT_Tsu 1.0 @@ -58,36 +49,36 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi] ### CPU/scanconverter clock relations ### -# Set pixel clocks as exclusive clocks -set_clock_groups -exclusive \ --group {pclk_hdtv} \ --group {pclk_sdtv_L2 pclk_2x} \ --group {pclk_sdtv_L3 pclk_3x} \ --group {pclk_sdtv_L4 pclk_4x} \ --group {pclk_sdtv_L5 pclk_5x} +# Set hdtv pixel clock group as exclusive +set_clock_groups -exclusive -group {pclk_hdtv} # Treat CPU clock asynchronous to pixel clocks set_clock_groups -asynchronous -group {clk27} -# Filter out impossible output mux combinations -set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out* scanconverter:scanconverter_inst|G_out* scanconverter:scanconverter_inst|B_out* scanconverter:scanconverter_inst|HSYNC_out* scanconverter:scanconverter_inst|VSYNC_out* scanconverter:scanconverter_inst|DE_out* scanconverter:scanconverter_inst|*_pp1* scanconverter:scanconverter_inst|*_pp2*}] -set clkmuxnodes [get_pins {scanconverter_inst|linebuf_*|altsyncram_*|auto_generated|ram_*|portbaddr*}] -set_false_path -from [get_clocks {pclk_sdtv_L2 pclk_sdtv_L3 pclk_sdtv_L4 pclk_sdtv_L5}] -through $clkmuxregs - -# Ignore paths from registers which are updated only at the end of vsync -set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}] - -# Ignore paths from registers which are updated only at the end of hsync -set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|HSYNC_start*}] - -# Ignore paths to registers which do not drive critical logic -set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}] - # Ignore following clock transfers -set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv_L2] -set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv_L3}] -set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv_L4}] -set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv_L5}] +set_false_path -from [get_clocks pclk_2x] -to [get_clocks {pclk_sdtv pclk_3x pclk_4x pclk_5x}] +set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv pclk_2x pclk_4x pclk_5x}] +set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_5x}] +set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_4x}] + +# Ignore paths which would result from pclk_act switchover during postprocess chain +set pclk_act_regs [get_cells {scanconverter:scanconverter_inst|R_out* \ + scanconverter:scanconverter_inst|G_out* \ + scanconverter:scanconverter_inst|B_out* \ + scanconverter:scanconverter_inst|HSYNC_out* \ + scanconverter:scanconverter_inst|VSYNC_out* \ + scanconverter:scanconverter_inst|DE_out* \ + scanconverter:scanconverter_inst|*_pp1* \ + scanconverter:scanconverter_inst|*_pp2* \ + scanconverter:scanconverter_inst|*_pp3*}] +set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs +set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*] + +# Ignore paths from registers which are updated only at leading edge of vsync +set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}] + +# Ignore paths from registers which are updated only at leading edge of hsync +#set_false_path -from [get_cells {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}] ### JTAG Signal Constraints ### diff --git a/rtl/ossc.v b/rtl/ossc.v index 00d65da..d5870cb 100644 --- a/rtl/ossc.v +++ b/rtl/ossc.v @@ -1,5 +1,5 @@ // -// Copyright (C) 2015-2016 Markus Hiienkari +// Copyright (C) 2015-2017 Markus Hiienkari // // This file is part of Open Source Scan Converter project. // @@ -19,6 +19,7 @@ //`define DEBUG `define VIDEOGEN +`define CPU_RESET_WIDTH 27 //1us module ossc ( input clk27, @@ -57,8 +58,8 @@ wire [7:0] sys_ctrl; wire h_unstable; wire [1:0] pclk_lock; wire [1:0] pll_lock_lost; -wire [31:0] h_info, h_info2, v_info; -wire [10:0] lines_out, tvp_lines; +wire [31:0] h_info, h_info2, v_info, extra_info; +wire [10:0] vmax, vmax_tvp; wire [1:0] fpga_vsyncgen; wire [15:0] ir_code; @@ -77,8 +78,8 @@ wire PCLK_out_videogen; wire DE_out_videogen; -reg [3:0] cpu_reset_ctr; -reg cpu_reset_n = 1'b1; +reg [7:0] cpu_reset_ctr = 0; +reg cpu_reset_n = 1'b0; reg [7:0] R_in_L, G_in_L, B_in_L; reg HSYNC_in_L, VSYNC_in_L, FID_in_L; @@ -89,63 +90,54 @@ reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_T // Latch inputs from TVP7002 (synchronized to PCLK_in) always @(posedge PCLK_in or negedge reset_n) begin - if (!reset_n) - begin - R_in_L <= 8'h00; - G_in_L <= 8'h00; - B_in_L <= 8'h00; - HSYNC_in_L <= 1'b0; - VSYNC_in_L <= 1'b0; - FID_in_L <= 1'b0; - end - else - begin - R_in_L <= R_in; - G_in_L <= G_in; - B_in_L <= B_in; - HSYNC_in_L <= HSYNC_in; - VSYNC_in_L <= VSYNC_in; - FID_in_L <= FID_in; - end + if (!reset_n) begin + R_in_L <= 8'h00; + G_in_L <= 8'h00; + B_in_L <= 8'h00; + HSYNC_in_L <= 1'b0; + VSYNC_in_L <= 1'b0; + FID_in_L <= 1'b0; + end else begin + R_in_L <= R_in; + G_in_L <= G_in; + B_in_L <= B_in; + HSYNC_in_L <= HSYNC_in; + VSYNC_in_L <= VSYNC_in; + FID_in_L <= FID_in; + end end // Insert synchronizers to async inputs (synchronize to CPU clock) always @(posedge clk27 or negedge cpu_reset_n) begin - if (!cpu_reset_n) - begin - btn_L <= 2'b00; - btn_LL <= 2'b00; - ir_rx_L <= 1'b0; - ir_rx_LL <= 1'b0; - HDMI_TX_INT_N_L <= 1'b0; - HDMI_TX_INT_N_LL <= 1'b0; - HDMI_TX_MODE_L <= 1'b0; - HDMI_TX_MODE_LL <= 1'b0; - end - else - begin - btn_L <= btn; - btn_LL <= btn_L; - ir_rx_L <= ir_rx; - ir_rx_LL <= ir_rx_L; - HDMI_TX_INT_N_L <= HDMI_TX_INT_N; - HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L; - HDMI_TX_MODE_L <= HDMI_TX_MODE; - HDMI_TX_MODE_LL <= HDMI_TX_MODE_L; - end + if (!cpu_reset_n) begin + btn_L <= 2'b00; + btn_LL <= 2'b00; + ir_rx_L <= 1'b0; + ir_rx_LL <= 1'b0; + HDMI_TX_INT_N_L <= 1'b0; + HDMI_TX_INT_N_LL <= 1'b0; + HDMI_TX_MODE_L <= 1'b0; + HDMI_TX_MODE_LL <= 1'b0; + end else begin + btn_L <= btn; + btn_LL <= btn_L; + ir_rx_L <= ir_rx; + ir_rx_LL <= ir_rx_L; + HDMI_TX_INT_N_L <= HDMI_TX_INT_N; + HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L; + HDMI_TX_MODE_L <= HDMI_TX_MODE; + HDMI_TX_MODE_LL <= HDMI_TX_MODE_L; + end end // CPU reset pulse generation (is this really necessary?) always @(posedge clk27) begin - if (cpu_reset_ctr == 4'b1000) + if (cpu_reset_ctr == `CPU_RESET_WIDTH) cpu_reset_n <= 1'b1; else - begin - cpu_reset_ctr <= cpu_reset_ctr + 1'b1; - cpu_reset_n <= 1'b0; - end + cpu_reset_ctr <= cpu_reset_ctr + 1'b1; end assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB @@ -197,10 +189,11 @@ sys sys_inst( .i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]), .pio_0_sys_ctrl_out_export (sys_ctrl), .pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}), - .pio_2_horizontal_info_out_export (h_info), - .pio_3_vertical_info_out_export (v_info), - .pio_4_linecount_in_export ({VSYNC_out, 2'b00, tvp_lines, fpga_vsyncgen, 5'h0, lines_out}), - .pio_5_horizontal_info2_out_export (h_info2), + .pio_2_status_in_export ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 5'h0, vmax}), + .pio_3_h_info_out_export (h_info), + .pio_4_h_info2_out_export (h_info2), + .pio_5_v_info_out_export (v_info), + .pio_6_extra_info_out_export (extra_info) ); scanconverter scanconverter_inst ( @@ -216,6 +209,7 @@ scanconverter scanconverter_inst ( .h_info (h_info), .h_info2 (h_info2), .v_info (v_info), + .extra_info (extra_info), .R_out (R_out), .G_out (G_out), .B_out (B_out), @@ -227,8 +221,8 @@ scanconverter scanconverter_inst ( .fpga_vsyncgen (fpga_vsyncgen), .pclk_lock (pclk_lock), .pll_lock_lost (pll_lock_lost), - .lines_out (lines_out), - .tvp_lines (tvp_lines) + .vmax (vmax), + .vmax_tvp (vmax_tvp) ); ir_rcv ir0 ( diff --git a/rtl/scanconverter.v b/rtl/scanconverter.v index 050df46..3cb2549 100644 --- a/rtl/scanconverter.v +++ b/rtl/scanconverter.v @@ -1,5 +1,5 @@ // -// Copyright (C) 2015-2016 Markus Hiienkari +// Copyright (C) 2015-2017 Markus Hiienkari // // This file is part of Open Source Scan Converter project. // @@ -22,6 +22,9 @@ `define HI 1'b1 `define LO 1'b0 +`define HSYNC_POL `LO +`define VSYNC_POL `LO + `define V_MULTMODE_1X 3'd0 `define V_MULTMODE_2X 3'd1 `define V_MULTMODE_3X 3'd2 @@ -48,11 +51,8 @@ `define DBLFRAME_THOLD 5 `define FALSE_FIELD (fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] & (FID_in == `FID_ODD)) -`define VSYNC_LEADING_EDGE ((prev_vs == `HI) & (VSYNC_in == `LO)) -`define VSYNC_TRAILING_EDGE ((prev_vs == `LO) & (VSYNC_in == `HI)) - -`define HSYNC_LEADING_EDGE ((prev_hs == `HI) & (HSYNC_in == `LO)) -`define HSYNC_TRAILING_EDGE ((prev_hs == `LO) & (HSYNC_in == `HI)) +`define HSYNC_LEADING_EDGE ((HSYNC_in_L == `HI) & (HSYNC_in == `LO)) +`define VSYNC_LEADING_EDGE ((VSYNC_in_L == `HI) & (VSYNC_in == `LO)) module scanconverter ( input reset_n, @@ -67,6 +67,7 @@ module scanconverter ( input [31:0] h_info, input [31:0] h_info2, input [31:0] v_info, + input [31:0] extra_info, output reg [7:0] R_out, output reg [7:0] G_out, output reg [7:0] B_out, @@ -78,90 +79,85 @@ module scanconverter ( output reg [1:0] fpga_vsyncgen, output [1:0] pclk_lock, output [1:0] pll_lock_lost, - output [10:0] lines_out, - output reg [10:0] tvp_lines + output reg [10:0] vmax, + output reg [10:0] vmax_tvp ); +//clock-related signals +wire pclk_act; wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x; +wire pclk_2x_lock, pclk_3x_lock; wire linebuf_rdclock; -wire pclk_act; -wire [2:0] line_id_act; -wire [2:0] col_id_act; +//RGB signals®isters: 8 bits per component -> 16.7M colors +wire [7:0] R_act, G_act, B_act; +wire [7:0] R_lbuf, G_lbuf, B_lbuf; +reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_1x, G_1x, B_1x, R_pp3, G_pp3, B_pp3; -wire pclk_2x_lock, pclk_3x_lock; +//H+V syncs + data enable signals®isters +wire HSYNC_act, VSYNC_act, DE_act; +reg HSYNC_in_L, VSYNC_in_L; +reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2, HSYNC_pp3; +reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x, VSYNC_pp1, VSYNC_pp2, VSYNC_pp3; +reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_pp1, DE_pp2, DE_pp3, DE_3x_prev4x; -wire HSYNC_act, VSYNC_act; -reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2; -reg VSYNC_1x, VSYNC_2x, VSYNC_pp1, VSYNC_pp2; - -reg [11:0] HSYNC_start; - -reg FID_1x, FID_prev; - -wire DE_act; -reg DE_pp1, DE_pp2; +//registers indicating line/frame change and field type +reg FID_cur, FID_prev, FID_1x; +reg frame_change, line_change; +//H+V counters wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written wire [11:0] hcnt_act; reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_opt, hcnt_3x_opt, hcnt_4x_opt, hcnt_5x_opt, hcnt_5x_hscomp; - reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr; - wire [10:0] vcnt_act; -reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, vcnt_4x, vcnt_5x, vcnt_2x_ref, vcnt_3x_ref, vcnt_4x_ref, vcnt_5x_ref, lines_1x, lines_2x, lines_4x, lines_5x; //max. 2047 -reg [9:0] vcnt_3x, lines_3x; //max. 1023 +reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047 -reg DE_3x_prev4x; - -reg pclk_1x_prev3x; -reg [1:0] pclk_3x_cnt; - -reg pclk_1x_prev4x; -reg [1:0] pclk_4x_cnt; - -reg pclk_1x_prev5x; -reg pclk_1x_prevprev5x; -reg [2:0] pclk_5x_cnt; - -// Data enable -reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x; - -reg prev_hs, prev_vs; +//other counters +wire [2:0] line_id_act, col_id_act; +reg [2:0] line_id_pp1, line_id_pp2, col_id_pp1, col_id_pp2; reg [11:0] hmax[0:1]; reg line_idx; reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x; reg [2:0] line_out_idx_5x; - reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x; +reg mask_enable_pp1, mask_enable_pp2, mask_enable_pp3; +//helper registers for sampling at synchronized clock edges +reg pclk_1x_prev3x; +reg [1:0] pclk_3x_cnt; +reg pclk_1x_prev4x; +reg [1:0] pclk_4x_cnt; +reg pclk_1x_prev5x; +reg pclk_1x_prevprev5x; +reg [2:0] pclk_5x_cnt; + +//configuration registers reg [10:0] H_ACTIVE; //max. 2047 reg [8:0] H_BACKPORCH; //max. 511 reg [10:0] V_ACTIVE; //max. 2047 reg [5:0] V_BACKPORCH; //max. 63 +reg [7:0] H_SYNCLEN; +reg [2:0] V_SYNCLEN; reg [1:0] V_SCANLINEMODE; reg [4:0] V_SCANLINEID; -reg [7:0] H_SCANLINESTR; reg [5:0] V_MASK; reg [2:0] V_MULTMODE; reg [1:0] H_MULTMODE; reg [9:0] H_MASK; -reg [3:0] H_MASK_BR; reg [9:0] H_OPT_STARTOFF; reg [2:0] H_OPT_SCALE; reg [2:0] H_OPT_SAMPLE_MULT; reg [2:0] H_OPT_SAMPLE_SEL; reg [9:0] H_L5BORDER; +reg [3:0] X_MASK_BR; +reg [7:0] X_SCANLINESTR; -// clk27 related registers -reg VSYNC_in_L, VSYNC_in_LL, VSYNC_in_LLL; +//clk27 related registers +reg VSYNC_in_cc_L, VSYNC_in_cc_LL, VSYNC_in_cc_LLL; reg [21:0] clk27_ctr; // min. 6.5Hz reg [2:0] dbl_frame_ctr; -//8 bits per component -> 16.7M colors -reg [7:0] R_1x, G_1x, B_1x, R_2x, G_2x, B_2x, R_3x, G_3x, B_3x, R_4x, G_4x, B_4x, R_5x, G_5x, B_5x, R_pp1, G_pp1, B_pp1; -wire [7:0] R_lbuf, G_lbuf, B_lbuf; -wire [7:0] R_act, G_act, B_act; assign pclk_1x = PCLK_in; assign PCLK_out = pclk_act; @@ -193,14 +189,8 @@ function [7:0] apply_mask; input enable; input [7:0] data; input [3:0] brightness; - input [11:0] hoffset; - input [11:0] hstart; - input [11:0] hend; - input [10:0] voffset; - input [10:0] vstart; - input [10:0] vend; begin - if (enable & ((hoffset < hstart) | (hoffset >= hend) | (voffset < vstart) | (voffset >= vend))) + if (enable) apply_mask = {brightness, 4'h0}; else apply_mask = data; @@ -220,96 +210,86 @@ case (V_MULTMODE) R_act = R_1x; G_act = G_1x; B_act = B_1x; - DE_act = DE_1x; HSYNC_act = HSYNC_1x; VSYNC_act = VSYNC_1x; - lines_out = lines_1x; - linebuf_rdclock = 0; - linebuf_hoffset = 0; - pclk_act = pclk_1x; + DE_act = DE_1x; line_id_act = {2'b00, vcnt_1x[0]}; - col_id_act = {2'b00, hcnt_1x[0]}; hcnt_act = hcnt_1x; vcnt_act = vcnt_1x; + pclk_act = pclk_1x; + linebuf_rdclock = 0; + linebuf_hoffset = 0; + col_id_act = {2'b00, hcnt_1x[0]}; end `V_MULTMODE_2X: begin - R_act = R_2x; - G_act = G_2x; - B_act = B_2x; - DE_act = DE_2x; + R_act = R_lbuf; + G_act = G_lbuf; + B_act = B_lbuf; HSYNC_act = HSYNC_2x; VSYNC_act = VSYNC_2x; - lines_out = lines_2x; + DE_act = DE_2x; + line_id_act = {1'b0, line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x}; + hcnt_act = hcnt_2x; + vcnt_act = vcnt_2x; linebuf_rdclock = pclk_2x; case (H_MULTMODE) default: begin //`H_MULTMODE_FULLWIDTH - linebuf_hoffset = hcnt_2x; pclk_act = pclk_2x; + linebuf_hoffset = hcnt_2x; col_id_act = {2'b00, hcnt_2x[0]}; end `H_MULTMODE_OPTIMIZED: begin - linebuf_hoffset = hcnt_2x_opt; pclk_act = pclk_1x; + linebuf_hoffset = hcnt_2x_opt; col_id_act = {2'b00, hcnt_2x[1]};; end endcase - line_id_act = {1'b0, line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x}; - hcnt_act = hcnt_2x; - vcnt_act = vcnt_2x_ref; end `V_MULTMODE_3X: begin + R_act = R_lbuf; + G_act = G_lbuf; + B_act = B_lbuf; HSYNC_act = HSYNC_3x; - VSYNC_act = VSYNC_1x; + VSYNC_act = VSYNC_3x; DE_act = DE_3x; - lines_out = {1'b0, lines_3x}; line_id_act = {1'b0, line_out_idx_3x}; - vcnt_act = vcnt_3x_ref; + vcnt_act = vcnt_3x; case (H_MULTMODE) default: begin //`H_MULTMODE_FULLWIDTH - R_act = R_3x; - G_act = G_3x; - B_act = B_3x; + pclk_act = pclk_3x; linebuf_rdclock = pclk_3x; linebuf_hoffset = hcnt_3x; - pclk_act = pclk_3x; hcnt_act = hcnt_3x; col_id_act = {2'b00, hcnt_3x[0]}; end `H_MULTMODE_ASPECTFIX: begin - R_act = R_4x; - G_act = G_4x; - B_act = B_4x; + pclk_act = pclk_4x; linebuf_rdclock = pclk_4x; linebuf_hoffset = hcnt_4x_aspfix; - pclk_act = pclk_4x; hcnt_act = hcnt_4x_aspfix; col_id_act = {2'b00, hcnt_4x[0]}; end `H_MULTMODE_OPTIMIZED: begin - R_act = R_3x; - G_act = G_3x; - B_act = B_3x; + pclk_act = pclk_3x; linebuf_rdclock = pclk_3x; linebuf_hoffset = hcnt_3x_opt; - pclk_act = pclk_3x; hcnt_act = hcnt_3x; col_id_act = hcnt_3x_opt_ctr; end endcase end `V_MULTMODE_4X: begin - R_act = R_4x; - G_act = G_4x; - B_act = B_4x; + R_act = R_lbuf; + G_act = G_lbuf; + B_act = B_lbuf; HSYNC_act = HSYNC_4x; - VSYNC_act = VSYNC_1x; + VSYNC_act = VSYNC_4x; DE_act = DE_4x; - lines_out = lines_4x; line_id_act = {1'b0, line_out_idx_4x}; - vcnt_act = vcnt_4x_ref; - linebuf_rdclock = pclk_4x; - pclk_act = pclk_4x; hcnt_act = hcnt_4x; + vcnt_act = vcnt_4x; + pclk_act = pclk_4x; + linebuf_rdclock = pclk_4x; case (H_MULTMODE) default: begin //`H_MULTMODE_FULLWIDTH linebuf_hoffset = hcnt_4x; @@ -322,18 +302,17 @@ case (V_MULTMODE) endcase end `V_MULTMODE_5X: begin - R_act = R_5x; - G_act = G_5x; - B_act = B_5x; + R_act = R_lbuf; + G_act = G_lbuf; + B_act = B_lbuf; HSYNC_act = HSYNC_5x; - VSYNC_act = VSYNC_1x; + VSYNC_act = VSYNC_5x; DE_act = DE_5x; - lines_out = lines_5x; line_id_act = {2'b00, line_out_idx_5x}; - vcnt_act = vcnt_5x_ref; - linebuf_rdclock = pclk_5x; - pclk_act = pclk_5x; hcnt_act = hcnt_5x; + vcnt_act = vcnt_5x; + pclk_act = pclk_5x; + linebuf_rdclock = pclk_5x; case (H_MULTMODE) default: begin //`H_MULTMODE_FULLWIDTH linebuf_hoffset = hcnt_5x_hscomp; @@ -366,77 +345,71 @@ pll_3x pll_linetriple ( //TODO: add secondary buffers for interlaced signals with alternative field order linebuf linebuf_rgb ( - .data ( {R_1x, G_1x, B_1x} ), - .rdaddress ( linebuf_hoffset + (~line_idx << 10) ), + .data({R_in_L, G_in_L, B_in_L}), + .rdaddress ( linebuf_hoffset + (~line_idx << 11) ), .rdclock ( linebuf_rdclock ), - .wraddress ( hcnt_1x + (line_idx << 10) ), + .wraddress(hcnt_1x + (line_idx << 11)), .wrclock ( pclk_1x ), .wren ( 1'b1 ), .q ( {R_lbuf, G_lbuf, B_lbuf} ) ); //Postprocess pipeline -always @(posedge pclk_act or negedge reset_n) +// h_cnt, v_cnt, line_id, col_id: 0 +// HSYNC, VSYNC, DE: 1 +// RGB: 2 +always @(posedge pclk_act) begin - if (!reset_n) - begin - R_pp1 <= 8'h00; - G_pp1 <= 8'h00; - B_pp1 <= 8'h00; - HSYNC_pp1 <= 1'b0; - VSYNC_pp1 <= 1'b0; - DE_pp1 <= 1'b0; - R_out <= 8'h00; - G_out <= 8'h00; - B_out <= 8'h00; - HSYNC_out <= 1'b0; - VSYNC_out <= 1'b0; - DE_out <= 1'b0; - end - else - begin - R_pp1 <= apply_scanlines(V_SCANLINEMODE, R_act, H_SCANLINESTR, V_SCANLINEID, line_id_act, col_id_act, FID_1x); - G_pp1 <= apply_scanlines(V_SCANLINEMODE, G_act, H_SCANLINESTR, V_SCANLINEID, line_id_act, col_id_act, FID_1x); - B_pp1 <= apply_scanlines(V_SCANLINEMODE, B_act, H_SCANLINESTR, V_SCANLINEID, line_id_act, col_id_act, FID_1x); - HSYNC_pp1 <= HSYNC_act; - VSYNC_pp1 <= VSYNC_act; - DE_pp1 <= DE_act; - - R_out <= apply_mask(1, R_pp1, H_MASK_BR, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK); - G_out <= apply_mask(1, G_pp1, H_MASK_BR, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK); - B_out <= apply_mask(1, B_pp1, H_MASK_BR, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK); - HSYNC_out <= HSYNC_pp1; - VSYNC_out <= VSYNC_pp1; - DE_out <= DE_pp1; - end + line_id_pp1 <= line_id_act; + col_id_pp1 <= col_id_act; + mask_enable_pp1 <= ((hcnt_act < H_SYNCLEN+H_BACKPORCH+H_MASK) | (hcnt_act >= H_SYNCLEN+H_BACKPORCH+H_ACTIVE-H_MASK) | (vcnt_act < V_SYNCLEN+V_BACKPORCH+V_MASK) | (vcnt_act >= V_SYNCLEN+V_BACKPORCH+V_ACTIVE-V_MASK)); + + HSYNC_pp2 <= HSYNC_act; + VSYNC_pp2 <= VSYNC_act; + DE_pp2 <= DE_act; + line_id_pp2 <= line_id_pp1; + col_id_pp2 <= col_id_pp1; + mask_enable_pp2 <= mask_enable_pp1; + + R_pp3 <= apply_scanlines(V_SCANLINEMODE, R_act, X_SCANLINESTR, V_SCANLINEID, line_id_pp2, col_id_pp2, FID_1x); + G_pp3 <= apply_scanlines(V_SCANLINEMODE, G_act, X_SCANLINESTR, V_SCANLINEID, line_id_pp2, col_id_pp2, FID_1x); + B_pp3 <= apply_scanlines(V_SCANLINEMODE, B_act, X_SCANLINESTR, V_SCANLINEID, line_id_pp2, col_id_pp2, FID_1x); + HSYNC_pp3 <= HSYNC_pp2; + VSYNC_pp3 <= VSYNC_pp2; + DE_pp3 <= DE_pp2; + mask_enable_pp3 <= mask_enable_pp2; + + R_out <= apply_mask(mask_enable_pp3, R_pp3, X_MASK_BR); + G_out <= apply_mask(mask_enable_pp3, G_pp3, X_MASK_BR); + B_out <= apply_mask(mask_enable_pp3, B_pp3, X_MASK_BR); + HSYNC_out <= HSYNC_pp3; + VSYNC_out <= VSYNC_pp3; + DE_out <= DE_pp3; end //Generate a warning signal from horizontal instability or PLL sync loss always @(posedge pclk_1x or negedge reset_n) begin - if (!reset_n) - begin - warn_h_unstable <= 1'b0; - warn_pll_lock_lost <= 1'b0; - warn_pll_lock_lost_3x <= 1'b0; - end - else - begin - if (hmax[0] != hmax[1]) - warn_h_unstable <= 1; - else if (warn_h_unstable != 0) - warn_h_unstable <= warn_h_unstable + 1'b1; - - if (((V_MULTMODE == `V_MULTMODE_2X) | (V_MULTMODE == `V_MULTMODE_5X)) & ~pclk_2x_lock) - warn_pll_lock_lost <= 1; - else if (warn_pll_lock_lost != 0) - warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1; - - if (((V_MULTMODE == `V_MULTMODE_3X) | (V_MULTMODE == `V_MULTMODE_4X)) & ~pclk_3x_lock) - warn_pll_lock_lost_3x <= 1; - else if (warn_pll_lock_lost_3x != 0) - warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1; - end + if (!reset_n) begin + warn_h_unstable <= 1'b0; + warn_pll_lock_lost <= 1'b0; + warn_pll_lock_lost_3x <= 1'b0; + end else begin + if (hmax[0] != hmax[1]) + warn_h_unstable <= 1; + else if (warn_h_unstable != 0) + warn_h_unstable <= warn_h_unstable + 1'b1; + + if (((V_MULTMODE == `V_MULTMODE_2X) | (V_MULTMODE == `V_MULTMODE_5X)) & ~pclk_2x_lock) + warn_pll_lock_lost <= 1; + else if (warn_pll_lock_lost != 0) + warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1; + + if (((V_MULTMODE == `V_MULTMODE_3X) | (V_MULTMODE == `V_MULTMODE_4X)) & ~pclk_3x_lock) + warn_pll_lock_lost_3x <= 1; + else if (warn_pll_lock_lost_3x != 0) + warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1; + end end assign h_unstable = (warn_h_unstable != 0); @@ -447,13 +420,13 @@ always @(posedge clk27 or negedge reset_n) begin if (!reset_n) begin fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= 1'b0; - VSYNC_in_L <= 1'b0; - VSYNC_in_LL <= 1'b0; - VSYNC_in_LLL <= 1'b0; + VSYNC_in_cc_L <= 1'b0; + VSYNC_in_cc_LL <= 1'b0; + VSYNC_in_cc_LLL <= 1'b0; clk27_ctr <= 0; dbl_frame_ctr <= 0; end else begin - if ((VSYNC_in_LLL == `HI) && (VSYNC_in_LL == `LO)) begin + if ((VSYNC_in_cc_LLL == `HI) && (VSYNC_in_cc_LL == `LO)) begin // If calculated refresh rate is between 22Hz and 44Hz, assume TVP7002 has skipped a vsync if ((clk27_ctr >= (27000000/44)) && (clk27_ctr <= (27000000/22)) && (dbl_frame_ctr < `DBLFRAME_THOLD)) dbl_frame_ctr <= dbl_frame_ctr + 1'b1; @@ -470,331 +443,244 @@ begin else if (dbl_frame_ctr == `DBLFRAME_THOLD) fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= 1'b1; - VSYNC_in_L <= VSYNC_in; - VSYNC_in_LL <= VSYNC_in_L; - VSYNC_in_LLL <= VSYNC_in_LL; + VSYNC_in_cc_L <= VSYNC_in; + VSYNC_in_cc_LL <= VSYNC_in_cc_L; + VSYNC_in_cc_LLL <= VSYNC_in_cc_LL; end end //Buffer the inputs using input pixel clock and generate 1x signals always @(posedge pclk_1x or negedge reset_n) begin - if (!reset_n) - begin + if (!reset_n) begin + hcnt_1x <= 0; + vcnt_1x <= 0; + vcnt_tvp <= 0; + hmax[0] <= 0; + hmax[1] <= 0; + vmax <= 0; + vmax_tvp <= 0; + line_idx <= 0; + FID_cur <= 1'b0; + line_change <= 1'b0; + frame_change <= 1'b0; + fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= 1'b0; + H_MULTMODE <= 0; + V_MULTMODE <= 0; + end else begin + if (`HSYNC_LEADING_EDGE) begin hcnt_1x <= 0; - hmax[0] <= 0; - hmax[1] <= 0; - line_idx <= 0; - vcnt_1x <= 0; - vcnt_1x_tvp <= 0; - FID_prev <= 0; - fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= 1'b0; - lines_1x <= 0; - H_MULTMODE <= 0; - V_MULTMODE <= 0; - H_ACTIVE <= 0; - H_BACKPORCH <= 0; - H_MASK <= 0; - V_ACTIVE <= 0; - V_BACKPORCH <= 0; - V_MASK <= 0; - V_SCANLINEMODE <= 0; - V_SCANLINEID <= 0; - H_SCANLINESTR <= 0; - H_OPT_STARTOFF <= 0; - H_OPT_SAMPLE_MULT <= 0; - H_OPT_SAMPLE_SEL <= 0; - H_OPT_SCALE <= 0; - H_L5BORDER <= 0; - H_MASK_BR <= 0; - prev_hs <= 0; - prev_vs <= 0; - HSYNC_start <= 0; - R_1x <= 8'h00; - G_1x <= 8'h00; - B_1x <= 8'h00; - HSYNC_1x <= 0; - VSYNC_1x <= 0; - DE_1x <= 0; - FID_1x <= 0; + hmax[line_idx] <= hcnt_1x; + line_idx <= line_idx ^ 1'b1; + line_change <= 1'b1; + end else begin + hcnt_1x <= hcnt_1x + 1'b1; + line_change <= 1'b0; end - else - begin - if (`HSYNC_TRAILING_EDGE) - begin - hcnt_1x <= 0; - hmax[line_idx] <= hcnt_1x; - line_idx <= line_idx ^ 1'b1; - vcnt_1x <= vcnt_1x + 1'b1; - vcnt_1x_tvp <= vcnt_1x_tvp + 1'b1; - FID_1x <= fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] ? 1'b0 : (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] ? (vcnt_1x > (V_BACKPORCH + V_ACTIVE)) : FID_in); - end - else - begin - hcnt_1x <= hcnt_1x + 1'b1; - end - if (`VSYNC_TRAILING_EDGE) //should be checked at every pclk_1x? - begin - vcnt_1x_tvp <= 0; - tvp_lines <= vcnt_1x_tvp; - FID_prev <= FID_in; - - // detect non-interlaced signal with odd-odd field signaling (TVP7002 detects it as interlaced with analog sync inputs). - // FID is updated at leading edge of VSYNC, so trailing edge has the status of current field. - if (FID_in == FID_prev) - fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= `FALSE; - else if (FID_in == `FID_ODD) // TVP7002 falsely indicates field change with (vcnt < active_lines) - fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_1x_tvp < `MIN_VALID_LINES); + if (`HSYNC_LEADING_EDGE) begin + if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or even field (interlace) start + FID_cur <= 1'b0; + vcnt_1x <= 0; + frame_change <= 1'b1; + vmax <= vcnt_1x; + vcnt_tvp <= 0; + vmax_tvp <= vcnt_tvp; + end else begin + vcnt_1x <= vcnt_1x + 1'b1; + vcnt_tvp <= vcnt_tvp + 1'b1; + end + end else if (`VSYNC_LEADING_EDGE) begin // odd field (interlace) start + if (!`FALSE_FIELD) begin + FID_cur <= 1'b1; + vcnt_1x <= -1; + frame_change <= 1'b1; + vmax <= vcnt_1x; + end + vcnt_tvp <= 0; + vmax_tvp <= vcnt_tvp; + end else if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT]) && (vcnt_tvp == (vmax_tvp>>1)) && (hcnt_1x == (hmax[~line_idx]>>1))) begin //VSM=1 + FID_cur <= 1'b1; + vcnt_1x <= -1; + frame_change <= 1'b1; + vmax <= vcnt_1x; + end else + frame_change <= 1'b0; - if (!(`FALSE_FIELD)) - begin - vcnt_1x <= 0; - lines_1x <= vcnt_1x; - end - - //Read configuration data from CPU - H_MULTMODE <= h_info[31:30]; // Horizontal scaling mode - V_MULTMODE <= v_info[26:24]; // Line multiply mode + if (`VSYNC_LEADING_EDGE) begin + FID_prev <= FID_in; + // detect non-interlaced signal with odd-odd field signaling (TVP7002 detects it as interlaced with analog sync inputs). + // FID is updated at leading edge of VSYNC + if (FID_in == FID_prev) + fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= `FALSE; + else if (FID_in == `FID_ODD) // TVP7002 falsely indicates field change with (vcnt < active_lines) + fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_tvp < `MIN_VALID_LINES); + end - H_ACTIVE <= h_info[19:9]; // Horizontal active length from by the CPU - 11bits (0...2047) - H_BACKPORCH <= h_info[7:0]; // Horizontal backporch length from by the CPU - 8bits (0...255) - H_MASK <= h_info[29:20]; - V_ACTIVE <= v_info[17:7]; // Vertical active length from by the CPU, 11bits (0...2047) - V_BACKPORCH <= v_info[5:0]; // Vertical backporch length from by the CPU, 6bits (0...64) - V_MASK <= v_info[23:18]; - - H_SCANLINESTR <= ((h_info2[22:19]+8'h01)<<4)-1'b1; - V_SCANLINEMODE <= v_info[31:30]; - case (v_info[26:24]) - `V_MULTMODE_1X, `V_MULTMODE_2X: V_SCANLINEID <= (5'b00001 << v_info[28]); - `V_MULTMODE_3X: V_SCANLINEID <= (5'b00001 << {v_info[28], 1'b0}); - `V_MULTMODE_4X: V_SCANLINEID <= (5'b00011 << {v_info[28], 1'b0}); - `V_MULTMODE_5X: V_SCANLINEID <= (5'b00011 << {2{v_info[28]}}); - endcase - - H_OPT_STARTOFF <= h_info2[9:0]; - H_OPT_SAMPLE_MULT <= h_info2[12:10]; - H_OPT_SAMPLE_SEL <= h_info2[15:13]; - H_OPT_SCALE <= h_info2[18:16]; - H_MASK_BR <= h_info2[26:23]; - H_L5BORDER <= h_info2[27] ? (1920-h_info[19:9])/2 : (1600-h_info[19:9])/2; - end - - prev_hs <= HSYNC_in; - prev_vs <= VSYNC_in; + if (frame_change) begin + //Read configuration data from CPU + H_MULTMODE <= h_info[31:30]; // Horizontal scaling mode + V_MULTMODE <= v_info[31:29]; // Line multiply mode - // record start position of HSYNC - if (`HSYNC_LEADING_EDGE) - HSYNC_start <= hcnt_1x; + H_SYNCLEN <= h_info[27:20]; + H_BACKPORCH <= h_info[19:11]; // Horizontal backporch length from by the CPU - 9bits (0...511) + H_ACTIVE <= h_info[10:0]; // Horizontal active length from by the CPU - 11bits (0...2047) - R_1x <= R_in; - G_1x <= G_in; - B_1x <= B_in; - HSYNC_1x <= HSYNC_in; + V_SYNCLEN <= v_info[19:17]; + V_BACKPORCH <= v_info[16:11]; // Vertical backporch length from by the CPU, 6bits (0...64) + V_ACTIVE <= v_info[10:0]; // Vertical active length from by the CPU, 11bits (0...2047) - // Ignore possible invalid vsyncs generated by TVP7002 - if (vcnt_1x > V_ACTIVE) - VSYNC_1x <= VSYNC_in; + H_MASK <= h_info2[28:19]; + V_MASK <= v_info[25:20]; - DE_1x <= ((hcnt_1x >= H_BACKPORCH) & (hcnt_1x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_1x >= V_BACKPORCH) & (vcnt_1x < V_BACKPORCH + V_ACTIVE)); + V_SCANLINEMODE <= v_info[28:27]; + case (v_info[31:29]) + `V_MULTMODE_1X, `V_MULTMODE_2X: V_SCANLINEID <= (5'b00001 << v_info[26]); + `V_MULTMODE_3X: V_SCANLINEID <= (5'b00001 << {v_info[26], 1'b0}); + `V_MULTMODE_4X: V_SCANLINEID <= (5'b00011 << {v_info[26], 1'b0}); + `V_MULTMODE_5X: V_SCANLINEID <= (5'b00011 << {2{v_info[26]}}); + endcase + + H_L5BORDER <= h_info[29] ? (11'd1920-h_info[10:0])/2 : (11'd1600-h_info[10:0])/2; + + H_OPT_SCALE <= h_info2[18:16]; + H_OPT_SAMPLE_SEL <= h_info2[15:13]; + H_OPT_SAMPLE_MULT <= h_info2[12:10]; + H_OPT_STARTOFF <= h_info2[9:0]; + + X_MASK_BR <= extra_info[7:4]; + X_SCANLINESTR <= ((extra_info[3:0]+8'h01)<<4)-1'b1; end + + R_in_L <= R_in; + G_in_L <= G_in; + B_in_L <= B_in; + HSYNC_in_L <= HSYNC_in; + VSYNC_in_L <= VSYNC_in; + + // Add one delay stage to match linebuf delay + R_in_LL <= R_in_L; + G_in_LL <= G_in_L; + B_in_LL <= B_in_L; + + R_1x <= R_in_LL; + G_1x <= G_in_LL; + B_1x <= B_in_LL; + HSYNC_1x <= (hcnt_1x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL; + if (FID_cur == `FID_EVEN) + VSYNC_1x <= (vcnt_1x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL; + else + VSYNC_1x <= (((vcnt_1x+1'b1) < V_SYNCLEN) | ((vcnt_1x+1'b1 == V_SYNCLEN) & (hcnt_1x <= (hmax[~line_idx]>>1)))) ? `VSYNC_POL : ~`VSYNC_POL; + DE_1x <= ((hcnt_1x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_1x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_1x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_1x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE)); + FID_1x <= FID_cur; + end end //Generate 2x signals for linedouble always @(posedge pclk_2x or negedge reset_n) begin - if (!reset_n) - begin + if (!reset_n) begin + hcnt_2x <= 0; + vcnt_2x <= 0; + line_out_idx_2x <= 0; + end else begin + if ((pclk_1x == 1'b0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x hcnt_2x <= 0; - vcnt_2x <= 0; - vcnt_2x_ref <= 0; - lines_2x <= 0; - R_2x <= 8'h00; - G_2x <= 8'h00; - B_2x <= 8'h00; - HSYNC_2x <= 0; - VSYNC_2x <= 0; - DE_2x <= 0; - line_out_idx_2x <= 0; - hcnt_2x_opt <= 0; + hcnt_2x_opt <= H_OPT_SAMPLE_SEL; hcnt_2x_opt_ctr <= 0; - end - else - begin - if ((pclk_1x == 1'b0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x - begin - hcnt_2x <= 0; - line_out_idx_2x <= 0; - hcnt_2x_opt <= H_OPT_SAMPLE_SEL; + line_out_idx_2x <= 0; + if (frame_change) + vcnt_2x <= -1; + else if (line_change & (FID_cur == `FID_EVEN)) + vcnt_2x <= vcnt_2x + 1'b1; + end else if (hcnt_2x == hmax[~line_idx]) begin + hcnt_2x <= 0; + line_out_idx_2x <= line_out_idx_2x + 1'b1; + hcnt_2x_opt <= H_OPT_SAMPLE_SEL; + hcnt_2x_opt_ctr <= 0; + if (FID_cur == `FID_ODD) + vcnt_2x <= vcnt_2x + 1'b1; + end else begin + hcnt_2x <= hcnt_2x + 1'b1; + if (hcnt_2x >= H_OPT_STARTOFF) begin + if (hcnt_2x_opt_ctr == H_OPT_SCALE-1'b1) begin + hcnt_2x_opt <= hcnt_2x_opt + H_OPT_SAMPLE_MULT; hcnt_2x_opt_ctr <= 0; - end - else if (hcnt_2x == hmax[~line_idx]) - begin - hcnt_2x <= 0; - line_out_idx_2x <= line_out_idx_2x + 1'b1; - hcnt_2x_opt <= H_OPT_SAMPLE_SEL; - hcnt_2x_opt_ctr <= 0; - end - else - begin - hcnt_2x <= hcnt_2x + 1'b1; - if (hcnt_2x >= H_OPT_STARTOFF) - begin - if (hcnt_2x_opt_ctr == H_OPT_SCALE-1'b1) - begin - hcnt_2x_opt <= hcnt_2x_opt + H_OPT_SAMPLE_MULT; - hcnt_2x_opt_ctr <= 0; - end - else - hcnt_2x_opt_ctr <= hcnt_2x_opt_ctr + 1'b1; - end - end - - if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x - begin - vcnt_2x <= 0; - vcnt_2x_ref <= 0; - if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b0) - lines_2x <= vcnt_2x; - end - else if (hcnt_2x == hmax[~line_idx]) - begin - if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1) & (vcnt_2x == lines_1x-1)) - begin - vcnt_2x <= 0; - vcnt_2x_ref <= 0; - lines_2x <= lines_1x; - end - else - begin - vcnt_2x <= vcnt_2x + 1'b1; - if (line_out_idx_2x == 1) - vcnt_2x_ref <= vcnt_2x_ref + 1'b1; - end - end - - if (pclk_1x == 1'b0) - begin - if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1) - VSYNC_2x <= (vcnt_2x >= lines_1x - `VSYNCGEN_LEN) ? 1'b0 : 1'b1; - else if (vcnt_2x_ref > V_ACTIVE) - VSYNC_2x <= VSYNC_in; - end - - - R_2x <= R_lbuf; - G_2x <= G_lbuf; - B_2x <= B_lbuf; - HSYNC_2x <= ~(hcnt_2x >= HSYNC_start); - DE_2x <= ((hcnt_2x >= H_BACKPORCH) & (hcnt_2x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_2x >= (V_BACKPORCH<<1)) & (vcnt_2x < ((V_BACKPORCH + V_ACTIVE)<<1))); + end else + hcnt_2x_opt_ctr <= hcnt_2x_opt_ctr + 1'b1; + end end + + HSYNC_2x <= (hcnt_2x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL; + VSYNC_2x <= (vcnt_2x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL; + DE_2x <= ((hcnt_2x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_2x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_2x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_2x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE)); + end end always @(posedge pclk_3x or negedge reset_n) begin - if (!reset_n) - begin + if (!reset_n) begin + hcnt_3x <= 0; + vcnt_3x <= 0; + line_out_idx_3x <= 0; + end else begin + if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x + if (!(frame_change & (FID_cur == `FID_ODD))) begin + hcnt_3x <= 0; + hcnt_3x_opt <= H_OPT_SAMPLE_SEL; + hcnt_3x_opt_ctr <= 0; + line_out_idx_3x <= 0; + end + if (frame_change) + vcnt_3x <= -11'b1-FID_cur; + else if (line_change) + vcnt_3x <= vcnt_3x + 1'b1; + end else if (hcnt_3x == hmax[~line_idx]) begin hcnt_3x <= 0; - vcnt_3x <= 0; - vcnt_3x_ref <= 0; - lines_3x <= 0; - R_3x <= 8'h00; - G_3x <= 8'h00; - B_3x <= 8'h00; - HSYNC_3x <= 0; - DE_3x <= 0; - pclk_3x_cnt <= 0; - pclk_1x_prev3x <= 0; - line_out_idx_3x <= 0; - hcnt_3x_opt <= 0; + line_out_idx_3x <= line_out_idx_3x + 1'b1; + hcnt_3x_opt <= H_OPT_SAMPLE_SEL; hcnt_3x_opt_ctr <= 0; + end else begin + hcnt_3x <= hcnt_3x + 1'b1; + if (hcnt_3x >= H_OPT_STARTOFF) begin + if (hcnt_3x_opt_ctr == H_OPT_SCALE-1'b1) begin + hcnt_3x_opt <= hcnt_3x_opt + H_OPT_SAMPLE_MULT; + hcnt_3x_opt_ctr <= 0; + end else + hcnt_3x_opt_ctr <= hcnt_3x_opt_ctr + 1'b1; + end end - else - begin - if ((pclk_3x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x - begin - hcnt_3x <= 0; - line_out_idx_3x <= 0; - hcnt_3x_opt <= H_OPT_SAMPLE_SEL; - hcnt_3x_opt_ctr <= 0; - end - else if (hcnt_3x == hmax[~line_idx]) - begin - hcnt_3x <= 0; - line_out_idx_3x <= line_out_idx_3x + 1'b1; - hcnt_3x_opt <= H_OPT_SAMPLE_SEL; - hcnt_3x_opt_ctr <= 0; - end - else - begin - hcnt_3x <= hcnt_3x + 1'b1; - if (hcnt_3x >= H_OPT_STARTOFF) - begin - if (hcnt_3x_opt_ctr == H_OPT_SCALE-1'b1) - begin - hcnt_3x_opt <= hcnt_3x_opt + H_OPT_SAMPLE_MULT; - hcnt_3x_opt_ctr <= 0; - end - else - hcnt_3x_opt_ctr <= hcnt_3x_opt_ctr + 1'b1; - end - end - if ((pclk_3x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x - begin - vcnt_3x <= 0; - vcnt_3x_ref <= 0; - lines_3x <= vcnt_3x; - end - else if (hcnt_3x == hmax[~line_idx]) - begin - vcnt_3x <= vcnt_3x + 1'b1; - if (line_out_idx_3x == 2) - vcnt_3x_ref <= vcnt_3x_ref + 1'b1; - end - //track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg) if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2)) pclk_3x_cnt <= 0; else pclk_3x_cnt <= pclk_3x_cnt + 1'b1; - + pclk_1x_prev3x <= pclk_1x; - - R_3x <= R_lbuf; - G_3x <= G_lbuf; - B_3x <= B_lbuf; - HSYNC_3x <= ~(hcnt_3x >= HSYNC_start); - //TODO: VSYNC_3x - DE_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_3x_ref >= V_BACKPORCH) & (vcnt_3x_ref < V_BACKPORCH + V_ACTIVE)); + HSYNC_3x <= (hcnt_3x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL; + if (FID_cur == `FID_EVEN) + VSYNC_3x <= (vcnt_3x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL; + else begin + if ((vcnt_3x+1'b1 == 11'd0) & (line_out_idx_3x == 1) & (hcnt_3x == (hmax[~line_idx]>>1)+1'b1)) + VSYNC_3x <= `VSYNC_POL; + else if ((vcnt_3x+1'b1 == V_SYNCLEN) & (line_out_idx_3x == 1) & (hcnt_3x == (hmax[~line_idx]>>1)+1'b1)) + VSYNC_3x <= ~`VSYNC_POL; end + + DE_3x <= ((hcnt_3x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_3x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_3x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_3x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE)); + end end always @(posedge pclk_4x or negedge reset_n) begin - if (!reset_n) - begin - hcnt_4x_aspfix <= 0; - DE_3x_prev4x <= 0; - hcnt_4x <= 0; - vcnt_4x <= 0; - vcnt_4x_ref <= 0; - lines_4x <= 0; - R_4x <= 8'h00; - G_4x <= 8'h00; - B_4x <= 8'h00; - HSYNC_4x <= 0; - DE_4x <= 0; - pclk_4x_cnt <= 0; - pclk_1x_prev4x <= 0; - line_out_idx_4x <= 0; - hcnt_4x_opt <= 0; - hcnt_4x_opt_ctr <= 0; - end - else - begin + if (!reset_n) begin + hcnt_4x <= 0; + vcnt_4x <= 0; + line_out_idx_4x <= 0; + end else begin + // TODO: better implementation if ((DE_3x == 1) & (DE_3x_prev4x == 0)) hcnt_4x_aspfix <= hcnt_3x - 160; @@ -802,50 +688,34 @@ begin hcnt_4x_aspfix <= hcnt_4x_aspfix + 1'b1; DE_3x_prev4x <= DE_3x; - - - if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x - begin - hcnt_4x <= 0; - line_out_idx_4x <= 0; - hcnt_4x_opt <= H_OPT_SAMPLE_SEL; + + if ((pclk_4x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x + hcnt_4x <= 0; + hcnt_4x_opt <= H_OPT_SAMPLE_SEL; + hcnt_4x_opt_ctr <= 0; + line_out_idx_4x <= 0; + if (frame_change) + vcnt_4x <= -1; + else if (line_change & (FID_cur == `FID_EVEN)) + vcnt_4x <= vcnt_4x + 1'b1; + end else if (hcnt_4x == hmax[~line_idx]) begin + hcnt_4x <= 0; + line_out_idx_4x <= line_out_idx_4x + 1'b1; + hcnt_4x_opt <= H_OPT_SAMPLE_SEL; + hcnt_4x_opt_ctr <= 0; + if ((FID_cur == `FID_ODD) && (line_out_idx_4x == 1)) + vcnt_4x <= vcnt_4x + 1'b1; + end else begin + hcnt_4x <= hcnt_4x + 1'b1; + if (hcnt_4x >= H_OPT_STARTOFF) begin + if (hcnt_4x_opt_ctr == H_OPT_SCALE-1'b1) begin + hcnt_4x_opt <= hcnt_4x_opt + H_OPT_SAMPLE_MULT; hcnt_4x_opt_ctr <= 0; - end - else if (hcnt_4x == hmax[~line_idx]) - begin - hcnt_4x <= 0; - line_out_idx_4x <= line_out_idx_4x + 1'b1; - hcnt_4x_opt <= H_OPT_SAMPLE_SEL; - hcnt_4x_opt_ctr <= 0; - end - else - begin - hcnt_4x <= hcnt_4x + 1'b1; - if (hcnt_4x >= H_OPT_STARTOFF) - begin - if (hcnt_4x_opt_ctr == H_OPT_SCALE-1'b1) - begin - hcnt_4x_opt <= hcnt_4x_opt + H_OPT_SAMPLE_MULT; - hcnt_4x_opt_ctr <= 0; - end - else - hcnt_4x_opt_ctr <= hcnt_4x_opt_ctr + 1'b1; - end - end - - if ((pclk_4x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x - begin - vcnt_4x <= 0; - vcnt_4x_ref <= 0; - lines_4x <= vcnt_4x; - end - else if (hcnt_4x == hmax[~line_idx]) - begin - vcnt_4x <= vcnt_4x + 1'b1; - if (line_out_idx_4x == 3) - vcnt_4x_ref <= vcnt_4x_ref + 1'b1; - end - + end else + hcnt_4x_opt_ctr <= hcnt_4x_opt_ctr + 1'b1; + end + end + //track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg) if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3)) pclk_4x_cnt <= 0; @@ -854,81 +724,44 @@ begin pclk_1x_prev4x <= pclk_1x; - - R_4x <= R_lbuf; - G_4x <= G_lbuf; - B_4x <= B_lbuf; - HSYNC_4x <= ~(hcnt_4x >= HSYNC_start); - //TODO: VSYNC_4x - DE_4x <= ((hcnt_4x >= H_BACKPORCH) & (hcnt_4x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_4x_ref >= V_BACKPORCH) & (vcnt_4x_ref < V_BACKPORCH + V_ACTIVE)); - end + HSYNC_4x <= (hcnt_4x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL; + VSYNC_4x <= (vcnt_4x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL; + DE_4x <= ((hcnt_4x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_4x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_4x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_4x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE)); + end end always @(posedge pclk_5x or negedge reset_n) begin - if (!reset_n) - begin + if (!reset_n) begin + hcnt_5x <= 0; + vcnt_5x <= 0; + line_out_idx_5x <= 0; + end else begin + if ((pclk_5x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x hcnt_5x <= 0; - vcnt_5x <= 0; - vcnt_5x_ref <= 0; - lines_5x <= 0; - R_5x <= 8'h00; - G_5x <= 8'h00; - B_5x <= 8'h00; - HSYNC_5x <= 0; - DE_5x <= 0; - pclk_5x_cnt <= 0; - pclk_1x_prev5x <= 0; - pclk_1x_prevprev5x <= 0; - line_out_idx_5x <= 0; - hcnt_5x_opt <= 0; + hcnt_5x_opt <= H_OPT_SAMPLE_SEL + 11'd120; hcnt_5x_opt_ctr <= 0; - hcnt_5x_hscomp <= 0; + line_out_idx_5x <= 0; + if (frame_change) + vcnt_5x <= -1; + else if (line_change) + vcnt_5x <= vcnt_5x + 1'b1; + end else if (hcnt_5x == hmax[~line_idx]) begin + hcnt_5x <= 0; + line_out_idx_5x <= line_out_idx_5x + 1'b1; + hcnt_5x_opt <= H_OPT_SAMPLE_SEL + 11'd120; + hcnt_5x_opt_ctr <= 0; + end else begin + hcnt_5x <= hcnt_5x + 1'b1; + if (hcnt_5x >= H_OPT_STARTOFF) begin + if (hcnt_5x_opt_ctr == H_OPT_SCALE-1'b1) begin + hcnt_5x_opt <= hcnt_5x_opt + H_OPT_SAMPLE_MULT; + hcnt_5x_opt_ctr <= 0; + end else + hcnt_5x_opt_ctr <= hcnt_5x_opt_ctr + 1'b1; + end end - else - begin - if ((pclk_5x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x - begin - hcnt_5x <= 0; - line_out_idx_5x <= 0; - hcnt_5x_opt <= 120 + H_OPT_SAMPLE_SEL; - hcnt_5x_opt_ctr <= 0; - end - else if (hcnt_5x == hmax[~line_idx]) - begin - hcnt_5x <= 0; - line_out_idx_5x <= line_out_idx_5x + 1'b1; - hcnt_5x_opt <= 120 + H_OPT_SAMPLE_SEL; - hcnt_5x_opt_ctr <= 0; - end - else - begin - hcnt_5x <= hcnt_5x + 1'b1; - if (hcnt_5x >= H_OPT_STARTOFF) - begin - if (hcnt_5x_opt_ctr == H_OPT_SCALE-1'b1) - begin - hcnt_5x_opt <= hcnt_5x_opt + H_OPT_SAMPLE_MULT; - hcnt_5x_opt_ctr <= 0; - end - else - hcnt_5x_opt_ctr <= hcnt_5x_opt_ctr + 1'b1; - end - end - - if ((pclk_5x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x - begin - vcnt_5x <= 0; - vcnt_5x_ref <= 0; - lines_5x <= vcnt_5x; - end - else if (hcnt_5x == hmax[~line_idx]) - begin - vcnt_5x <= vcnt_5x + 1'b1; - if (line_out_idx_5x == 4) - vcnt_5x_ref <= vcnt_5x_ref + 1'b1; - end - + //track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg) if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4)) pclk_5x_cnt <= 0; @@ -938,16 +771,12 @@ begin pclk_1x_prev5x <= pclk_1x; pclk_1x_prevprev5x <= pclk_1x_prev5x; - hcnt_5x_hscomp <= hcnt_5x + 121; - - - R_5x <= R_lbuf; - G_5x <= G_lbuf; - B_5x <= B_lbuf; - HSYNC_5x <= ~(hcnt_5x >= HSYNC_start); - //TODO: VSYNC_5x - DE_5x <= ((hcnt_5x >= H_BACKPORCH - H_L5BORDER) & (hcnt_5x < H_BACKPORCH + H_ACTIVE + H_L5BORDER)) & ((vcnt_5x_ref >= V_BACKPORCH) & (vcnt_5x_ref < V_BACKPORCH + V_ACTIVE)); - end + hcnt_5x_hscomp <= hcnt_5x + 11'd121; + + HSYNC_5x <= (hcnt_5x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL; + VSYNC_5x <= (vcnt_5x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL; + DE_5x <= ((hcnt_5x >= H_SYNCLEN+H_BACKPORCH-H_L5BORDER) & (hcnt_5x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE+H_L5BORDER)) & ((vcnt_5x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_5x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE)); + end end endmodule diff --git a/rtl/videogen.v b/rtl/videogen.v index 455f4c6..5b82bd8 100644 --- a/rtl/videogen.v +++ b/rtl/videogen.v @@ -1,5 +1,5 @@ // -// Copyright (C) 2015-2016 Markus Hiienkari +// Copyright (C) 2015-2017 Markus Hiienkari // // This file is part of Open Source Scan Converter project. // @@ -72,79 +72,57 @@ reg [7:0] V_gen; //HSYNC gen (negative polarity) always @(posedge clk27 or negedge reset_n) begin - if (!reset_n) - begin + if (!reset_n) begin + h_cnt <= 0; + HSYNC_out <= 0; + end else begin + //Hsync counter + if (h_cnt < H_TOTAL-1) + h_cnt <= h_cnt + 1'b1; + else h_cnt <= 0; - HSYNC_out <= 0; - end - else - begin - //Hsync counter - if (h_cnt < H_TOTAL-1 ) - h_cnt <= h_cnt + 1'b1; - else - h_cnt <= 0; - - //Hsync signal - HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1; - end + + //Hsync signal + HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1; + end end //VSYNC gen (negative polarity) always @(posedge clk27 or negedge reset_n) begin - if (!reset_n) - begin - v_cnt <= 0; - VSYNC_out <= 0; - end - else - begin - if (h_cnt == 0) - begin - //Vsync counter - if (v_cnt < V_TOTAL-1 ) - v_cnt <= v_cnt + 1'b1; - else - v_cnt <= 0; - - //Vsync signal - VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1; - end - end -end - -//Data gen -always @(posedge clk27 or negedge reset_n) -begin - if (!reset_n) - begin - V_gen <= 8'h00; - end - else - begin - if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA)) - V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00; - else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER)) - V_gen <= 8'h50; + if (!reset_n) begin + v_cnt <= 0; + VSYNC_out <= 0; + end else begin + //Vsync counter + if (h_cnt == H_TOTAL-1) begin + if (v_cnt < V_TOTAL-1) + v_cnt <= v_cnt + 1'b1; else - V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1; - /*else - V_gen <= 8'h00;*/ + v_cnt <= 0; end + + //Vsync signal + VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1; + end end -//Enable gen +//Data and ENABLE gen always @(posedge clk27 or negedge reset_n) begin - if (!reset_n) - begin - ENABLE_out <= 1'b0; - end - else - begin - ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE); - end + if (!reset_n) begin + V_gen <= 8'h00; + ENABLE_out <= 1'b0; + end else begin + if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA)) + V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00; + else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER)) + V_gen <= 8'h50; + else + V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1; + + ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE); + end end endmodule diff --git a/software/sys_controller/it6613/HDMI_TX.c b/software/sys_controller/it6613/HDMI_TX.c index f96ced0..0c8098d 100644 --- a/software/sys_controller/it6613/HDMI_TX.c +++ b/software/sys_controller/it6613/HDMI_TX.c @@ -78,19 +78,18 @@ bool HDMITX_HPD(void){ } -void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool ITU709) +void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep) { - AVI_InfoFrame AviInfo; - alt_u8 pixelrep = 0; - - OS_PRINTF("HDMITX_SetAVIInfoFrame, VIC=%d, ColorMode=%d, Aspect-Ratio=%s, ITU709=%s\n", - VIC, OutputColorMode, b16x9?"16:9":"4:3", ITU709?"Yes":"No"); + AVI_InfoFrame AviInfo; + + OS_PRINTF("HDMITX_SetAVIInfoFrame, VIC=%d, Aspect-Ratio=%s, ITU709=%s, ITC=%s, pixelrep=%u\n", + VIC, b16x9?"16:9":"4:3", ITU709?"Yes":"No", ITC?"Yes":"No", pixelrep); AviInfo.pktbyte.AVI_HB[0] = AVI_INFOFRAME_TYPE|0x80 ; AviInfo.pktbyte.AVI_HB[1] = AVI_INFOFRAME_VER ; AviInfo.pktbyte.AVI_HB[2] = AVI_INFOFRAME_LEN ; - switch(OutputColorMode) + /*switch(OutputColorMode) { case F_MODE_YUV444: // AviInfo.info.ColorMode = 2 ; @@ -105,14 +104,15 @@ void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool // AviInfo.info.ColorMode = 0 ; AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ; break ; - } + }*/ + AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ; AviInfo.pktbyte.AVI_DB[0] |= 2; // indicate "no overscan" AviInfo.pktbyte.AVI_DB[1] = 8 ; - AviInfo.pktbyte.AVI_DB[1] |= (!b16x9)?(1<<4):(2<<4) ; // 4:3 or 16:9 + //AviInfo.pktbyte.AVI_DB[1] |= (!b16x9)?(1<<4):(2<<4) ; // 4:3 or 16:9 AviInfo.pktbyte.AVI_DB[1] |= (!ITU709)?(1<<6):(2<<6) ; // ITU709 or ITU601 - AviInfo.pktbyte.AVI_DB[2] = (1<<3) ; // indicate "full-range RGB" + AviInfo.pktbyte.AVI_DB[2] = ((1<<3) | (ITC<<7)) ; // indicate "full-range RGB", setup ITC bit AviInfo.pktbyte.AVI_DB[3] = VIC ; - AviInfo.pktbyte.AVI_DB[4] = pixelrep & 3 ; + AviInfo.pktbyte.AVI_DB[4] = pixelrep & 3 ; AviInfo.pktbyte.AVI_DB[5] = 0 ; AviInfo.pktbyte.AVI_DB[6] = 0 ; AviInfo.pktbyte.AVI_DB[7] = 0 ; diff --git a/software/sys_controller/it6613/HDMI_TX.h b/software/sys_controller/it6613/HDMI_TX.h index 061e7e6..464761b 100644 --- a/software/sys_controller/it6613/HDMI_TX.h +++ b/software/sys_controller/it6613/HDMI_TX.h @@ -12,7 +12,7 @@ bool HDMITX_ChipVerify(void); bool HDMITX_HPD(void); void HDMITX_ChangeVideoTiming(int VIC); void HDMITX_ChangeVideoTimingAndColor(int VIC, COLOR_TYPE Color); -void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool ITU709); +void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep); void HDMITX_DisableVideoOutput(void); void HDMITX_EnableVideoOutput(void); diff --git a/software/sys_controller/it6613/it6613_drv.c b/software/sys_controller/it6613/it6613_drv.c index 1c00e9b..736db30 100644 --- a/software/sys_controller/it6613/it6613_drv.c +++ b/software/sys_controller/it6613/it6613_drv.c @@ -3274,25 +3274,16 @@ DISABLE_MPG_INFOFRM_PKT() HDMITX_WriteI2C_Byte(REG_TX_MPG_INFOFRM_CTRL,0); } -void HDMITX_SetPixelRepetition(int pixelrep, int set_infoframe) { +void HDMITX_SetPixelRepetition(BYTE pixelrep, BYTE set_infoframe) { BYTE pllpr; - //Switch_HDMITX_Bank(0); - pllpr = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1) & 0x2F; - pixelrep &= 0x3; - - if (set_infoframe) { - HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, pllpr); - Switch_HDMITX_Bank(1); - HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB5, pixelrep); - } else { - pllpr |= (1<<4)|(pixelrep<<6); - HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, pllpr); - Switch_HDMITX_Bank(1); - HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB5, 0); - } - Switch_HDMITX_Bank(0); + pllpr = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1) & 0x2F; + + if (!set_infoframe) + pllpr |= (1<<4)|((pixelrep&0x3)<<6); + + HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, pllpr); } ////////////////////////////////////////////////////////////////////// diff --git a/software/sys_controller/it6613/it6613_drv.h b/software/sys_controller/it6613/it6613_drv.h index 53316ac..8fdaab5 100644 --- a/software/sys_controller/it6613/it6613_drv.h +++ b/software/sys_controller/it6613/it6613_drv.h @@ -834,7 +834,7 @@ BOOL EnableAudioInfoFrame(BYTE bEnable,BYTE *pAudioInfoFrame); void SetAVMute(BYTE bEnable) ; void SetOutputColorDepthPhase(BYTE ColorDepth,BYTE bPhase) ; void Get6613Reg(BYTE *pReg) ; -void HDMITX_SetPixelRepetition(int pixelrep, int set_infoframe); +void HDMITX_SetPixelRepetition(BYTE pixelrep, BYTE set_infoframe); //////////////////////////////////////////////////////////////////// // Required Interfance diff --git a/software/sys_controller/mem_init/sys_onchip_memory2_0.hex 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:2021F8000000000000000000000000000000000000000000000000000000000000000000C7 :202200000000000000000000000000000000000000000000000000000000000000000000BE :202208000000000000000000000000000000000000000000000000000000000000000000B6 diff --git a/software/sys_controller/ossc/av_controller.c b/software/sys_controller/ossc/av_controller.c index 3282e12..5395a68 100644 --- a/software/sys_controller/ossc/av_controller.c +++ b/software/sys_controller/ossc/av_controller.c @@ -68,7 +68,7 @@ alt_u8 stable_frames; alt_u8 update_cur_vm; alt_u8 vm_sel, vm_edit, profile_sel; -alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_active, tc_v_active, tc_h_bporch, tc_v_bporch; +alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active; char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1]; @@ -94,8 +94,7 @@ inline void SetupAudio(tx_mode_t mode) if (tc.tx_mode == TX_HDMI) { alt_u32 pclk_out = (TVP_EXTCLK_HZ/cm.clkcnt)*video_modes[cm.id].h_total*cm.sample_mult*(cm.fpga_vmultmode+1); - if (cm.hdmitx_pixelrep == HDMITX_PIXELREP_2X) - pclk_out *= 2; + pclk_out *= 1+cm.hdmitx_pixelrep; printf("PCLK_out: %luHz\n", pclk_out); EnableAudioOutput4OSSC(pclk_out, tc.audio_dw_sampl, tc.audio_swap_lr); @@ -122,9 +121,10 @@ inline void TX_enable(tx_mode_t mode) // re-setup EnableVideoOutput(PCLK_MEDIUM, COLOR_RGB444, COLOR_RGB444, !mode); - //TODO: set correct VID based on mode + //TODO: set VIC based on mode if (mode == TX_HDMI) { - HDMITX_SetAVIInfoFrame(HDMI_480p60, F_MODE_RGB444, 0, 0); + HDMITX_SetAVIInfoFrame(HDMI_Unkown, 0, 0, tc.hdmi_itc, cm.hdmitx_pixelrep); + cm.cc.hdmi_itc = tc.hdmi_itc; #ifdef DIY_AUDIO SetupAudio(mode); #endif @@ -184,7 +184,7 @@ status_t get_status(tvp_input_t input, video_format format) //alt_u8 refclk; alt_u8 sync_active; alt_u8 vsyncmode; - alt_u16 fpga_totlines; + alt_u16 totlines_tvp; alt_u16 h_samplerate; status_t status; static alt_8 act_ctr; @@ -196,14 +196,14 @@ status_t get_status(tvp_input_t input, video_format format) // Wait until vsync active (avoid noise coupled to I2C bus on earlier prototypes) for (ctr=0; ctr> 16) & 0x3) : 0; + vsyncmode = cm.sync_active ? ((IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3) : 0; // Read sync information from TVP7002 status registers data1 = tvp_readreg(TVP_LINECNT1); @@ -215,15 +215,15 @@ status_t get_status(tvp_input_t input, video_format format) data2 = tvp_readreg(TVP_CLKCNT2); clkcnt = ((data2 & 0x0f) << 8) | data1; - // Read how many lines FPGA actually receives from TVP7002 - fpga_totlines = (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 18) & 0x7ff; + // Read how many lines TVP7002 outputs in reality + totlines_tvp = ((IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 18) & 0x7ff)+1; // NOTE: "progressive" may not have correct value if H-PLL is not locked (!cm.sync_active) if ((vsyncmode == 0x2) || (!cm.sync_active && (totlines < MIN_LINES_INTERLACED))) { progressive = 1; } else if (vsyncmode == 0x1) { progressive = 0; - totlines = fpga_totlines; //compensate skipped vsync + totlines = totlines_tvp; //compensate skipped vsync } valid_linecnt = check_linecnt(progressive, totlines); @@ -254,7 +254,7 @@ status_t get_status(tvp_input_t input, video_format format) if (valid_linecnt) { if ((totlines != cm.totlines) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) { - printf("totlines: %lu (cur) / %lu (prev), clkcnt: %lu (cur) / %lu (prev). FPGA_totlines: %u, VSM: %u\n", totlines, cm.totlines, clkcnt, cm.clkcnt, fpga_totlines, vsyncmode); + printf("totlines: %lu (cur) / %lu (prev), clkcnt: %lu (cur) / %lu (prev). totlines_tvp: %u, VSM: %u\n", totlines, cm.totlines, clkcnt, cm.clkcnt, totlines_tvp, vsyncmode); /*if (!cm.sync_active) act_ctr = 0;*/ stable_frames = 0; @@ -282,8 +282,6 @@ status_t get_status(tvp_input_t input, video_format format) if (update_cur_vm) { tvp_setup_hpll(cm.sample_mult*video_modes[cm.id].h_total, clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2)); - tvp_writereg(TVP_HSOUTWIDTH, cm.sample_mult*video_modes[cm.id].h_synclen-cm.hsync_cut); - status = (status < INFO_CHANGE) ? INFO_CHANGE : status; } @@ -348,14 +346,17 @@ status_t get_status(tvp_input_t input, video_format format) return status; } -// h_info: [31:30] [29:20] [19:9] [8:0] -// | H_MULTMODE[1:0] | H_MASK[9:0] | H_ACTIVE[10:0] | H_BACKPORCH[8:0] | +// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0] +// | H_MULTMODE[1:0] | H_L5FMT | | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] | // -// h_info2: [31:28] [27] [26:23] [22:19] [18:16] [15:13] [12:10] [9:0] -// | | H_L5FMT | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] | +// h_info2: [31:29] [28:19] [18:16] [15:13] [12:10] [9:0] +// | | H_MASK[9:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] | // -// v_info: [31:30] [29:28] [27] [26:24] [23:18] [17:7] [6] [5:0] -// | V_SCANLINEMODE[1:0] | V_SCANLINEID | | V_MULTMODE[2:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] | +// v_info: [31:29] [28:27] [26] [25:20] [19:17] [16:11] [10:0] +// | V_MULTMODE[2:0] | V_SCANLINEMODE[1:0] | V_SCANLINEID | V_MASK[5:0] | V_SYNCLEN[2:0] | V_BACKPORCH[5:0] | V_ACTIVE[10:0] | +// +// extra: [31:8] [7:4] [3:0] +// | | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] | // void set_videoinfo() { @@ -427,13 +428,29 @@ void set_videoinfo() h_border = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2); h_mask = h_border + h_opt_scale*cm.cc.h_mask; - h_opt_startoffs = h_border + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch) / cm.sample_mult); + h_opt_startoffs = h_border + (cm.sample_mult-h_opt_scale)*((alt_u16)video_modes[cm.id].h_synclen+(alt_u16)video_modes[cm.id].h_backporch); h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult; - printf("h_opt_startoffs: %u\n", h_opt_startoffs); + printf("h_border: %u, h_opt_startoffs: %u\n", h_border, h_opt_startoffs); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.fpga_hmultmode<<30) | (h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, ((cm.cc.l5_fmt!=L5FMT_1600x1200)<<27) | (cm.cc.mask_br<<23) | (cm.cc.sl_str<<19) | (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (cm.cc.sl_id<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (v_active<<7) | v_backporch); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (cm.fpga_hmultmode<<30) | + ((cm.cc.l5_fmt!=L5FMT_1600x1200)<<29) | + ((((cm.sample_mult*video_modes[cm.id].h_synclen)-cm.hsync_cut)&0xff)<<20) | + (((cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch)&0x1ff)<<11) | + ((cm.sample_mult*video_modes[cm.id].h_active)&0x7ff)); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_4_BASE, (h_mask<<19) | + (h_opt_scale<<16) | + (cm.sample_sel<<13) | + (cm.sample_mult<<10) | + h_opt_startoffs); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (cm.fpga_vmultmode<<29) | + (sl_mode_fpga<<27) | + (cm.cc.sl_id<<26) | + (cm.cc.v_mask<<20) | + (video_modes[cm.id].v_synclen<<17) | + (v_backporch<<11) | + v_active); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, (cm.cc.mask_br<<4) | + cm.cc.sl_str); } // Configure TVP7002 and scan converter logic based on the video mode @@ -484,7 +501,6 @@ void program_mode() cm.clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2), (alt_u8)h_synclen_px, - cm.sample_mult*video_modes[cm.id].h_synclen-cm.hsync_cut, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold); @@ -492,6 +508,8 @@ void program_mode() cm.sample_sel = tvp_set_hpll_phase(cm.cc.sampler_phase, cm.sample_mult); HDMITX_SetPixelRepetition(cm.hdmitx_pixelrep, (cm.cc.tx_mode==TX_HDMI) ? cm.hdmitx_pixr_ifr : 0); + if (cm.cc.tx_mode==TX_HDMI) + HDMITX_SetAVIInfoFrame(HDMI_Unkown, 0, 0, cm.cc.hdmi_itc, cm.hdmitx_pixr_ifr ? cm.hdmitx_pixelrep : 0); set_videoinfo(); @@ -567,10 +585,11 @@ void vm_display(alt_u8 code) { vm_edit = vm_sel; tc_h_samplerate = video_modes[vm_edit].h_total; tc_h_synclen = (alt_u16)video_modes[vm_edit].h_synclen; - tc_h_active = video_modes[vm_edit].h_active; - tc_v_active = video_modes[vm_edit].v_active; tc_h_bporch = (alt_u16)video_modes[vm_edit].h_backporch; + tc_h_active = video_modes[vm_edit].h_active; + tc_v_synclen = (alt_u16)video_modes[vm_edit].v_synclen; tc_v_bporch = (alt_u16)video_modes[vm_edit].v_backporch; + tc_v_active = video_modes[vm_edit].v_active; break; case NO_ACTION: default: @@ -583,18 +602,20 @@ void vm_tweak(alt_u16 v) { if (cm.sync_active && (cm.id == vm_edit)) { if ((video_modes[cm.id].h_total != tc_h_samplerate) || (video_modes[cm.id].h_synclen != tc_h_synclen) || - (video_modes[cm.id].h_active != tc_h_active) || - (video_modes[cm.id].v_active != tc_v_active) || (video_modes[cm.id].h_backporch != (alt_u8)tc_h_bporch) || - (video_modes[cm.id].v_backporch != (alt_u8)tc_v_bporch)) + (video_modes[cm.id].h_active != tc_h_active) || + (video_modes[cm.id].v_synclen != tc_v_synclen) || + (video_modes[cm.id].v_backporch != (alt_u8)tc_v_bporch) || + (video_modes[cm.id].v_active != tc_v_active)) update_cur_vm = 1; } video_modes[vm_edit].h_total = tc_h_samplerate; video_modes[vm_edit].h_synclen = (alt_u8)tc_h_synclen; - video_modes[vm_edit].h_active = tc_h_active; - video_modes[vm_edit].v_active = tc_v_active; video_modes[vm_edit].h_backporch = (alt_u8)tc_h_bporch; + video_modes[vm_edit].h_active = tc_h_active; + video_modes[vm_edit].v_synclen = (alt_u8)tc_v_synclen; video_modes[vm_edit].v_backporch = (alt_u8)tc_v_bporch; + video_modes[vm_edit].v_active = tc_v_active; sniprintf(menu_row2, LCD_ROW_LEN+1, "%u", v); } @@ -607,8 +628,8 @@ int init_hw() // Reset hardware IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, AV_RESET_N|LCD_BL); IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, 0x00000000); IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, 0x00000000); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, 0x00000000); usleep(10000); // unreset hw @@ -826,6 +847,12 @@ int main() cm.cc.tx_mode = tc.tx_mode; cm.clkcnt = 0; //TODO: proper invalidate } + if ((tc.tx_mode == TX_HDMI) && (tc.hdmi_itc != cm.cc.hdmi_itc)) { + //EnableAVIInfoFrame(FALSE, NULL); + printf("setting ITC to %d\n", tc.hdmi_itc); + HDMITX_SetAVIInfoFrame(0, 0, 0, tc.hdmi_itc, cm.hdmitx_pixelrep); + cm.cc.hdmi_itc = tc.hdmi_itc; + } if (av_init) { status = get_status(target_input, target_format); diff --git a/software/sys_controller/ossc/avconfig.c b/software/sys_controller/ossc/avconfig.c index 66e4a6a..5e2715f 100644 --- a/software/sys_controller/ossc/avconfig.c +++ b/software/sys_controller/ossc/avconfig.c @@ -47,6 +47,7 @@ const avconfig_t tc_default = { .pm_480i = 1, .pm_1080i = 1, .tvp_hpll2x = 1, + .hdmi_itc = 1, .sampler_phase = DEFAULT_SAMPLER_PHASE, .sync_vth = DEFAULT_SYNC_VTH, .linelen_tol = DEFAULT_LINELEN_TOL, diff --git a/software/sys_controller/ossc/avconfig.h b/software/sys_controller/ossc/avconfig.h index fce10ea..c58d51a 100644 --- a/software/sys_controller/ossc/avconfig.h +++ b/software/sys_controller/ossc/avconfig.h @@ -62,6 +62,7 @@ typedef struct { alt_u8 v_mask; alt_u8 mask_br; alt_u8 tx_mode; + alt_u8 hdmi_itc; alt_u8 s480p_mode; alt_u8 sampler_phase; alt_u8 tvp_hpll2x; diff --git a/software/sys_controller/ossc/controls.c b/software/sys_controller/ossc/controls.c index 81e9b0c..3752774 100644 --- a/software/sys_controller/ossc/controls.c +++ b/software/sys_controller/ossc/controls.c @@ -111,7 +111,7 @@ void parse_control() // one for each video_group alt_u8* pmcfg_ptr[] = { &pt_only, &tc.pm_240p, &tc.pm_384p, &tc.pm_480i, &tc.pm_480p, &tc.pm_480p, &tc.pm_1080i }; - alt_u8 valid_pm[] = { 0x1, 0x1f, 0x3, 0x3, 0x3, 0x3, 0x3 }; + alt_u8 valid_pm[] = { 0x1, 0x1f, 0x3, 0xf, 0x3, 0x3, 0x3 }; if (remote_code) printf("RCODE: 0x%.4lx, %d\n", remote_code, remote_rpt); @@ -147,10 +147,10 @@ void parse_control() break; case RC_INFO: sniprintf(menu_row1, LCD_ROW_LEN+1, "VMod: %s", video_modes[cm.id].name); - sniprintf(menu_row2, LCD_ROW_LEN+1, "LO: %u VSM: %u", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0x7ff, (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3); + sniprintf(menu_row2, LCD_ROW_LEN+1, "LC: %u VSM: %u", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3); lcd_write_menu(); printf("Mod: %s\n", video_modes[cm.id].name); - printf("Lines: %u M: %u\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0x7ff, cm.macrovis); + printf("Lines: %u M: %u\n", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, cm.macrovis); break; case RC_LCDBL: sys_ctrl ^= LCD_BL; diff --git a/software/sys_controller/ossc/firmware.h b/software/sys_controller/ossc/firmware.h index 4fd18d4..37e0955 100644 --- a/software/sys_controller/ossc/firmware.h +++ b/software/sys_controller/ossc/firmware.h @@ -24,7 +24,7 @@ #include "sysconfig.h" #define FW_VER_MAJOR 0 -#define FW_VER_MINOR 76 +#define FW_VER_MINOR 77 #ifdef DIY_AUDIO #define FW_SUFFIX1 "a" diff --git a/software/sys_controller/ossc/menu.c b/software/sys_controller/ossc/menu.c index 9878221..4d6d4cf 100644 --- a/software/sys_controller/ossc/menu.c +++ b/software/sys_controller/ossc/menu.c @@ -37,7 +37,7 @@ extern char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1]; extern avconfig_t tc; -extern alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_active, tc_v_active, tc_h_bporch, tc_v_bporch; +extern alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active; extern alt_u32 remote_code; extern alt_u16 rc_keymap[REMOTE_MAX_KEYS]; @@ -52,7 +52,7 @@ static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") }; static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" }; static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" }; -static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" }; +static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" }; static const char *pm_384p_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" }; static const char *ar_256col_desc[] = { "4:3", "8:7" }; static const char *tx_mode_desc[] = { "HDMI", "DVI" }; @@ -73,10 +73,11 @@ static void value_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, " %u", MENU(menu_advtiming, P99_PROTECT({ \ { LNG("H. samplerate","ｽｲﾍｲｻﾝﾌﾟﾙﾚﾄ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_samplerate, H_TOTAL_MIN, H_TOTAL_MAX, vm_tweak } } }, { LNG("H. synclen","ｽｲﾍｲﾗｲﾝﾄﾞｳｷｼﾝｺﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_synclen, H_SYNCLEN_MIN, H_SYNCLEN_MAX, vm_tweak } } }, - { LNG("H. active","ｽｲﾍｲｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_active, H_ACTIVE_MIN, H_ACTIVE_MAX, vm_tweak } } }, - { LNG("V. active","ｽｲﾁｮｸｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_active, V_ACTIVE_MIN, V_ACTIVE_MAX, vm_tweak } } }, { LNG("H. backporch","ｽｲﾍｲﾊﾞｯｸﾎﾟｰﾁ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_bporch, H_BPORCH_MIN, H_BPORCH_MAX, vm_tweak } } }, + { LNG("H. active","ｽｲﾍｲｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_active, H_ACTIVE_MIN, H_ACTIVE_MAX, vm_tweak } } }, + { LNG("V. synclen","ｽｲﾁｮｸﾗｲﾝﾄﾞｳｷｼﾝｺﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_synclen, V_SYNCLEN_MIN, V_SYNCLEN_MAX, vm_tweak } } }, { LNG("V. backporch","ｽｲﾁｮｸﾊﾞｯｸﾎﾟｰﾁ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_bporch, V_BPORCH_MIN, V_BPORCH_MAX, vm_tweak } } }, + { LNG("V. active","ｽｲﾁｮｸｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_active, V_ACTIVE_MIN, V_ACTIVE_MAX, vm_tweak } } }, })) @@ -120,6 +121,7 @@ MENU(menu_output, P99_PROTECT({ \ { LNG("Line5x format","Line5xｹｲｼｷ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_fmt, OPT_WRAP, SETTING_ITEM(l5_fmt_desc) } } }, { LNG("256x240 aspect","256x240ｱｽﾍﾟｸﾄ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.ar_256col, OPT_WRAP, SETTING_ITEM(ar_256col_desc) } } }, { LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } }, + { "HDMI ITC", OPT_AVCONFIG_SELECTION, { .sel = { &tc.hdmi_itc, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, { LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } }, })) diff --git a/software/sys_controller/tvp7002/tvp7002.c b/software/sys_controller/tvp7002/tvp7002.c index 8753426..bdea7c9 100644 --- a/software/sys_controller/tvp7002/tvp7002.c +++ b/software/sys_controller/tvp7002/tvp7002.c @@ -342,7 +342,7 @@ void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen) } } -void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u16 h_syncoutlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold) +void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold) { // Clamp position and ALC tvp_set_clamp_position(type, h_syncinlen); @@ -370,9 +370,6 @@ void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per // Default (3,3) coast may lead to PLL jitter and sync loss (e.g. SNES) tvp_set_hpllcoast(pre_coast, post_coast); - - // Hsync output width - tvp_writereg(TVP_HSOUTWIDTH, h_syncoutlen); } void tvp_source_sel(tvp_input_t input, video_format fmt) diff --git a/software/sys_controller/tvp7002/tvp7002.h b/software/sys_controller/tvp7002/tvp7002.h index 10b22b3..0174db3 100644 --- a/software/sys_controller/tvp7002/tvp7002.h +++ b/software/sys_controller/tvp7002/tvp7002.h @@ -100,7 +100,7 @@ void tvp_set_sog_thold(alt_u8 val); void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen); -void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u16 h_syncoutlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold); +void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold); void tvp_source_sel(tvp_input_t input, video_format fmt); diff --git a/software/sys_controller/tvp7002/video_modes.c b/software/sys_controller/tvp7002/video_modes.c index f847688..9d532b8 100644 --- a/software/sys_controller/tvp7002/video_modes.c +++ b/software/sys_controller/tvp7002/video_modes.c @@ -46,20 +46,33 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t for (i=0; i GROUP_1080I) { - printf("WARNING: Corrupted mode (id %d)\n", i); - continue; + break; } target_lm = valid_lm[*group_ptr[video_modes[i].group]]; @@ -106,6 +119,8 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t case MODE_L3_GEN_16_9: cm.fpga_vmultmode = FPGA_V_MULTMODE_3X; cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH; + if (video_modes[i].group == GROUP_480I) + cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X; break; case MODE_L3_GEN_4_3: cm.fpga_vmultmode = FPGA_V_MULTMODE_3X; @@ -124,6 +139,8 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t case MODE_L4_GEN_4_3: cm.fpga_vmultmode = FPGA_V_MULTMODE_4X; cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH; + if (video_modes[i].group == GROUP_480I) + cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X; break; case MODE_L4_320_COL: cm.fpga_vmultmode = FPGA_V_MULTMODE_4X; diff --git a/software/sys_controller/tvp7002/video_modes.h b/software/sys_controller/tvp7002/video_modes.h index b28067d..f8b9e4f 100644 --- a/software/sys_controller/tvp7002/video_modes.h +++ b/software/sys_controller/tvp7002/video_modes.h @@ -23,18 +23,20 @@ #include #include "sysconfig.h" -#define H_ACTIVE_MIN 200 -#define H_ACTIVE_MAX 1920 -#define V_ACTIVE_MIN 200 -#define V_ACTIVE_MAX 1200 #define H_TOTAL_MIN 300 #define H_TOTAL_MAX 2300 #define H_SYNCLEN_MIN 10 #define H_SYNCLEN_MAX 200 #define H_BPORCH_MIN 1 #define H_BPORCH_MAX 255 +#define H_ACTIVE_MIN 200 +#define H_ACTIVE_MAX 1920 +#define V_SYNCLEN_MIN 1 +#define V_SYNCLEN_MAX 7 #define V_BPORCH_MIN 1 -#define V_BPORCH_MAX 255 +#define V_BPORCH_MAX 63 +#define V_ACTIVE_MIN 200 +#define V_ACTIVE_MAX 1200 typedef enum { FORMAT_RGBS = 0, @@ -97,37 +99,49 @@ typedef struct { mode_flags flags; } mode_data_t; + #define VIDEO_MODES_DEF { \ - { "1280x240", 1280, 240, 6000, 1560, 262, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \ - { "960x240", 960, 240, 6000, 1170, 262, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \ - /*{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2*/ \ - { "320x240", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \ - { "256x240", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \ - { "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ - { "1536x240", 1536, 240, 6000, 2046, 262, 234, 16, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \ - { "1280x288", 1280, 288, 5000, 1560, 312, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \ - { "960x288", 960, 288, 5000, 1170, 312, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \ - { "320x240LB", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \ - { "256x240LB", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \ - { "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ + /* 240p modes */ \ + { "1536x240", 1536, 240, 6000, 2046, 262, 234, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \ + { "1280x240", 1280, 240, 6000, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \ + { "960x240", 960, 240, 6000, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \ + { "320x240", 320, 240, 6000, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \ + { "256x240", 256, 240, 6000, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \ + { "240p", 720, 240, 6000, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ + /* 288p modes */ \ { "1536x240L", 1536, 240, 5000, 2046, 312, 234, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \ - { "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* Sega Model 2 */ \ - { "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* X68k @ 24kHz */ \ - { "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \ - { "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \ - { "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \ - { "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, /* X68k @ 31kHz */ \ - { "576i", 720, 288, 5000, 864, 625, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \ - { "576p", 720, 576, 5000, 864, 625, 65, 32, 60, 6, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \ + { "1280x288", 1280, 288, 5000, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \ + { "960x288", 960, 288, 5000, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \ + { "320x240LB", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \ + { "256x240LB", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \ + { "288p", 720, 288, 5000, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ + /* 384p: Sega Model 2 */ \ + { "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ + /* 384p: X68k @ 24kHz */ \ + { "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ + /* ~525-line modes */ \ + { "480i", 720, 240, 5994, 858, 525, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \ + { "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \ + { "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \ + /* X68k @ 31kHz */ \ + { "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, \ + /* ~625-line modes */ \ + { "576i", 720, 288, 5000, 864, 625, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \ + { "576p", 720, 576, 5000, 864, 625, 68, 39, 64, 5, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \ { "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, GROUP_NONE, MODE_PT }, \ + /* 720p modes */ \ { "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \ { "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \ + /* VESA XGA and SXGA modes */ \ { "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, GROUP_NONE, MODE_PT }, \ { "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \ + /* PS2 GSM 960i mode */ \ { "640x960i", 640, 480, 5994, 800, 1050, 48, 33, 96, 2, (VIDEO_EDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \ + /* 1080i/p HDTV modes */ \ { "1080i", 1920, 540, 5994, 2200, 1125, 188, 16, 44, 5, VIDEO_HDTV, GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \ { "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \ { "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \ + /* VESA UXGA with reduced h.backporch */ \ { "1600x1200", 1600, 1200, 6000, 2160, 1250, 255, 46, 192, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \ } diff --git a/software/sys_controller_bsp/libhal_bsp.a b/software/sys_controller_bsp/libhal_bsp.a index 6ed23a7c785ee26b9ecf64db7a63d460dac1630f..6db8f32a9acbf1b7e52d29a45ee40e5fd88a9fdb 100644 GIT binary patch delta 1159 zcmZ8fUr19?9Okz_Zo|3F8M}AWSs}BRSlwk0BXTw$#b#x_6t19$)c(O9BqVZ`;2_!Z z6idPaBW4uBI*fxU%ta6NP_fJ?C=#UyAA(U9;Y;0NG(AmYe`0icCXI1xuMhBg!qHcl{5Lq9VPuc$^O#Ysx<)qDXW(;%q=5 znQ_xir-$&a%8)5N+p958_r$W5zGYfHa8qagSB63yL5b!soDdXVN$BDW1gJe;YsQ(} zL~EiMPl+0u#K^xA%5glp_b=JeVzdUCy5BlP&rJ5;90%!ClwQ2j`^JgU`O{t5%(%UQW=SLw85&iEEFK~VVQMz!W0_ZVAUUh@rsLGii^ED1k3mY z0n(*NY~dJO0)5GGnH1_`WXb0sL#+-{@;TXh4>V&n0sdYrbP`4}cRJb!KiKnAkiu1B yDm47xOx+pyiOsOz=irNmATvV@thim=l+1PxfI$Pf*ug>Qv5Cw)&8q}-*Zct;2vv9h delta 1173 zcmZ9KUr3Wt7{+#FXLba+oFrQs90tc6b+>dF9Iox@TShucE0m<_kGXzJJ0*P&v&M#E2pL_ zldh^=t%1M}|IWa^sU2VHT2#iPtJ7E-OogFHcNUxAvO=i?L zPJ%!aX$5ocF`Y&j*pyX;uus8YbHP+5FzmYtc*pxdAWZ425ubCR3QPHggndq22-h|W zA(5`f4X1|1Sw<*`XZkeZad$K$=T@+K@P^L#uM8it2b`EYe_Ta)CBX|Xg@CqLjZw_x zA==_C;wxcGlbkz<&#vxOgK&>+iL72bMo+F)Ym6S>elMIck)Biy)?Gj0mWLV9FMfH{ ztzE4vv!n*G#awtOyU`$KrjGT4g4buxiEaI4AB*4oG$SBC$+M^{`THU&XB_zC`KqyO zr( zz)Y1YvwuZrP4KZoNU4$o4%6>8@JfCh3)aDeDp7`AQC|s*MlZV{u4zW0Tix(m8pm?c zP7jz&V%+#QCmry@yc&QvN+YfCS*nY>AK3#%$(>7G?XYAPR=jxH(+zU-oNCw)6VgFe zD}8$q79@K72IMf%|q!5cg|8Ywp@t}!HNRh>+Xum*ksS2E5cFEro%uGe hal default - May 9, 2017 1:10:34 AM - 1494281434127 + May 17, 2017 10:57:24 PM + 1495051044048 ./ settings.bsp ../../sys.sopcinfo @@ -935,44 +935,50 @@ - pio_5 + pio_6 0x00821080 - 0x0082108F 16 - pio_4 + pio_5 0x00821090 - 0x0082109F 16 - pio_3 + pio_4 0x008210A0 - 0x008210AF 16 - pio_2 + pio_3 0x008210B0 - 0x008210BF 16 - pio_1 + pio_2 0x008210C0 - 0x008210CF 16 - pio_0 + pio_1 0x008210D0 - 0x008210DF 16 + + pio_0 + 0x008210E0 - 0x008210EF + 16 + + jtag_uart_0 - 0x008210E0 - 0x008210E7 + 0x008210F0 - 0x008210F7 8 printable diff --git a/software/sys_controller_bsp/system.h b/software/sys_controller_bsp/system.h index 6330ba0..8b5a1fd 100644 --- a/software/sys_controller_bsp/system.h +++ b/software/sys_controller_bsp/system.h @@ -4,7 +4,7 @@ * Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys' * SOPC Builder design path: ../../sys.sopcinfo * - * Generated: Sat Jan 21 12:40:58 EET 2017 + * Generated: Tue May 16 19:45:17 EEST 2017 */ /* @@ -175,19 +175,19 @@ #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_STDERR "/dev/jtag_uart_0" -#define ALT_STDERR_BASE 0x8210e0 +#define ALT_STDERR_BASE 0x8210f0 #define ALT_STDERR_DEV jtag_uart_0 #define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_PRESENT #define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN "/dev/jtag_uart_0" -#define ALT_STDIN_BASE 0x8210e0 +#define ALT_STDIN_BASE 0x8210f0 #define ALT_STDIN_DEV jtag_uart_0 #define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_PRESENT #define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDOUT "/dev/jtag_uart_0" -#define ALT_STDOUT_BASE 0x8210e0 +#define ALT_STDOUT_BASE 0x8210f0 #define ALT_STDOUT_DEV jtag_uart_0 #define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_PRESENT @@ -279,7 +279,7 @@ */ #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart -#define JTAG_UART_0_BASE 0x8210e0 +#define JTAG_UART_0_BASE 0x8210f0 #define JTAG_UART_0_IRQ 1 #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_0_NAME "/dev/jtag_uart_0" @@ -326,7 +326,7 @@ */ #define ALT_MODULE_CLASS_pio_0 altera_avalon_pio -#define PIO_0_BASE 0x8210d0 +#define PIO_0_BASE 0x8210e0 #define PIO_0_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_0_CAPTURE 0 @@ -353,7 +353,7 @@ */ #define ALT_MODULE_CLASS_pio_1 altera_avalon_pio -#define PIO_1_BASE 0x8210c0 +#define PIO_1_BASE 0x8210d0 #define PIO_1_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_1_CAPTURE 0 @@ -380,7 +380,7 @@ */ #define ALT_MODULE_CLASS_pio_2 altera_avalon_pio -#define PIO_2_BASE 0x8210b0 +#define PIO_2_BASE 0x8210c0 #define PIO_2_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_2_CAPTURE 0 @@ -389,8 +389,8 @@ #define PIO_2_DRIVEN_SIM_VALUE 0 #define PIO_2_EDGE_TYPE "NONE" #define PIO_2_FREQ 27000000 -#define PIO_2_HAS_IN 0 -#define PIO_2_HAS_OUT 1 +#define PIO_2_HAS_IN 1 +#define PIO_2_HAS_OUT 0 #define PIO_2_HAS_TRI 0 #define PIO_2_IRQ -1 #define PIO_2_IRQ_INTERRUPT_CONTROLLER_ID -1 @@ -407,7 +407,7 @@ */ #define ALT_MODULE_CLASS_pio_3 altera_avalon_pio -#define PIO_3_BASE 0x8210a0 +#define PIO_3_BASE 0x8210b0 #define PIO_3_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_3_CAPTURE 0 @@ -434,7 +434,7 @@ */ #define ALT_MODULE_CLASS_pio_4 altera_avalon_pio -#define PIO_4_BASE 0x821090 +#define PIO_4_BASE 0x8210a0 #define PIO_4_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_4_CAPTURE 0 @@ -443,8 +443,8 @@ #define PIO_4_DRIVEN_SIM_VALUE 0 #define PIO_4_EDGE_TYPE "NONE" #define PIO_4_FREQ 27000000 -#define PIO_4_HAS_IN 1 -#define PIO_4_HAS_OUT 0 +#define PIO_4_HAS_IN 0 +#define PIO_4_HAS_OUT 1 #define PIO_4_HAS_TRI 0 #define PIO_4_IRQ -1 #define PIO_4_IRQ_INTERRUPT_CONTROLLER_ID -1 @@ -461,7 +461,7 @@ */ #define ALT_MODULE_CLASS_pio_5 altera_avalon_pio -#define PIO_5_BASE 0x821080 +#define PIO_5_BASE 0x821090 #define PIO_5_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_5_CAPTURE 0 @@ -482,6 +482,33 @@ #define PIO_5_TYPE "altera_avalon_pio" +/* + * pio_6 configuration + * + */ + +#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio +#define PIO_6_BASE 0x821080 +#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_6_CAPTURE 0 +#define PIO_6_DATA_WIDTH 32 +#define PIO_6_DO_TEST_BENCH_WIRING 0 +#define PIO_6_DRIVEN_SIM_VALUE 0 +#define PIO_6_EDGE_TYPE "NONE" +#define PIO_6_FREQ 27000000 +#define PIO_6_HAS_IN 0 +#define PIO_6_HAS_OUT 1 +#define PIO_6_HAS_TRI 0 +#define PIO_6_IRQ -1 +#define PIO_6_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_6_IRQ_TYPE "NONE" +#define PIO_6_NAME "/dev/pio_6" +#define PIO_6_RESET_VALUE 0 +#define PIO_6_SPAN 16 +#define PIO_6_TYPE "altera_avalon_pio" + + /* * timer_0 configuration * diff --git a/sys.qsys b/sys.qsys index 2e62c28..0f4c594 100644 --- a/sys.qsys +++ b/sys.qsys @@ -85,7 +85,7 @@ { datum baseAddress { - value = "8524000"; + value = "8524016"; type = "String"; } } @@ -157,7 +157,7 @@ { datum baseAddress { - value = "8523984"; + value = "8524000"; type = "String"; } } @@ -173,7 +173,7 @@ { datum baseAddress { - value = "8523968"; + value = "8523984"; type = "String"; } } @@ -189,7 +189,7 @@ { datum baseAddress { - value = "8523952"; + value = "8523968"; type = "String"; } } @@ -205,7 +205,7 @@ { datum baseAddress { - value = "8523936"; + value = "8523952"; type = "String"; } } @@ -221,7 +221,7 @@ { datum baseAddress { - value = "8523920"; + value = "8523936"; type = "String"; } } @@ -234,6 +234,22 @@ } } element pio_5.s1 + { + datum baseAddress + { + value = "8523920"; + type = "String"; + } + } + element pio_6 + { + datum _sortIndex + { + value = "17"; + type = "int"; + } + } + element pio_6.s1 { datum baseAddress { @@ -300,25 +316,30 @@ type="conduit" dir="end" /> + @@ -408,7 +429,7 @@ - ]]> + ]]> @@ -643,7 +664,7 @@ - + @@ -671,7 +692,7 @@ - + @@ -694,6 +715,20 @@ + + + + + + + + + + + + + + @@ -712,7 +747,7 @@ start="nios2_qsys_0.data_master" end="jtag_uart_0.avalon_jtag_slave"> - + - + - + - + - + - + + + + + + @@ -859,6 +903,7 @@ + + - + java.lang.Integer - 1494281170 + 1495139511 false true false @@ -384,6 +384,12 @@ parameters are a RESULT of the module parameters. --> clk pio_5.clk + + false + pio_6 + clk + pio_6.clk + false onchip_memory2_0 @@ -5438,7 +5444,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -6109,7 +6115,7 @@ parameters are a RESULT of the module parameters. --> jtag_uart_0 avalon_jtag_slave jtag_uart_0.avalon_jtag_slave - 8524000 + 8524016 8 @@ -6165,7 +6171,7 @@ parameters are a RESULT of the module parameters. --> pio_0 s1 pio_0.s1 - 8523984 + 8524000 16 @@ -6173,7 +6179,7 @@ parameters are a RESULT of the module parameters. --> pio_1 s1 pio_1.s1 - 8523968 + 8523984 16 @@ -6181,7 +6187,7 @@ parameters are a RESULT of the module parameters. --> pio_2 s1 pio_2.s1 - 8523952 + 8523968 16 @@ -6189,7 +6195,7 @@ parameters are a RESULT of the module parameters. --> pio_3 s1 pio_3.s1 - 8523936 + 8523952 16 @@ -6197,7 +6203,7 @@ parameters are a RESULT of the module parameters. --> pio_4 s1 pio_4.s1 - 8523920 + 8523936 16 @@ -6213,6 +6219,14 @@ parameters are a RESULT of the module parameters. --> pio_5 s1 pio_5.s1 + 8523920 + 16 + + + false + pio_6 + s1 + pio_6.s1 8523904 16 @@ -9978,11 +9992,11 @@ the requested settings for a module instance. --> embeddedsw.CMacro.HAS_IN - 0 + 1 embeddedsw.CMacro.HAS_OUT - 1 + 0 embeddedsw.CMacro.HAS_TRI @@ -10032,7 +10046,7 @@ the requested settings for a module instance. --> boolean false false - true + false true true @@ -10040,13 +10054,13 @@ the requested settings for a module instance. --> boolean false false - false + true true true java.lang.String - Output + Input false true true @@ -10064,7 +10078,7 @@ the requested settings for a module instance. --> boolean false false - false + true true true @@ -10080,7 +10094,7 @@ the requested settings for a module instance. --> long 0 false - true + false true true @@ -10088,7 +10102,7 @@ the requested settings for a module instance. --> boolean false false - false + true true true @@ -10128,7 +10142,7 @@ the requested settings for a module instance. --> boolean - true + false true true false @@ -10136,7 +10150,7 @@ the requested settings for a module instance. --> boolean - false + true true true false @@ -10644,24 +10658,6 @@ parameters are a RESULT of the module parameters. --> 2 address - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - readdata Output @@ -10708,8 +10704,8 @@ parameters are a RESULT of the module parameters. --> conduit false - out_port - Output + in_port + Input 32 export @@ -11526,11 +11522,11 @@ the requested settings for a module instance. --> embeddedsw.CMacro.HAS_IN - 1 + 0 embeddedsw.CMacro.HAS_OUT - 0 + 1 embeddedsw.CMacro.HAS_TRI @@ -11580,7 +11576,7 @@ the requested settings for a module instance. --> boolean false false - false + true true true @@ -11588,13 +11584,13 @@ the requested settings for a module instance. --> boolean false false - true + false true true java.lang.String - Input + Output false true true @@ -11612,7 +11608,7 @@ the requested settings for a module instance. --> boolean false false - true + false true true @@ -11628,7 +11624,7 @@ the requested settings for a module instance. --> long 0 false - false + true true true @@ -11636,7 +11632,7 @@ the requested settings for a module instance. --> boolean false false - true + false true true @@ -11676,7 +11672,7 @@ the requested settings for a module instance. --> boolean - false + true true true false @@ -11684,7 +11680,7 @@ the requested settings for a module instance. --> boolean - true + false true true false @@ -12192,6 +12188,24 @@ parameters are a RESULT of the module parameters. --> 2 address + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + readdata Output @@ -12238,8 +12252,8 @@ parameters are a RESULT of the module parameters. --> conduit false - in_port - Input + out_port + Output 32 export @@ -12976,6 +12990,780 @@ parameters are a RESULT of the module parameters. --> + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 32 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 32 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 27000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + embeddedsw.dts.group + gpio + + + embeddedsw.dts.name + pio + + + embeddedsw.dts.params.altr,gpio-bank-width + 32 + + + embeddedsw.dts.params.resetvalue + 0 + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 32 + false + true + true + true + + + long + 27000000 + false + true + false + true + CLOCK_RATE + clk + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 27000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + java.lang.String @@ -13817,7 +14605,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210e0 + 0x008210f0 false true true @@ -14174,7 +14962,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210d0 + 0x008210e0 false true true @@ -14225,7 +15013,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210c0 + 0x008210d0 false true true @@ -14276,7 +15064,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210b0 + 0x008210c0 false true true @@ -14327,7 +15115,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x008210a0 + 0x008210b0 false true true @@ -14378,7 +15166,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821090 + 0x008210a0 false true true @@ -14480,7 +15268,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00821080 + 0x00821090 false true true @@ -14515,6 +15303,57 @@ parameters are a RESULT of the module parameters. --> pio_5 s1 + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00821080 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_qsys_0 + data_master + pio_6 + s1 + pio_5 clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk + pio_6 + clk + pio_5 reset + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk_reset + pio_6 + reset + 16.1 - 13 + 14 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -15752,7 +16645,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 13 + 14 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -15760,7 +16653,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 14 + 15 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -15784,7 +16677,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 8 + 9 conduit_end com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -15880,7 +16773,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 6 + 7 altera_avalon_pio com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule @@ -15896,7 +16789,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 16 + 17 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -15904,7 +16797,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 13 + 14 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -15928,7 +16821,7 @@ parameters are a RESULT of the module parameters. --> 16.1 - 13 + 14 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection