From 94c0526265c0f786054a822e42ac77490ac932b8 Mon Sep 17 00:00:00 2001 From: marqs Date: Mon, 13 Feb 2023 18:55:14 +0200 Subject: [PATCH] update project configuration and IP files --- .gitignore | 5 + ip/sc_config/inc/sc_config_regs.h | 89 +++++++---- ip/sc_config/sc_config_hw.tcl | 56 +++---- ip/sc_config/sc_config_sw.tcl | 2 +- ip/sc_config/sc_config_top.sv | 190 +++++++++--------------- ossc.qsf | 238 +----------------------------- rtl/linebuf.qip | 2 - rtl/linebuf.v | 40 +++-- rtl/pll_2x.ppf | 1 - rtl/pll_2x.qip | 2 - rtl/pll_2x.v | 61 +++----- software/ossc_sw.project | 7 +- software/sys_controller/Makefile | 122 +++++++-------- 13 files changed, 273 insertions(+), 542 deletions(-) diff --git a/.gitignore b/.gitignore index d7a3c2d..d181a4d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,8 @@ +*_bb.v +*_inst.v +*.ppf +*.qws +greybox_tmp .DS_Store software/sys_controller/.cproject software/sys_controller/.force_relink diff --git a/ip/sc_config/inc/sc_config_regs.h b/ip/sc_config/inc/sc_config_regs.h index c56096e..3275beb 100644 --- a/ip/sc_config/inc/sc_config_regs.h +++ b/ip/sc_config/inc/sc_config_regs.h @@ -1,5 +1,5 @@ // -// Copyright (C) 2015-2022 Markus Hiienkari +// Copyright (C) 2015-2019 Markus Hiienkari // // This file is part of Open Source Scan Converter project. // @@ -25,24 +25,21 @@ // bit-fields coded as little-endian typedef union { struct { - uint16_t vmax:11; + uint16_t vtotal:11; uint8_t interlace_flag:1; - uint8_t sc_rsv2:4; - uint8_t fpga_vsyncgen:2; - uint16_t vmax_tvp:11; - uint8_t sc_rsv:2; - uint8_t vsync_flag:1; + uint8_t sync_active:1; + uint32_t fe_rsv:19; } __attribute__((packed, __may_alias__)); uint32_t data; -} sc_status_reg; +} fe_status_reg; typedef union { struct { uint32_t pcnt_frame:20; - uint16_t sc_rsv:12; + uint16_t fe_rsv:12; } __attribute__((packed, __may_alias__)); uint32_t data; -} sc_status2_reg; +} fe_status2_reg; typedef union { struct { @@ -84,54 +81,86 @@ typedef union { uint32_t data; } hv_config3_reg; +typedef union { + struct { + uint16_t x_size:12; + uint16_t y_size:11; + int16_t y_offset:9; + } __attribute__((packed, __may_alias__)); + uint32_t data; +} xy_config_reg; + +typedef union { + struct { + int16_t x_offset:10; + uint8_t x_start_lb:8; + int8_t y_start_lb:6; + int8_t x_rpt:4; + int8_t y_rpt:4; + } __attribute__((packed, __may_alias__)); + uint32_t data; +} xy_config2_reg; + typedef union { struct { uint8_t mask_br:4; uint8_t mask_color:3; - uint8_t rev_lpf_str:5; - uint8_t panasonic_hack:1; - /* temp */ - uint8_t h_l3_240x360:1; - uint16_t h_opt_startoff:10; - //uint8_t h_l5fmt:1; - uint8_t h_multmode:2; - uint8_t v_multmode:3; - uint8_t h_opt_scale:3; + uint8_t reverse_lpf:5; + uint8_t lm_deint_mode:1; + uint8_t nir_even_offset:1; + uint8_t ypbpr_cs:1; + uint8_t vip_enable:1; + uint8_t bfi_str:4; + uint8_t bfi_enable:1; + uint32_t misc_rsv:11; } __attribute__((packed, __may_alias__)); uint32_t data; } misc_config_reg; typedef union { struct { - uint32_t sl_l_str_arr:20; - uint8_t sl_l_overlay:5; - uint8_t sl_hybr_str:5; + uint32_t sl_l_str_arr:24; + uint8_t sl_l_overlay:6; uint8_t sl_method:1; - uint8_t sl_no_altern:1; + uint8_t sl_altern:1; } __attribute__((packed, __may_alias__)); uint32_t data; } sl_config_reg; typedef union { struct { - uint32_t sl_c_str_arr:24; - uint8_t sl_c_overlay:6; - uint8_t sl_rsv:1; - uint8_t sl_altiv:1; + uint32_t sl_c_str_arr_l; } __attribute__((packed, __may_alias__)); uint32_t data; } sl_config2_reg; +typedef union { + struct { + uint32_t sl_c_str_arr_h:8; + uint32_t sl_c_overlay:10; + uint8_t sl_iv_y:3; + uint8_t sl_iv_x:4; + uint32_t sl_rsv:7; + } __attribute__((packed, __may_alias__)); + uint32_t data; +} sl_config3_reg; + typedef struct { - sc_status_reg sc_status; - sc_status2_reg sc_status2; + fe_status_reg fe_status; + fe_status2_reg fe_status2; lt_status_reg lt_status; hv_config_reg hv_in_config; hv_config2_reg hv_in_config2; hv_config3_reg hv_in_config3; + hv_config_reg hv_out_config; + hv_config2_reg hv_out_config2; + hv_config3_reg hv_out_config3; + xy_config_reg xy_out_config; + xy_config2_reg xy_out_config2; misc_config_reg misc_config; sl_config_reg sl_config; sl_config2_reg sl_config2; -} __attribute__((packed, __may_alias__)) sc_regs; + sl_config3_reg sl_config3; +} sc_regs; #endif //SC_CONFIG_REGS_H_ diff --git a/ip/sc_config/sc_config_hw.tcl b/ip/sc_config/sc_config_hw.tcl index 1542e77..d07c21c 100644 --- a/ip/sc_config/sc_config_hw.tcl +++ b/ip/sc_config/sc_config_hw.tcl @@ -1,11 +1,11 @@ -# +# # request TCL package from ACDS 16.1 -# +# package require -exact qsys 16.1 -# +# # module -# +# set_module_property DESCRIPTION "Scanconverter config" set_module_property NAME sc_config #set_module_property VERSION 18.0 @@ -20,9 +20,9 @@ set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false -# +# # file sets -# +# add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL sc_config_top set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false @@ -35,19 +35,19 @@ set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false set_fileset_property SIM_VERILOG TOP_LEVEL sc_config_top add_fileset_file sc_config_top.sv VERILOG PATH sc_config_top.sv -# +# # parameters -# +# -# +# # display items -# +# -# +# # connection point clock_sink -# +# add_interface clock_sink clock end set_interface_property clock_sink clockRate 0 set_interface_property clock_sink ENABLED true @@ -59,9 +59,9 @@ set_interface_property clock_sink SVD_ADDRESS_GROUP "" add_interface_port clock_sink clk_i clk Input 1 -# +# # connection point reset_sink -# +# add_interface reset_sink reset end set_interface_property reset_sink associatedClock clock_sink set_interface_property reset_sink synchronousEdges DEASSERT @@ -74,9 +74,9 @@ set_interface_property reset_sink SVD_ADDRESS_GROUP "" add_interface_port reset_sink rst_i reset Input 1 -# +# # connection point avalon_s -# +# add_interface avalon_s avalon end set_interface_property avalon_s addressUnits WORDS set_interface_property avalon_s associatedClock clock_sink @@ -114,9 +114,9 @@ set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0 -# +# # connection point bus -# +# #add_sv_interface bus sc_if # Setting the parameter property to add SV interface parameters @@ -131,9 +131,9 @@ set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0 #add_fileset_file sc_if.sv SYSTEM_VERILOG PATH sc_if.sv SYSTEMVERILOG_INTERFACE -# +# # connection point sc_if -# +# add_interface sc_if conduit end set_interface_property sc_if associatedClock "" set_interface_property sc_if associatedReset "" @@ -143,12 +143,18 @@ set_interface_property sc_if PORT_NAME_MAP "" set_interface_property sc_if CMSIS_SVD_VARIABLES "" set_interface_property sc_if SVD_ADDRESS_GROUP "" -add_interface_port sc_if sc_status_i sc_status_i Input 32 -add_interface_port sc_if sc_status2_i sc_status2_i Input 32 +add_interface_port sc_if fe_status_i fe_status_i Input 32 +add_interface_port sc_if fe_status2_i fe_status2_i Input 32 add_interface_port sc_if lt_status_i lt_status_i Input 32 -add_interface_port sc_if h_config_o h_config_o Output 32 -add_interface_port sc_if h_config2_o h_config2_o Output 32 -add_interface_port sc_if v_config_o v_config_o Output 32 +add_interface_port sc_if hv_in_config_o hv_in_config_o Output 32 +add_interface_port sc_if hv_in_config2_o hv_in_config2_o Output 32 +add_interface_port sc_if hv_in_config3_o hv_in_config3_o Output 32 +add_interface_port sc_if hv_out_config_o hv_out_config_o Output 32 +add_interface_port sc_if hv_out_config2_o hv_out_config2_o Output 32 +add_interface_port sc_if hv_out_config3_o hv_out_config3_o Output 32 +add_interface_port sc_if xy_out_config_o xy_out_config_o Output 32 +add_interface_port sc_if xy_out_config2_o xy_out_config2_o Output 32 add_interface_port sc_if misc_config_o misc_config_o Output 32 add_interface_port sc_if sl_config_o sl_config_o Output 32 add_interface_port sc_if sl_config2_o sl_config2_o Output 32 +add_interface_port sc_if sl_config3_o sl_config3_o Output 32 diff --git a/ip/sc_config/sc_config_sw.tcl b/ip/sc_config/sc_config_sw.tcl index 5fe295b..f73f70a 100644 --- a/ip/sc_config/sc_config_sw.tcl +++ b/ip/sc_config/sc_config_sw.tcl @@ -18,7 +18,7 @@ set_sw_property version 1.0 # # Multiple-Version compatibility was introduced in version 7.1; # prior versions are therefore excluded. -set_sw_property min_compatible_hw_version 7.1 +set_sw_property min_compatible_hw_version 1.0 # Initialize the driver in alt_sys_init() set_sw_property auto_initialize false diff --git a/ip/sc_config/sc_config_top.sv b/ip/sc_config/sc_config_top.sv index 1e55635..386dcb8 100644 --- a/ip/sc_config/sc_config_top.sv +++ b/ip/sc_config/sc_config_top.sv @@ -23,7 +23,7 @@ module sc_config_top( input rst_i, // avalon slave input [31:0] avalon_s_writedata, - output [31:0] avalon_s_readdata, + output reg [31:0] avalon_s_readdata, input [3:0] avalon_s_address, input [3:0] avalon_s_byteenable, input avalon_s_write, @@ -31,144 +31,73 @@ module sc_config_top( input avalon_s_chipselect, output avalon_s_waitrequest_n, // SC interface - input [31:0] sc_status_i, - input [31:0] sc_status2_i, + input [31:0] fe_status_i, + input [31:0] fe_status2_i, input [31:0] lt_status_i, - output reg [31:0] h_config_o, - output reg [31:0] h_config2_o, - output reg [31:0] v_config_o, - output reg [31:0] misc_config_o, - output reg [31:0] sl_config_o, - output reg [31:0] sl_config2_o + output [31:0] hv_in_config_o, + output [31:0] hv_in_config2_o, + output [31:0] hv_in_config3_o, + output [31:0] hv_out_config_o, + output [31:0] hv_out_config2_o, + output [31:0] hv_out_config3_o, + output [31:0] xy_out_config_o, + output [31:0] xy_out_config2_o, + output [31:0] misc_config_o, + output [31:0] sl_config_o, + output [31:0] sl_config2_o, + output [31:0] sl_config3_o ); -localparam SC_STATUS_REGNUM = 4'h0; -localparam SC_STATUS2_REGNUM = 4'h1; -localparam LT_STATUS_REGNUM = 4'h2; -localparam H_CONFIG_REGNUM = 4'h3; -localparam H_CONFIG2_REGNUM = 4'h4; -localparam V_CONFIG_REGNUM = 4'h5; -localparam MISC_CONFIG_REGNUM = 4'h6; -localparam SL_CONFIG_REGNUM = 4'h7; -localparam SL_CONFIG2_REGNUM = 4'h8; +localparam FE_STATUS_REGNUM = 4'h0; +localparam FE_STATUS2_REGNUM = 4'h1; +localparam LT_STATUS_REGNUM = 4'h2; +localparam HV_IN_CONFIG_REGNUM = 4'h3; +localparam HV_IN_CONFIG2_REGNUM = 4'h4; +localparam HV_IN_CONFIG3_REGNUM = 4'h5; +localparam HV_OUT_CONFIG_REGNUM = 4'h6; +localparam HV_OUT_CONFIG2_REGNUM = 4'h7; +localparam HV_OUT_CONFIG3_REGNUM = 4'h8; +localparam XY_OUT_CONFIG_REGNUM = 4'h9; +localparam XY_OUT_CONFIG2_REGNUM = 4'ha; +localparam MISC_CONFIG_REGNUM = 4'hb; +localparam SL_CONFIG_REGNUM = 4'hc; +localparam SL_CONFIG2_REGNUM = 4'hd; +localparam SL_CONFIG3_REGNUM = 4'he; +reg [31:0] config_reg[HV_IN_CONFIG_REGNUM:SL_CONFIG3_REGNUM] /* synthesis ramstyle = "logic" */; assign avalon_s_waitrequest_n = 1'b1; -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - h_config_o <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==H_CONFIG_REGNUM)) begin - if (avalon_s_byteenable[3]) - h_config_o[31:24] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - h_config_o[23:16] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - h_config_o[15:8] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - h_config_o[7:0] <= avalon_s_writedata[7:0]; +genvar i; +generate + for (i=HV_IN_CONFIG_REGNUM; i <= SL_CONFIG3_REGNUM; i++) begin : gen_reg + always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + config_reg[i] <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==i)) begin + if (avalon_s_byteenable[3]) + config_reg[i][31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + config_reg[i][23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + config_reg[i][15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + config_reg[i][7:0] <= avalon_s_writedata[7:0]; + end + end end end -end +endgenerate -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - h_config2_o <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==H_CONFIG2_REGNUM)) begin - if (avalon_s_byteenable[3]) - h_config2_o[31:24] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - h_config2_o[23:16] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - h_config2_o[15:8] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - h_config2_o[7:0] <= avalon_s_writedata[7:0]; - end - end -end - -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - v_config_o <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==V_CONFIG_REGNUM)) begin - if (avalon_s_byteenable[3]) - v_config_o[31:24] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - v_config_o[23:16] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - v_config_o[15:8] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - v_config_o[7:0] <= avalon_s_writedata[7:0]; - end - end -end - -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - misc_config_o <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==MISC_CONFIG_REGNUM)) begin - if (avalon_s_byteenable[3]) - misc_config_o[31:24] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - misc_config_o[23:16] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - misc_config_o[15:8] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - misc_config_o[7:0] <= avalon_s_writedata[7:0]; - end - end -end - -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - sl_config_o <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==SL_CONFIG_REGNUM)) begin - if (avalon_s_byteenable[3]) - sl_config_o[31:24] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - sl_config_o[23:16] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - sl_config_o[15:8] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - sl_config_o[7:0] <= avalon_s_writedata[7:0]; - end - end -end - -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - sl_config2_o <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==SL_CONFIG2_REGNUM)) begin - if (avalon_s_byteenable[3]) - sl_config2_o[31:24] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - sl_config2_o[23:16] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - sl_config2_o[15:8] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - sl_config2_o[7:0] <= avalon_s_writedata[7:0]; - end - end -end +// no readback for config regs -> unused bits optimized out always @(*) begin if (avalon_s_chipselect && avalon_s_read) begin case (avalon_s_address) - SC_STATUS_REGNUM: avalon_s_readdata = sc_status_i; - SC_STATUS2_REGNUM: avalon_s_readdata = sc_status2_i; + FE_STATUS_REGNUM: avalon_s_readdata = fe_status_i; + FE_STATUS2_REGNUM: avalon_s_readdata = fe_status2_i; LT_STATUS_REGNUM: avalon_s_readdata = lt_status_i; - H_CONFIG_REGNUM: avalon_s_readdata = h_config_o; - H_CONFIG2_REGNUM: avalon_s_readdata = h_config2_o; - V_CONFIG_REGNUM: avalon_s_readdata = v_config_o; - MISC_CONFIG_REGNUM: avalon_s_readdata = misc_config_o; - SL_CONFIG_REGNUM: avalon_s_readdata = sl_config_o; - SL_CONFIG2_REGNUM: avalon_s_readdata = sl_config2_o; default: avalon_s_readdata = 32'h00000000; endcase end else begin @@ -176,4 +105,17 @@ always @(*) begin end end +assign hv_in_config_o = config_reg[HV_IN_CONFIG_REGNUM]; +assign hv_in_config2_o = config_reg[HV_IN_CONFIG2_REGNUM]; +assign hv_in_config3_o = config_reg[HV_IN_CONFIG3_REGNUM]; +assign hv_out_config_o = config_reg[HV_OUT_CONFIG_REGNUM]; +assign hv_out_config2_o = config_reg[HV_OUT_CONFIG2_REGNUM]; +assign hv_out_config3_o = config_reg[HV_OUT_CONFIG3_REGNUM]; +assign xy_out_config_o = config_reg[XY_OUT_CONFIG_REGNUM]; +assign xy_out_config2_o = config_reg[XY_OUT_CONFIG2_REGNUM]; +assign misc_config_o = config_reg[MISC_CONFIG_REGNUM]; +assign sl_config_o = config_reg[SL_CONFIG_REGNUM]; +assign sl_config2_o = config_reg[SL_CONFIG2_REGNUM]; +assign sl_config3_o = config_reg[SL_CONFIG3_REGNUM]; + endmodule diff --git a/ossc.qsf b/ossc.qsf index dbc3190..062774d 100644 --- a/ossc.qsf +++ b/ossc.qsf @@ -215,7 +215,7 @@ set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_new.stp set_global_assignment -name FITTER_EFFORT "AUTO FIT" @@ -235,6 +235,7 @@ set_global_assignment -name VERILOG_FILE rtl/videogen.v set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v set_global_assignment -name VERILOG_FILE rtl/ossc.v set_global_assignment -name VERILOG_FILE rtl/scanconverter.v +set_global_assignment -name VERILOG_FILE rtl/linebuf_top.v set_global_assignment -name VERILOG_FILE rtl/tvp7002_frontend.v set_global_assignment -name VERILOG_FILE rtl/lat_tester.v set_global_assignment -name QIP_FILE sys/synthesis/sys.qip @@ -251,236 +252,5 @@ set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp set_global_assignment -name QIP_FILE rtl/char_array.qip -set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk27 -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "tvp7002_frontend:u_tvp_frontend|FID_o" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "tvp7002_frontend:u_tvp_frontend|HSYNC_i" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "tvp7002_frontend:u_tvp_frontend|HSYNC_o" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "tvp7002_frontend:u_tvp_frontend|HS_i" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "tvp7002_frontend:u_tvp_frontend|VSYNC_i" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "tvp7002_frontend:u_tvp_frontend|VSYNC_o" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "tvp7002_frontend:u_tvp_frontend|VS_i" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "tvp7002_frontend:u_tvp_frontend|datavalid_o" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "tvp7002_frontend:u_tvp_frontend|frame_change" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "tvp7002_frontend:u_tvp_frontend|hsync_i_pol" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "tvp7002_frontend:u_tvp_frontend|interlace_flag" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "tvp7002_frontend:u_tvp_frontend|meas_fid" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "tvp7002_frontend:u_tvp_frontend|meas_hl_det" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line_stored" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "tvp7002_frontend:u_tvp_frontend|sof_scaler" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "tvp7002_frontend:u_tvp_frontend|vsync_i_pol" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "tvp7002_frontend:u_tvp_frontend|vtotal[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "tvp7002_frontend:u_tvp_frontend|vtotal[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "tvp7002_frontend:u_tvp_frontend|vtotal[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "tvp7002_frontend:u_tvp_frontend|vtotal[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "tvp7002_frontend:u_tvp_frontend|vtotal[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "tvp7002_frontend:u_tvp_frontend|vtotal[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "tvp7002_frontend:u_tvp_frontend|vtotal[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "tvp7002_frontend:u_tvp_frontend|vtotal[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "tvp7002_frontend:u_tvp_frontend|vtotal[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "tvp7002_frontend:u_tvp_frontend|vtotal[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "tvp7002_frontend:u_tvp_frontend|vtotal[9]" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=129" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=129" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "tvp7002_frontend:u_tvp_frontend|HSYNC_i" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "tvp7002_frontend:u_tvp_frontend|VSYNC_i" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "tvp7002_frontend:u_tvp_frontend|hsync_i_pol" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "tvp7002_frontend:u_tvp_frontend|interlace_flag" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "tvp7002_frontend:u_tvp_frontend|meas_fid" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "tvp7002_frontend:u_tvp_frontend|meas_hl_det" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line_stored" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "tvp7002_frontend:u_tvp_frontend|vsync_i_pol" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "tvp7002_frontend:u_tvp_frontend|vtotal[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "tvp7002_frontend:u_tvp_frontend|vtotal[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "tvp7002_frontend:u_tvp_frontend|vtotal[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "tvp7002_frontend:u_tvp_frontend|vtotal[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "tvp7002_frontend:u_tvp_frontend|vtotal[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "tvp7002_frontend:u_tvp_frontend|vtotal[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "tvp7002_frontend:u_tvp_frontend|vtotal[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "tvp7002_frontend:u_tvp_frontend|vtotal[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "tvp7002_frontend:u_tvp_frontend|vtotal[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "tvp7002_frontend:u_tvp_frontend|vtotal[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "tvp7002_frontend:u_tvp_frontend|vtotal[9]" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=42" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=411" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id auto_signaltap_0 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name SLD_FILE db/ossc_new_auto_stripped.stp \ No newline at end of file + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/rtl/linebuf.qip b/rtl/linebuf.qip index b9f1735..17270d7 100644 --- a/rtl/linebuf.qip +++ b/rtl/linebuf.qip @@ -2,5 +2,3 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" set_global_assignment -name IP_TOOL_VERSION "21.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_bb.v"] diff --git a/rtl/linebuf.v b/rtl/linebuf.v index 091c470..19140a9 100644 --- a/rtl/linebuf.v +++ b/rtl/linebuf.v @@ -41,22 +41,28 @@ module linebuf ( data, rdaddress, rdclock, + rdclocken, wraddress, wrclock, + wrclocken, wren, q); input [23:0] data; input [11:0] rdaddress; input rdclock; + input rdclocken; input [11:0] wraddress; input wrclock; + input wrclocken; input wren; output [23:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif + tri1 rdclocken; tri1 wrclock; + tri1 wrclocken; tri0 wren; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on @@ -70,6 +76,8 @@ module linebuf ( .address_b (rdaddress), .clock0 (wrclock), .clock1 (rdclock), + .clocken0 (wrclocken), + .clocken1 (rdclocken), .data_a (data), .wren_a (wren), .q_b (sub_wire0), @@ -79,8 +87,6 @@ module linebuf ( .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .data_b ({24{1'b1}}), @@ -92,9 +98,9 @@ module linebuf ( defparam altsyncram_component.address_aclr_b = "NONE", altsyncram_component.address_reg_b = "CLOCK1", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_input_b = "NORMAL", + altsyncram_component.clock_enable_output_b = "NORMAL", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 4096, @@ -123,10 +129,10 @@ endmodule // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" // Retrieval info: PRIVATE: CLRdata NUMERIC "0" // Retrieval info: PRIVATE: CLRq NUMERIC "0" // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" @@ -172,14 +178,14 @@ endmodule // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "1" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" @@ -197,13 +203,17 @@ endmodule // Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]" // Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL "rdaddress[11..0]" // Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" +// Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken" // Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]" // Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" +// Retrieval info: USED_PORT: wrclocken 0 0 0 0 INPUT VCC "wrclocken" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0 // Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 // Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 wrclocken 0 0 0 0 +// Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0 @@ -211,6 +221,6 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf diff --git a/rtl/pll_2x.ppf b/rtl/pll_2x.ppf index 3d83c85..bcd48b7 100644 --- a/rtl/pll_2x.ppf +++ b/rtl/pll_2x.ppf @@ -12,7 +12,6 @@ - diff --git a/rtl/pll_2x.qip b/rtl/pll_2x.qip index a9995dc..d047ad4 100644 --- a/rtl/pll_2x.qip +++ b/rtl/pll_2x.qip @@ -2,6 +2,4 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_VERSION "21.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"] diff --git a/rtl/pll_2x.v b/rtl/pll_2x.v index ad71f6b..2f50912 100644 --- a/rtl/pll_2x.v +++ b/rtl/pll_2x.v @@ -9,7 +9,7 @@ // altpll // // Simulation Library Files(s): -// +// altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -48,7 +48,6 @@ module pll_2x ( scandata, activeclock, c0, - c1, locked, scandataout, scandone); @@ -63,7 +62,6 @@ module pll_2x ( input scandata; output activeclock; output c0; - output c1; output locked; output scandataout; output scandone; @@ -81,34 +79,32 @@ module pll_2x ( wire sub_wire0; wire [4:0] sub_wire1; + wire sub_wire3; wire sub_wire4; wire sub_wire5; - wire sub_wire6; - wire sub_wire9 = inclk1; + wire sub_wire8 = inclk1; wire activeclock = sub_wire0; - wire [1:1] sub_wire3 = sub_wire1[1:1]; wire [0:0] sub_wire2 = sub_wire1[0:0]; wire c0 = sub_wire2; - wire c1 = sub_wire3; - wire locked = sub_wire4; - wire scandataout = sub_wire5; - wire scandone = sub_wire6; - wire sub_wire7 = inclk0; - wire [1:0] sub_wire8 = {sub_wire9, sub_wire7}; + wire locked = sub_wire3; + wire scandataout = sub_wire4; + wire scandone = sub_wire5; + wire sub_wire6 = inclk0; + wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; altpll altpll_component ( .areset (areset), .clkswitch (clkswitch), .configupdate (configupdate), - .inclk (sub_wire8), + .inclk (sub_wire7), .scanclk (scanclk), .scanclkena (scanclkena), .scandata (scandata), .activeclock (sub_wire0), .clk (sub_wire1), - .locked (sub_wire4), - .scandataout (sub_wire5), - .scandone (sub_wire6), + .locked (sub_wire3), + .scandataout (sub_wire4), + .scandone (sub_wire5), .clkbad (), .clkena ({6{1'b1}}), .clkloss (), @@ -140,10 +136,6 @@ module pll_2x ( altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 1, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 1, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 1, - altpll_component.clk1_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.inclk1_input_frequency = 37037, @@ -178,7 +170,7 @@ module pll_2x ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", @@ -227,11 +219,8 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "27.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -252,26 +241,18 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -294,14 +275,11 @@ endmodule // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -310,10 +288,6 @@ endmodule // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "37037" @@ -347,7 +321,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" @@ -371,7 +345,6 @@ endmodule // Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock" // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch" // Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" @@ -392,7 +365,6 @@ endmodule // Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 // Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 // Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 @@ -401,8 +373,9 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE +// Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/software/ossc_sw.project b/software/ossc_sw.project index 4d1d241..087a3ca 100644 --- a/software/ossc_sw.project +++ b/software/ossc_sw.project @@ -33,7 +33,7 @@ - /home/markus/Code/ossc/software + ./ @@ -61,9 +61,7 @@ - - @@ -89,6 +87,9 @@ + + + diff --git a/software/sys_controller/Makefile b/software/sys_controller/Makefile index ed6950c..55f33ab 100644 --- a/software/sys_controller/Makefile +++ b/software/sys_controller/Makefile @@ -38,13 +38,13 @@ ALT_LDFLAGS := #------------------------------------------------------------------------------ # The adjust-path macro -# +# # If COMSPEC/ComSpec is defined, Make is launched from Windows through # Cygwin. The adjust-path macro converts absolute windows paths into # unix style paths (Example: c:/dir -> /c/dir). This will ensture # paths are readable by GNU Make. # -# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no # adjustment is necessary # #------------------------------------------------------------------------------ @@ -57,7 +57,7 @@ endif # COMSPEC ifdef COMSPEC # if Windows OS -ifeq ($(MAKE_VERSION),3.81) +ifeq ($(MAKE_VERSION),3.81) # # adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows # @@ -69,10 +69,10 @@ ifeq ($(MAKE_VERSION),3.81) # # adjust-path -# - converts back slash characters into forward slashes +# - converts back slash characters into forward slashes # - if input arg ($1) is an empty string then return the empty string # - if input arg ($1) does not contain the string ":/", then return input arg -# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] define adjust-path $(strip \ $(if $1,\ @@ -83,13 +83,13 @@ endef # # adjust-path-mixed -# - converts back slash characters into forward slashes +# - converts back slash characters into forward slashes # - if input arg ($1) is an empty string then return the empty string -# - if input arg ($1) does not begin with a forward slash '/' char, then +# - if input arg ($1) does not begin with a forward slash '/' char, then # return input arg -# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] -# into a mixed path [c:/...] -define adjust-path-mixed +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed $(strip \ $(if $1,\ $(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ @@ -97,7 +97,7 @@ $(subst \,/,$1),\ $(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,')))) endef -else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) # # adjust-path for Cygwin Gnu Make # $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb @@ -123,22 +123,22 @@ endif # COMSPEC ACTIVE_BUILD_CONFIG := default BUILD_CONFIGS := default -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. # TYPE: APP_MAKEFILE -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. # ACDS_VERSION: 14.1 ACDS_VERSION := 14.1 -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. # BUILD_NUMBER: 190 -# Define path to the application ELF. -# It may be used by the makefile fragments so is defined before including them. -# +# Define path to the application ELF. +# It may be used by the makefile fragments so is defined before including them. +# ELF := sys_controller.elf # Paths to C, C++, and assembly source files. @@ -149,7 +149,6 @@ C_SRCS += it6613/it6613.c C_SRCS += it6613/it6613_drv.c C_SRCS += it6613/it6613_sys.c C_SRCS += tvp7002/tvp7002.c -C_SRCS += tvp7002/video_modes.c C_SRCS += ths7353/ths7353.c C_SRCS += pcm1862/pcm1862.c C_SRCS += spi_charlcd/lcd.c @@ -171,6 +170,7 @@ else C_SRCS += ossc/userdata.c endif C_SRCS += ossc/utils.c +C_SRCS += ossc/video_modes.c C_SRCS += ulibSD/sd_io.c C_SRCS += ulibSD/spi_io.c CXX_SRCS := @@ -257,7 +257,7 @@ endif all: @$(ECHO) [$(APP_NAME) build complete] -all : build_pre_process libs app build_post_process +all : build_pre_process libs app build_post_process #------------------------------------------------------------------------------ @@ -283,25 +283,25 @@ ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) include $(BSP_INCLUDE_FILE) -# C2H will need this to touch the BSP public.mk and avoid the sopc file +# C2H will need this to touch the BSP public.mk and avoid the sopc file # out-of-date error during a BSP make ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk ifneq ($(WARNING.SMALL_STACK_SIZE),) # This WARNING is here to protect you from unknowingly using a very small stack -# If the warning is set, increase your stack size or enable the BSP small stack +# If the warning is set, increase your stack size or enable the BSP small stack # setting to eliminate the warning $(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) endif -# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF -# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) endif -# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to # download_elf target ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) GMON_OUT_FILENAME := gmon.out @@ -434,22 +434,22 @@ ifeq ($(CREATE_LINKER_MAP), 1) APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) endif -# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the -# mem_init_install target of the mem_init.mk (located in the associated BSP) -# to know how to copy memory initialization files (e.g. .dat, .hex) into +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into # directories required for Quartus compilation or RTL simulation. -# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory -# initialization files into your Quartus project directory. This is required -# to provide the initial memory contents of FPGA memories that can be -# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used # for VHDL simulation of on-chip memories. -# Defining SOPC_NAME causes the mem_init_install target to copy memory -# initialization files into your RTL simulation directory. This is required -# to provide the initial memory contents of all memories that can be -# initialized by RTL simulation. This variable should be set to the same name -# as your SOPC Builder system name. For example, if you have a system called +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called # "foo.sopc", this variable should be set to "foo". # If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. @@ -459,23 +459,23 @@ SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) endif endif -# Defining JDI_FILE is required to specify the JTAG Debug Information File -# path. This file is generated by Quartus, and is needed along with the -# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU -# systems. For multi-CPU systems, the processor instance ID is used to select +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select # from multiple CPU's during ELF download. -# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during -# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then -# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be -# multiple .sopcinfo files in a Quartus project. +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. ifeq ($(JDI_FILE),) ifneq ($(QUARTUS_PROJECT_DIR),) JDI_FILE := $(firstword $(wildcard $(QUARTUS_PROJECT_DIR)/output_files/*.jdi) $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi)) endif endif -# Path to root runtime directory used for hdl simulation +# Path to root runtime directory used for hdl simulation RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime @@ -523,7 +523,7 @@ SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ # Relative-pathed objects that being with "../" are handled differently. # -# Regular objects are created as +# Regular objects are created as # $(CONFIG_OBJ_DIR)//.o # where the path structure is maintained under the obj directory. This # applies for both absolute and relative paths; in the absolute path @@ -531,16 +531,16 @@ SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ # directory. This is done to allow two source files with the same name # to be included as part of the project. # -# Note: On Cygwin, the path recreated under the obj directory will be +# Note: On Cygwin, the path recreated under the obj directory will be # the cygpath -u output path. # -# Relative-path objects that begin with "../" cause problems under this +# Relative-path objects that begin with "../" cause problems under this # scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object # files anywhere in the system, creating clutter and polluting the source tree. -# As such, their paths are flattened - the object file created will be -# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with -# "../" in the beginning cannot have the same name in the project. VPATH -# will be set for these sources to allow make to relocate the source file +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file # via %.o rules. # # The following lines separate the object list into the flatten and regular @@ -628,7 +628,7 @@ ifneq ($(wildcard $(SOPCINFO_FILE)),) ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) endif -# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. # This is not needed if you only have one cable. ifneq ($(DOWNLOAD_CABLE),) DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' @@ -793,7 +793,7 @@ $(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< $(AS_POST_PROCESS) endef -ifeq ($(MAKE_VERSION),3.81) +ifeq ($(MAKE_VERSION),3.81) .SECONDEXPANSION: $(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) @@ -891,7 +891,7 @@ help : @$(ECHO) " all (default) - Application and all libraries (including BSP)" @$(ECHO) " bsp - Just the BSP" @$(ECHO) " libs - All libraries (including BSP)" - @$(ECHO) " flash - All flash files" + @$(ECHO) " flash - All flash files" @$(ECHO) " mem_init_generate - All memory initialization files" ifeq ($(QSYS),1) @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" @@ -952,7 +952,7 @@ $(APP_LDDEPS): libs endif # Rules to force your project to rebuild or relink -# .force_relink file will cause any application that depends on this project to relink +# .force_relink file will cause any application that depends on this project to relink # .force_rebuild file will cause this project to rebuild object files # .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files @@ -1019,9 +1019,9 @@ download-elf : $(ELF) else \ $(ECHO) Info: Downloading $(ELF); \ $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ - fi + fi -# Delete the target of a rule if it has changed and its commands exit +# Delete the target of a rule if it has changed and its commands exit # with a nonzero exit status. .DELETE_ON_ERROR: