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optimize away one pp stage and unify code formatting

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marqs
2018-03-12 01:24:17 +02:00
parent 77d122940b
commit 9ad696dbc3
8 changed files with 1304 additions and 1299 deletions
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software/sys_controller/mem_init/sys_onchip_memory2_0.hex
+1159 -1159
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software/sys_controller/ossc/av_controller.c
+2 -2
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@@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@@ -777,7 +777,7 @@ int main()
printf("### DIY VIDEO DIGITIZER / SCANCONVERTER INIT OK ###\n\n");
sniprintf(row1, LCD_ROW_LEN+1, "OSSC fw. %u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
#ifndef DEBUG
strncpy(row2, "2014-2017 marqs", LCD_ROW_LEN+1);
strncpy(row2, "2014-2018 marqs", LCD_ROW_LEN+1);
#else
strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
#endif
software/sys_controller/ossc/avconfig.h
+2 -2
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@@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@@ -51,7 +51,7 @@
typedef struct {
alt_u8 sl_mode;
alt_u8 sl_type;
alt_u8 sl_hybr_str;
alt_u8 sl_hybr_str;
alt_u8 sl_method;
alt_u8 sl_str;
alt_u8 sl_id;
software/sys_controller_bsp/settings.bsp
+2 -2
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@@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Mar 6, 2018 11:46:21 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1520372781076</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Mar 12, 2018 12:02:20 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1520805740902</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>