diff --git a/ip/sc_config/inc/sc_config_regs.h b/ip/sc_config/inc/sc_config_regs.h new file mode 100644 index 0000000..aa5ceed --- /dev/null +++ b/ip/sc_config/inc/sc_config_regs.h @@ -0,0 +1,135 @@ +// +// Copyright (C) 2015-2019 Markus Hiienkari +// +// This file is part of Open Source Scan Converter project. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef SC_CONFIG_REGS_H_ +#define SC_CONFIG_REGS_H_ + +#include + +// bit-fields coded as little-endian +typedef union { + struct { + alt_u16 vmax:11; + alt_u8 interlace_flag:1; + alt_u8 sc_rsv2:4; + alt_u8 fpga_vsyncgen:2; + alt_u16 vmax_tvp:11; + alt_u8 sc_rsv:2; + alt_u8 vsync_flag:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sc_status_reg; + +typedef union { + struct { + alt_u32 pcnt_frame:20; + alt_u16 sc_rsv:12; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sc_status2_reg; + +typedef union { + struct { + alt_u16 lt_lat_result:16; + alt_u16 lt_stb_result:12; + alt_u8 lt_rsv:3; + alt_u8 lt_finished:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} lt_status_reg; + +typedef union { + struct { + alt_u16 h_active:11; + alt_u16 h_backporch:9; + alt_u8 h_synclen:8; + alt_u8 h_l3_240x360:1; + alt_u8 h_l5fmt:1; + alt_u8 h_multmode:2; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} h_config_reg; + +typedef union { + struct { + alt_u16 h_opt_startoff:10; + alt_u8 h_opt_sample_mult:3; + alt_u8 h_opt_sample_sel:3; + alt_u8 h_opt_scale:3; + alt_u16 h_mask:11; + alt_u8 h_rsv:2; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} h_config2_reg; + +typedef union { + struct { + alt_u16 v_active:11; + alt_u8 v_backporch:6; + alt_u8 v_synclen:3; + alt_u8 v_mask:6; + alt_u8 v_rsv:3; + alt_u8 v_multmode:3; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} v_config_reg; + +typedef union { + struct { + alt_u8 mask_br:4; + alt_u8 rev_lpf_str:5; + alt_u32 misc_rsv:23; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} misc_config_reg; + +typedef union { + struct { + alt_u32 sl_l_str_arr:20; + alt_u8 sl_l_overlay:5; + alt_u8 sl_hybr_str:5; + alt_u8 sl_method:1; + alt_u8 sl_no_altern:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sl_config_reg; + +typedef union { + struct { + alt_u32 sl_c_str_arr:24; + alt_u8 sl_c_overlay:6; + alt_u8 sl_rsv:1; + alt_u8 sl_altiv:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sl_config2_reg; + +typedef struct { + sc_status_reg sc_status; + sc_status2_reg sc_status2; + lt_status_reg lt_status; + h_config_reg h_config; + h_config2_reg h_config2; + v_config_reg v_config; + misc_config_reg misc_config; + sl_config_reg sl_config; + sl_config2_reg sl_config2; +} __attribute__((packed, __may_alias__)) sc_regs; + +#endif //SC_CONFIG_REGS_H_ diff --git a/ip/sc_config/sc_config_hw.tcl b/ip/sc_config/sc_config_hw.tcl new file mode 100644 index 0000000..1542e77 --- /dev/null +++ b/ip/sc_config/sc_config_hw.tcl @@ -0,0 +1,154 @@ +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + +# +# module +# +set_module_property DESCRIPTION "Scanconverter config" +set_module_property NAME sc_config +#set_module_property VERSION 18.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP "Interface Protocols" +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME sc_config +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL sc_config_top +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file sc_config_top.sv VERILOG PATH sc_config_top.sv + +add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false +set_fileset_property SIM_VERILOG TOP_LEVEL sc_config_top +add_fileset_file sc_config_top.sv VERILOG PATH sc_config_top.sv + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock_sink +# +add_interface clock_sink clock end +set_interface_property clock_sink clockRate 0 +set_interface_property clock_sink ENABLED true +set_interface_property clock_sink EXPORT_OF "" +set_interface_property clock_sink PORT_NAME_MAP "" +set_interface_property clock_sink CMSIS_SVD_VARIABLES "" +set_interface_property clock_sink SVD_ADDRESS_GROUP "" + +add_interface_port clock_sink clk_i clk Input 1 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock_sink +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst_i reset Input 1 + + +# +# connection point avalon_s +# +add_interface avalon_s avalon end +set_interface_property avalon_s addressUnits WORDS +set_interface_property avalon_s associatedClock clock_sink +set_interface_property avalon_s associatedReset reset_sink +set_interface_property avalon_s bitsPerSymbol 8 +set_interface_property avalon_s burstOnBurstBoundariesOnly false +set_interface_property avalon_s burstcountUnits WORDS +set_interface_property avalon_s explicitAddressSpan 0 +set_interface_property avalon_s holdTime 0 +set_interface_property avalon_s linewrapBursts false +set_interface_property avalon_s maximumPendingReadTransactions 0 +set_interface_property avalon_s maximumPendingWriteTransactions 0 +set_interface_property avalon_s readLatency 0 +set_interface_property avalon_s readWaitTime 1 +set_interface_property avalon_s setupTime 0 +set_interface_property avalon_s timingUnits Cycles +set_interface_property avalon_s writeWaitTime 0 +set_interface_property avalon_s ENABLED true +set_interface_property avalon_s EXPORT_OF "" +set_interface_property avalon_s PORT_NAME_MAP "" +set_interface_property avalon_s CMSIS_SVD_VARIABLES "" +set_interface_property avalon_s SVD_ADDRESS_GROUP "" + +add_interface_port avalon_s avalon_s_address address Input 4 +add_interface_port avalon_s avalon_s_writedata writedata Input 32 +add_interface_port avalon_s avalon_s_readdata readdata Output 32 +add_interface_port avalon_s avalon_s_byteenable byteenable Input 4 +add_interface_port avalon_s avalon_s_write write Input 1 +add_interface_port avalon_s avalon_s_read read Input 1 +add_interface_port avalon_s avalon_s_chipselect chipselect Input 1 +add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1 +set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point bus +# +#add_sv_interface bus sc_if + +# Setting the parameter property to add SV interface parameters +#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus + +# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus +#set_port_property p2 SV_INTERFACE_PORT bus +#set_port_property p1 SV_INTERFACE_SIGNAL bus +#set_port_property p2 SV_INTERFACE_SIGNAL bus + +#Adding the SV Interface File +#add_fileset_file sc_if.sv SYSTEM_VERILOG PATH sc_if.sv SYSTEMVERILOG_INTERFACE + + +# +# connection point sc_if +# +add_interface sc_if conduit end +set_interface_property sc_if associatedClock "" +set_interface_property sc_if associatedReset "" +set_interface_property sc_if ENABLED true +set_interface_property sc_if EXPORT_OF "" +set_interface_property sc_if PORT_NAME_MAP "" +set_interface_property sc_if CMSIS_SVD_VARIABLES "" +set_interface_property sc_if SVD_ADDRESS_GROUP "" + +add_interface_port sc_if sc_status_i sc_status_i Input 32 +add_interface_port sc_if sc_status2_i sc_status2_i Input 32 +add_interface_port sc_if lt_status_i lt_status_i Input 32 +add_interface_port sc_if h_config_o h_config_o Output 32 +add_interface_port sc_if h_config2_o h_config2_o Output 32 +add_interface_port sc_if v_config_o v_config_o Output 32 +add_interface_port sc_if misc_config_o misc_config_o Output 32 +add_interface_port sc_if sl_config_o sl_config_o Output 32 +add_interface_port sc_if sl_config2_o sl_config2_o Output 32 diff --git a/ip/sc_config/sc_config_sw.tcl b/ip/sc_config/sc_config_sw.tcl new file mode 100644 index 0000000..5fe295b --- /dev/null +++ b/ip/sc_config/sc_config_sw.tcl @@ -0,0 +1,54 @@ +# +# opencores_i2c_sw.tcl +# + +# Create a new driver +create_driver sc_config_driver + +# Associate it with some hardware known as "opencores_i2c" +set_sw_property hw_class_name sc_config + +# The version of this driver +set_sw_property version 1.0 + +# This driver may be incompatible with versions of hardware less +# than specified below. Updates to hardware and device drivers +# rendering the driver incompatible with older versions of +# hardware are noted with this property assignment. +# +# Multiple-Version compatibility was introduced in version 7.1; +# prior versions are therefore excluded. +set_sw_property min_compatible_hw_version 7.1 + +# Initialize the driver in alt_sys_init() +set_sw_property auto_initialize false + +# Location in generated BSP that above sources will be copied into +set_sw_property bsp_subdirectory drivers + + +# Interrupt properties: +# This peripheral has an IRQ output but the driver doesn't currently +# have any interrupt service routine. To ensure that the BSP tools +# do not otherwise limit the BSP functionality for users of the +# Nios II enhanced interrupt port, these settings advertise +# compliance with both legacy and enhanced interrupt APIs, and to state +# that any driver ISR supports preemption. If an interrupt handler +# is added to this driver, these must be re-examined for validity. +set_sw_property isr_preemption_supported true +set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api" + +# +# Source file listings... +# + +# C/C++ source files + +# Include files +add_sw_property include_source inc/sc_config_regs.h + +# This driver supports HAL & UCOSII BSP (OS) types +add_sw_property supported_bsp_type HAL +add_sw_property supported_bsp_type UCOSII + +# End of file diff --git a/ip/sc_config/sc_config_top.sv b/ip/sc_config/sc_config_top.sv new file mode 100644 index 0000000..1e55635 --- /dev/null +++ b/ip/sc_config/sc_config_top.sv @@ -0,0 +1,179 @@ +// +// Copyright (C) 2015-2019 Markus Hiienkari +// +// This file is part of Open Source Scan Converter project. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sc_config_top( + // common + input clk_i, + input rst_i, + // avalon slave + input [31:0] avalon_s_writedata, + output [31:0] avalon_s_readdata, + input [3:0] avalon_s_address, + input [3:0] avalon_s_byteenable, + input avalon_s_write, + input avalon_s_read, + input avalon_s_chipselect, + output avalon_s_waitrequest_n, + // SC interface + input [31:0] sc_status_i, + input [31:0] sc_status2_i, + input [31:0] lt_status_i, + output reg [31:0] h_config_o, + output reg [31:0] h_config2_o, + output reg [31:0] v_config_o, + output reg [31:0] misc_config_o, + output reg [31:0] sl_config_o, + output reg [31:0] sl_config2_o +); + +localparam SC_STATUS_REGNUM = 4'h0; +localparam SC_STATUS2_REGNUM = 4'h1; +localparam LT_STATUS_REGNUM = 4'h2; +localparam H_CONFIG_REGNUM = 4'h3; +localparam H_CONFIG2_REGNUM = 4'h4; +localparam V_CONFIG_REGNUM = 4'h5; +localparam MISC_CONFIG_REGNUM = 4'h6; +localparam SL_CONFIG_REGNUM = 4'h7; +localparam SL_CONFIG2_REGNUM = 4'h8; + + +assign avalon_s_waitrequest_n = 1'b1; + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + h_config_o <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==H_CONFIG_REGNUM)) begin + if (avalon_s_byteenable[3]) + h_config_o[31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + h_config_o[23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + h_config_o[15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + h_config_o[7:0] <= avalon_s_writedata[7:0]; + end + end +end + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + h_config2_o <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==H_CONFIG2_REGNUM)) begin + if (avalon_s_byteenable[3]) + h_config2_o[31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + h_config2_o[23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + h_config2_o[15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + h_config2_o[7:0] <= avalon_s_writedata[7:0]; + end + end +end + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + v_config_o <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==V_CONFIG_REGNUM)) begin + if (avalon_s_byteenable[3]) + v_config_o[31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + v_config_o[23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + v_config_o[15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + v_config_o[7:0] <= avalon_s_writedata[7:0]; + end + end +end + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + misc_config_o <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==MISC_CONFIG_REGNUM)) begin + if (avalon_s_byteenable[3]) + misc_config_o[31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + misc_config_o[23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + misc_config_o[15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + misc_config_o[7:0] <= avalon_s_writedata[7:0]; + end + end +end + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + sl_config_o <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==SL_CONFIG_REGNUM)) begin + if (avalon_s_byteenable[3]) + sl_config_o[31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + sl_config_o[23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + sl_config_o[15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + sl_config_o[7:0] <= avalon_s_writedata[7:0]; + end + end +end + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + sl_config2_o <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==SL_CONFIG2_REGNUM)) begin + if (avalon_s_byteenable[3]) + sl_config2_o[31:24] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + sl_config2_o[23:16] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + sl_config2_o[15:8] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + sl_config2_o[7:0] <= avalon_s_writedata[7:0]; + end + end +end + +always @(*) begin + if (avalon_s_chipselect && avalon_s_read) begin + case (avalon_s_address) + SC_STATUS_REGNUM: avalon_s_readdata = sc_status_i; + SC_STATUS2_REGNUM: avalon_s_readdata = sc_status2_i; + LT_STATUS_REGNUM: avalon_s_readdata = lt_status_i; + H_CONFIG_REGNUM: avalon_s_readdata = h_config_o; + H_CONFIG2_REGNUM: avalon_s_readdata = h_config2_o; + V_CONFIG_REGNUM: avalon_s_readdata = v_config_o; + MISC_CONFIG_REGNUM: avalon_s_readdata = misc_config_o; + SL_CONFIG_REGNUM: avalon_s_readdata = sl_config_o; + SL_CONFIG2_REGNUM: avalon_s_readdata = sl_config2_o; + default: avalon_s_readdata = 32'h00000000; + endcase + end else begin + avalon_s_readdata = 32'h00000000; + end +end + +endmodule diff --git a/ossc.sdc b/ossc.sdc index 38c6773..51373b2 100644 --- a/ossc.sdc +++ b/ossc.sdc @@ -73,7 +73,7 @@ set_clock_groups -asynchronous -group \ {pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out} # Ignore paths from registers which are updated only at leading edge of vsync -set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|LT_POS_* scanconverter_inst|FID_1x}] +set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_* scanconverter_inst|FID_1x}] # Ignore paths from registers which are updated only at leading edge of hsync set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}] diff --git a/rtl/lat_tester_includes.v b/rtl/lat_tester_includes.v index f614331..c0a4915 100644 --- a/rtl/lat_tester_includes.v +++ b/rtl/lat_tester_includes.v @@ -22,5 +22,5 @@ `define LT_POS_CENTER 2'b10 `define LT_POS_BOTTOMRIGHT 2'b11 -`define LT_WIDTH_DIV 8 -`define LT_HEIGHT_DIV 8 +`define LT_WIDTH_DIV 4'h8 +`define LT_HEIGHT_DIV 4'h8 diff --git a/rtl/ossc.v b/rtl/ossc.v index 3d5e61a..ccc2ed0 100644 --- a/rtl/ossc.v +++ b/rtl/ossc.v @@ -1,5 +1,5 @@ // -// Copyright (C) 2015-2018 Markus Hiienkari +// Copyright (C) 2015-2019 Markus Hiienkari // // This file is part of Open Source Scan Converter project. // @@ -59,10 +59,10 @@ wire [15:0] sys_ctrl; wire h_unstable; wire [1:0] pclk_lock; wire [1:0] pll_lock_lost; -wire [31:0] h_info, h_info2, v_info, extra_info; +wire [31:0] h_config, h_config2, v_config, misc_config, sl_config, sl_config2; wire [10:0] vmax, vmax_tvp; wire [1:0] fpga_vsyncgen; -wire ilace_flag; +wire ilace_flag, vsync_flag; wire [19:0] pcnt_frame; wire [15:0] ir_code; @@ -242,13 +242,15 @@ sys sys_inst( .i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]), .pio_0_sys_ctrl_out_export (sys_ctrl), .pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}), - .pio_2_status_in_export ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}), - .pio_3_h_info_out_export (h_info), - .pio_4_h_info2_out_export (h_info2), - .pio_5_v_info_out_export (v_info), - .pio_6_extra_info_out_export (extra_info), - .pio_7_lt_results_in_export ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}), - .pio_8_pcnt_vhz_in_export ({12'h000, pcnt_frame}) + .sc_config_0_sc_if_sc_status_i ({vsync_flag, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}), + .sc_config_0_sc_if_sc_status2_i ({12'h000, pcnt_frame}), + .sc_config_0_sc_if_lt_status_i ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}), + .sc_config_0_sc_if_h_config_o (h_config), + .sc_config_0_sc_if_h_config2_o (h_config2), + .sc_config_0_sc_if_v_config_o (v_config), + .sc_config_0_sc_if_misc_config_o (misc_config), + .sc_config_0_sc_if_sl_config_o (sl_config), + .sc_config_0_sc_if_sl_config2_o (sl_config2) ); scanconverter scanconverter_inst ( @@ -261,10 +263,12 @@ scanconverter scanconverter_inst ( .R_in (R_in_L), .G_in (G_in_L), .B_in (B_in_L), - .h_info (h_info), - .h_info2 (h_info2), - .v_info (v_info), - .extra_info (extra_info), + .h_config (h_config), + .h_config2 (h_config2), + .v_config (v_config), + .misc_config (misc_config), + .sl_config (sl_config), + .sl_config2 (sl_config2), .R_out (R_out), .G_out (G_out), .B_out (B_out), @@ -280,6 +284,7 @@ scanconverter scanconverter_inst ( .vmax_tvp (vmax_tvp), .pcnt_frame (pcnt_frame), .ilace_flag (ilace_flag), + .vsync_flag (vsync_flag), .lt_active (lt_active), .lt_mode (lt_mode_synced) ); diff --git a/rtl/scanconverter.v b/rtl/scanconverter.v index b6f4e59..20d0ac0 100644 --- a/rtl/scanconverter.v +++ b/rtl/scanconverter.v @@ -1,5 +1,5 @@ // -// Copyright (C) 2015-2018 Markus Hiienkari +// Copyright (C) 2015-2019 Markus Hiienkari // // This file is part of Open Source Scan Converter project. // @@ -44,11 +44,6 @@ `define H_MULTMODE_OPTIMIZED 2'h2 `define H_MULTMODE_OPTIMIZED_1X 2'h3 -`define SCANLINES_OFF 2'h0 -`define SCANLINES_H 2'h1 -`define SCANLINES_V 2'h2 -`define SCANLINES_ALT 2'h3 - `define SCANLINES_HYBR_CONTR_LOW 2'h1 `define SCANLINES_HYBR_CONTR_MED 2'h2 `define SCANLINES_HYBR_CONTR_HIGH 2'h3 @@ -87,10 +82,12 @@ module scanconverter ( input HSYNC_in, input PCLK_in, input clk27, - input [31:0] h_info, - input [31:0] h_info2, - input [31:0] v_info, - input [31:0] extra_info, + input [31:0] h_config, + input [31:0] h_config2, + input [31:0] v_config, + input [31:0] misc_config, + input [31:0] sl_config, + input [31:0] sl_config2, output reg [7:0] R_out, output reg [7:0] G_out, output reg [7:0] B_out, @@ -106,6 +103,7 @@ module scanconverter ( output reg [10:0] vmax_tvp, output reg [19:0] pcnt_frame, output ilace_flag, + output vsync_flag, input lt_active, input [1:0] lt_mode ); @@ -157,7 +155,8 @@ reg [11:0] hcnt_pp /* synthesis ramstyle = "logic" */; reg [10:0] vcnt_pp /* synthesis ramstyle = "logic" */; reg rlpf_trigger_r[1:`PP_RLPF_PL_START-1] /* synthesis ramstyle = "logic" */; reg [7:0] R_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1], G_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1], B_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1] /* synthesis ramstyle = "logic" */; -reg [2:0] line_id_pp[1:`PP_SLGEN_PL_END-2], col_id_pp[1:`PP_SLGEN_PL_END-2] /* synthesis ramstyle = "logic" */; +reg [2:0] line_id_pp[1:`PP_SLGEN_PL_END-5], col_id_pp[1:`PP_SLGEN_PL_END-5] /* synthesis ramstyle = "logic" */; +reg draw_sl_pp[`PP_SLGEN_PL_END-4:`PP_SLGEN_PL_END-1] /* synthesis ramstyle = "logic" */; reg border_enable_pp[2:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */; reg lt_box_enable_pp[2:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */; @@ -177,8 +176,6 @@ reg [10:0] V_ACTIVE; //max. 2047 reg [6:0] V_AVIDSTART; //max. 127 reg [7:0] H_SYNCLEN; reg [2:0] V_SYNCLEN; -reg [1:0] V_SCANLINEMODE; -reg [4:0] V_SCANLINEID; reg [5:0] V_MASK; reg [2:0] V_MULTMODE; reg [1:0] H_MULTMODE; @@ -191,10 +188,15 @@ reg [9:0] H_L5BORDER; reg [9:0] H_L3BORDER; reg [6:0] H_L3_OPT_SAMPLE_COMP; reg [3:0] X_MASK_BR; -reg X_SCANLINE_METHOD; -reg [4:0] X_SCANLINE_HYBRSTR; -reg [7:0] X_SCANLINESTR; reg [5:0] X_REV_LPF_STR; +reg [3:0] SL_L_STR[4:0] /* synthesis ramstyle = "logic" */; +reg [3:0] SL_C_STR[5:0] /* synthesis ramstyle = "logic" */; +reg [4:0] SL_HYBRSTR; +reg [4:0] SL_L_OVERLAY; +reg [5:0] SL_C_OVERLAY; +reg SL_METHOD; +reg SL_NO_ALTERN; +reg SL_ALTIV; reg X_REV_LPF_ENABLE; // constants for each frame to be calculated off config-registers @@ -237,28 +239,28 @@ lpm_mult_4_hybr_ref_pre Y_sl_hybr_ref_pre_u ( .clock(pclk_act), .dataa(Y[9:2]), - .datab(X_SCANLINE_HYBRSTR), + .datab(SL_HYBRSTR), .result(Y_sl_hybr_ref_pre) ); lpm_mult_4_hybr_ref_pre R_sl_hybr_ref_pre_u ( .clock(pclk_act), .dataa(R_pp[`PP_RLPF_PL_END]), - .datab(X_SCANLINE_HYBRSTR), + .datab(SL_HYBRSTR), .result(R_sl_hybr_ref_pre) ); lpm_mult_4_hybr_ref_pre G_sl_hybr_ref_pre_u ( .clock(pclk_act), .dataa(G_pp[`PP_RLPF_PL_END]), - .datab(X_SCANLINE_HYBRSTR), + .datab(SL_HYBRSTR), .result(G_sl_hybr_ref_pre) ); lpm_mult_4_hybr_ref_pre B_sl_hybr_ref_pre_u ( .clock(pclk_act), .dataa(B_pp[`PP_RLPF_PL_END]), - .datab(X_SCANLINE_HYBRSTR), + .datab(SL_HYBRSTR), .result(B_sl_hybr_ref_pre) ); @@ -267,32 +269,32 @@ lpm_mult_4_hybr_ref Y_sl_hybr_ref_u ( .clock(pclk_act), .dataa(Y_sl_hybr_ref_pre), - .datab(X_SCANLINESTR), + .datab(sl_str_tmp), .result(Y_sl_hybr_ref) ); lpm_mult_4_hybr_ref R_sl_hybr_ref_u ( .clock(pclk_act), .dataa(R_sl_hybr_ref_pre), - .datab(X_SCANLINESTR), + .datab(sl_str_tmp), .result(R_sl_hybr_ref) ); lpm_mult_4_hybr_ref G_sl_hybr_ref_u ( .clock(pclk_act), .dataa(G_sl_hybr_ref_pre), - .datab(X_SCANLINESTR), + .datab(sl_str_tmp), .result(G_sl_hybr_ref) ); lpm_mult_4_hybr_ref B_sl_hybr_ref_u ( .clock(pclk_act), .dataa(B_sl_hybr_ref_pre), - .datab(X_SCANLINESTR), + .datab(sl_str_tmp), .result(B_sl_hybr_ref) ); -reg [7:0] Y_sl_str, R_sl_str, G_sl_str, B_sl_str; +reg [7:0] sl_str, sl_str_tmp, Y_sl_str, R_sl_str, G_sl_str, B_sl_str; reg [7:0] R_sl_sub, G_sl_sub, B_sl_sub; wire [7:0] R_sl_mult, G_sl_mult, B_sl_mult; @@ -318,8 +320,6 @@ lpm_mult_4_sl B_sl_mult_u .result(B_sl_mult) ); -reg draw_sl; - //Reverse LPF wire rlpf_trigger_act; reg signed [14:0] R_diff_s15_pre, G_diff_s15_pre, B_diff_s15_pre, R_diff_s15, G_diff_s15, B_diff_s15; @@ -368,7 +368,7 @@ case (V_MULTMODE) HSYNC_act = HSYNC_2x; VSYNC_act = VSYNC_2x; DE_act = DE_2x; - line_id_act = {1'b0, line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x}; + line_id_act = SL_NO_ALTERN ? {2'b0, {line_out_idx_2x[0]+FID_1x}} : {1'b0, line_out_idx_2x}; hcnt_act = hcnt_2x; vcnt_act = vcnt_2x; case (H_MULTMODE) @@ -432,7 +432,7 @@ case (V_MULTMODE) HSYNC_act = HSYNC_4x; VSYNC_act = VSYNC_4x; DE_act = DE_4x; - line_id_act = {1'b0, line_out_idx_4x}; + line_id_act = SL_NO_ALTERN ? {1'b0, {line_out_idx_4x+{FID_1x, 1'b0}}} : {1'b0, line_out_idx_4x}; hcnt_act = hcnt_4x; vcnt_act = vcnt_4x; pclk_mux_sel = `PCLK_MUX_4X; @@ -535,9 +535,9 @@ mux5 mux5_inst ( integer pp_idx; always @(posedge pclk_act) begin - line_id_pp[1] <= line_id_act; + line_id_pp[1] <= SL_ALTIV ? {2'b00, vcnt_act[0]} : line_id_act; col_id_pp[1] <= col_id_act; - for(pp_idx = 2; pp_idx <= `PP_SLGEN_PL_END-2; pp_idx = pp_idx+1) begin + for(pp_idx = 2; pp_idx <= `PP_SLGEN_PL_END-5; pp_idx = pp_idx+1) begin line_id_pp[pp_idx] <= line_id_pp[pp_idx-1]; col_id_pp[pp_idx] <= col_id_pp[pp_idx-1]; end @@ -647,30 +647,40 @@ begin // modify scanline strength (3 pp-stages) // ... step 1/3 // Y_sl_hybr_ref_tmp, R_sl_hybr_ref_tmp, G_sl_hybr_ref_tmp, B_sl_hybr_ref_tmp are outputs of multiplier IPs (1 pp-stage delay) + if (|(SL_L_OVERLAY & (5'h1< R_sl_str) ? (R_pp[`PP_SLGEN_PL_END-2]-R_sl_str) : 8'h00; G_sl_sub <= (G_pp[`PP_SLGEN_PL_END-2] > G_sl_str) ? (G_pp[`PP_SLGEN_PL_END-2]-G_sl_str) : 8'h00; B_sl_sub <= (B_pp[`PP_SLGEN_PL_END-2] > B_sl_str) ? (B_pp[`PP_SLGEN_PL_END-2]-B_sl_str) : 8'h00; - draw_sl <= |{(V_SCANLINEMODE == `SCANLINES_H) && (V_SCANLINEID & (5'h1<sc_status.vsync_flag) { //printf("ctrval %u\n", ctr); break; } } sync_active = tvp_check_sync(input, format); - vsyncmode = cm.sync_active ? ((IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3) : 0; + vsyncmode = cm.sync_active ? sc->sc_status.fpga_vsyncgen : 0; // Read sync information from TVP7002 status registers data1 = tvp_readreg(TVP_LINECNT1); @@ -221,7 +223,7 @@ status_t get_status(tvp_input_t input, video_format format) clkcnt = ((data2 & 0x0f) << 8) | data1; // Read how many lines TVP7002 outputs in reality (valid only if output enabled) - totlines_tvp = ((IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 18) & 0x7ff)+1; + totlines_tvp = sc->sc_status.vmax_tvp+1; // NOTE: "progressive" may not have correct value if H-PLL is not locked (!cm.sync_active) if ((vsyncmode == 0x2) || (!cm.sync_active && (totlines < MIN_LINES_INTERLACED))) { @@ -290,7 +292,7 @@ status_t get_status(tvp_input_t input, video_format format) if (update_cur_vm) { tvp_setup_hpll(cm.sample_mult*video_modes[cm.id].h_total, clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2)); - status = (status < INFO_CHANGE) ? INFO_CHANGE : status; + status = (status < SC_CONFIG_CHANGE) ? SC_CONFIG_CHANGE : status; } cm.totlines = totlines; @@ -303,17 +305,21 @@ status_t get_status(tvp_input_t input, video_format format) (tc.sl_hybr_str != cm.cc.sl_hybr_str) || (tc.sl_method != cm.cc.sl_method) || (tc.sl_str != cm.cc.sl_str) || + memcmp(tc.sl_cust_l_str, cm.cc.sl_cust_l_str, 5) || + memcmp(tc.sl_cust_c_str, cm.cc.sl_cust_c_str, 6) || + (tc.sl_altern != cm.cc.sl_altern) || + (tc.sl_altiv != cm.cc.sl_altiv) || (tc.sl_id != cm.cc.sl_id) || (tc.h_mask != cm.cc.h_mask) || (tc.v_mask != cm.cc.v_mask) || (tc.mask_br != cm.cc.mask_br) || (tc.ar_256col != cm.cc.ar_256col) || (tc.reverse_lpf != cm.cc.reverse_lpf)) - status = (status < INFO_CHANGE) ? INFO_CHANGE : status; + status = (status < SC_CONFIG_CHANGE) ? SC_CONFIG_CHANGE : status; if (tc.sampler_phase != cm.cc.sampler_phase) { cm.sample_sel = tvp_set_hpll_phase(tc.sampler_phase, cm.sample_mult); - status = (status < INFO_CHANGE) ? INFO_CHANGE : status; + status = (status < SC_CONFIG_CHANGE) ? SC_CONFIG_CHANGE : status; } if (tc.sync_vth != cm.cc.sync_vth) @@ -358,21 +364,19 @@ status_t get_status(tvp_input_t input, video_format format) return status; } -// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0] -// | H_MULTMODE[1:0] | H_L5FMT | H_L3_240x360 | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] | -// -// h_info2: [31:30] [29:19] [18:16] [15:13] [12:10] [9:0] -// | | H_MASK[10:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] | -// -// v_info: [31:29] [28:27] [26] [25:20] [19:17] [16:11] [10:0] -// | V_MULTMODE[2:0] | V_SCANLINEMODE[1:0] | V_SCANLINEID | V_MASK[5:0] | V_SYNCLEN[2:0] | V_BACKPORCH[5:0] | V_ACTIVE[10:0] | -// -// extra: [31:19] [18:14] [13:10] [9] [8:4] [3:0] -// | | X_REV_LPF_STR | H_MASK_BR[3:0] | H_SCANLINE_METHOD | H_SL_HYBRSTR[4:0] | H_SCANLINESTR[3:0] | -// -void set_videoinfo() +void update_sc_config() { - alt_u8 sl_mode_fpga; + h_config_reg h_config = {.data=0x00000000}; + h_config2_reg h_config2 = {.data=0x00000000}; + v_config_reg v_config = {.data=0x00000000}; + misc_config_reg misc_config = {.data=0x00000000}; + sl_config_reg sl_config = {.data=0x00000000}; + sl_config2_reg sl_config2 = {.data=0x00000000}; + + alt_u8 sl_no_altern = 0; + alt_u8 sl_l_overlay = 0, sl_c_overlay = 0; + alt_u32 sl_l_str_arr = 0, sl_c_str_arr = 0; + alt_u8 h_opt_scale = cm.sample_mult; alt_u16 h_opt_startoffs = 0; alt_u16 h_synclen = video_modes[cm.id].h_synclen; @@ -380,17 +384,66 @@ void set_videoinfo() alt_u16 v_active = video_modes[cm.id].v_active; alt_u16 v_backporch = video_modes[cm.id].v_backporch; - if (cm.cc.sl_mode == 2) { //manual - sl_mode_fpga = 1+cm.cc.sl_type; - } else if (cm.cc.sl_mode == 1) { //auto - if (video_modes[cm.id].flags & MODE_INTERLACED) - sl_mode_fpga = cm.fpga_vmultmode ? FPGA_SCANLINEMODE_ALT : FPGA_SCANLINEMODE_OFF; - else if ((cm.fpga_vmultmode) && (video_modes[cm.id].group != GROUP_480P)) - sl_mode_fpga = FPGA_SCANLINEMODE_H; + int i; + + // construct default scanline overlay + if ((cm.cc.sl_type == 0) || (cm.cc.sl_type == 2)) { + if (cm.cc.sl_altiv) { + sl_l_overlay = 1<<(cm.cc.sl_id); + } else { + switch (cm.fpga_vmultmode) { + case FPGA_V_MULTMODE_3X: + sl_l_overlay = 1<<(2*(cm.cc.sl_id)); + break; + case FPGA_V_MULTMODE_4X: + sl_l_overlay = 3<<(2*(cm.cc.sl_id)); + break; + case FPGA_V_MULTMODE_5X: + sl_l_overlay = 3<<(3*(cm.cc.sl_id)); + break; + default: //1x, 2x + sl_l_overlay = 1<<(cm.cc.sl_id); + break; + } + } + } + if ((cm.cc.sl_type == 1) || (cm.cc.sl_type == 2)) { + if (cm.sample_mult <= 4) + sl_c_overlay = (1<<((cm.sample_mult-1)*(cm.cc.sl_id))); else - sl_mode_fpga = FPGA_SCANLINEMODE_OFF; - } else { - sl_mode_fpga = FPGA_SCANLINEMODE_OFF; + sl_c_overlay = (3<<((cm.sample_mult-2)*(cm.cc.sl_id))); + } + // construct custom scanline overlay and strength arrays + for (i=0; i<5; i++) { + if (cm.cc.sl_type == 3) { + sl_l_str_arr |= ((cm.cc.sl_cust_l_str[i]-1)&0xf)<<(4*i); + sl_l_overlay |= (cm.cc.sl_cust_l_str[i]!=0)<h_config = h_config; + sc->h_config2 = h_config2; + sc->v_config = v_config; + sc->misc_config = misc_config; + sc->sl_config = sl_config; + sc->sl_config2 = sl_config2; } // Configure TVP7002 and scan converter logic based on the video mode @@ -522,7 +590,7 @@ void program_mode() set_lpf(cm.cc.video_lpf); cm.sample_sel = tvp_set_hpll_phase(cm.cc.sampler_phase, cm.sample_mult); - set_videoinfo(); + update_sc_config(); TX_SetPixelRepetition(cm.tx_pixelrep, ((cm.cc.tx_mode!=TX_DVI) && (cm.tx_pixelrep == cm.hdmitx_pixr_ifr)) ? 1 : 0); @@ -629,8 +697,8 @@ int init_hw() // Reset hardware IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, AV_RESET_N|LCD_BL); IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x0000); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, 0x00000000); - IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, 0x00000000); + sc->h_config.data = 0x00000000; + sc->v_config.data = 0x00000000; usleep(10000); // unreset hw @@ -705,8 +773,9 @@ int init_hw() } int latency_test() { - alt_u32 lt_status, btn_vec, btn_vec_prev=1; + lt_status_reg lt_status; alt_u16 latency_ms_x100, stb_ms_x100; + alt_u32 btn_vec, btn_vec_prev=1; alt_u8 position = lt_sel+1; sys_ctrl |= LT_ACTIVE|(position<lt_status.lt_finished) {} //Hangs if sync is lost SPI_Timer_On(1000); while ((SPI_Timer_Status()==TRUE)) { - lt_status = IORD_ALTERA_AVALON_PIO_DATA(PIO_7_BASE); - if (lt_status & (1<<31)) + lt_status = sc->lt_status; + if (lt_status.lt_finished) break; } SPI_Timer_Off(); - latency_ms_x100 = lt_status & 0xffff; - stb_ms_x100 = (lt_status >> 16) & 0xfff; + latency_ms_x100 = lt_status.lt_lat_result; + stb_ms_x100 = lt_status.lt_stb_result; + if (latency_ms_x100 == 0) sniprintf(menu_row2, LCD_ROW_LEN+1, "False trigger"); else if (latency_ms_x100 == 0xffff) @@ -1009,10 +1079,10 @@ int main() program_mode(); } break; - case INFO_CHANGE: + case SC_CONFIG_CHANGE: if (cm.sync_active) { - printf("Info change\n"); - set_videoinfo(); + printf("Scanconverter config change\n"); + update_sc_config(); } break; default: diff --git a/software/sys_controller/ossc/av_controller.h b/software/sys_controller/ossc/av_controller.h index ed6b691..85b65e9 100644 --- a/software/sys_controller/ossc/av_controller.h +++ b/software/sys_controller/ossc/av_controller.h @@ -22,6 +22,7 @@ #include "avconfig.h" #include "sysconfig.h" +#include "sc_config_regs.h" // sys_ctrl bits #define LT_ACTIVE (1<<15) @@ -57,11 +58,6 @@ #define FPGA_H_MULTMODE_OPTIMIZED 2 #define FPGA_H_MULTMODE_OPTIMIZED_1X 3 -#define FPGA_SCANLINEMODE_OFF 0 -#define FPGA_SCANLINEMODE_H 1 -#define FPGA_SCANLINEMODE_V 2 -#define FPGA_SCANLINEMODE_ALT 3 - #define AUTO_OFF 0 #define AUTO_CURRENT_INPUT 1 #define AUTO_MAX_COUNT 100 @@ -70,7 +66,7 @@ // In reverse order of importance typedef enum { NO_CHANGE = 0, - INFO_CHANGE = 1, + SC_CONFIG_CHANGE = 1, MODE_CHANGE = 2, TX_MODE_CHANGE = 3, ACTIVITY_CHANGE = 4 diff --git a/software/sys_controller/ossc/avconfig.c b/software/sys_controller/ossc/avconfig.c index 9c16307..8fb24da 100644 --- a/software/sys_controller/ossc/avconfig.c +++ b/software/sys_controller/ossc/avconfig.c @@ -47,6 +47,7 @@ const avconfig_t tc_default = { .sync_lpf = DEFAULT_SYNC_LPF, .pre_coast = DEFAULT_PRE_COAST, .post_coast = DEFAULT_POST_COAST, + .sl_altern = 1, #ifdef ENABLE_AUDIO .audio_dw_sampl = DEFAULT_ON, .tx_mode = TX_HDMI_RGB, diff --git a/software/sys_controller/ossc/avconfig.h b/software/sys_controller/ossc/avconfig.h index 2fd5afc..e15571c 100644 --- a/software/sys_controller/ossc/avconfig.h +++ b/software/sys_controller/ossc/avconfig.h @@ -71,8 +71,12 @@ typedef struct { alt_u8 sl_type; alt_u8 sl_hybr_str; alt_u8 sl_method; + alt_u8 sl_altern; + alt_u8 sl_altiv; alt_u8 sl_str; alt_u8 sl_id; + alt_u8 sl_cust_l_str[5]; + alt_u8 sl_cust_c_str[6]; alt_u8 linemult_target; alt_u8 l2_mode; alt_u8 l3_mode; diff --git a/software/sys_controller/ossc/controls.c b/software/sys_controller/ossc/controls.c index 00e062f..bf5ffeb 100644 --- a/software/sys_controller/ossc/controls.c +++ b/software/sys_controller/ossc/controls.c @@ -45,6 +45,7 @@ extern alt_u8 menu_active; extern alt_u16 sys_ctrl; extern alt_u8 profile_sel, profile_sel_menu; extern alt_u8 lcd_bl_timeout; +extern volatile sc_regs *sc; alt_u32 remote_code; alt_u8 remote_rpt, remote_rpt_prev; @@ -111,9 +112,9 @@ int parse_control() alt_u8 pt_only = 0; avinput_t man_target_input = AV_LAST; - alt_u32 fpga_status; + sc_status_reg sc_status; + sc_status2_reg sc_status2; alt_u32 fpga_v_hz_x100; - alt_u8 fpga_ilace; // one for each video_group alt_u8* pmcfg_ptr[] = { &pt_only, &tc.pm_240p, &tc.pm_384p, &tc.pm_480i, &tc.pm_480p, &tc.pm_480p, &tc.pm_1080i }; @@ -155,8 +156,8 @@ int parse_control() break; case RC_INFO: - fpga_status = IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE); - fpga_ilace = !!(fpga_status & (1<<11)); + sc_status = sc->sc_status; + sc_status2 = sc->sc_status2; sniprintf(menu_row1, LCD_ROW_LEN+1, "Prof.%u %9s", profile_sel, video_modes[cm.id].name); if (cm.sync_active) { //fpga_v_hz_x100 = (100*TVP_EXTCLK_HZ)/IORD_ALTERA_AVALON_PIO_DATA(PIO_8_BASE); @@ -165,10 +166,10 @@ int parse_control() ((fpga_status >> 16) & 0x3) ? '*' : ' ', fpga_v_hz_x100/100, fpga_v_hz_x100%100);*/ - sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %lu", (((fpga_status & 0x7ff)+1)<> 16) & 0x3) ? '*' : ' ', - IORD_ALTERA_AVALON_PIO_DATA(PIO_8_BASE)); + sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %lu", (unsigned long)((sc_status.vmax+1)<", OPT_SUBMENU, { .sub = { &menu_cust_sl, NULL, NULL } } }, +})) + +MENU(menu_postproc, P99_PROTECT({ \ { LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.h_mask, OPT_NOWRAP, 0, H_MASK_MAX, pixels_disp } } }, { LNG("Vertical mask","ｽｲﾁｮｸﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.v_mask, OPT_NOWRAP, 0, V_MASK_MAX, pixels_disp } } }, { LNG("Mask brightness","ﾏｽｸｱｶﾙｻ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.mask_br, OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } }, @@ -164,8 +185,8 @@ MENU(menu_postproc, P99_PROTECT({ \ })) MENU(menu_compatibility, P99_PROTECT({ \ - { LNG("Full TX setup","ﾌﾙTXｾｯﾄｱｯﾌﾟ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.full_tx_setup, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, - { LNG("AV3 interlacefix","AV3ｲﾝﾀｰﾚｰｽｼｭｳｾｲ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.vga_ilace_fix, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, + { LNG("Full TX setup","ﾌﾙTXｾｯﾄｱｯﾌﾟ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.full_tx_setup, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, + { LNG("AV3 interlacefix","AV3ｲﾝﾀｰﾚｰｽｼｭｳｾｲ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.vga_ilace_fix, OPT_WRAP, SETTING_ITEM(off_on_desc) } } }, })) #ifdef ENABLE_AUDIO @@ -203,6 +224,7 @@ MENU(menu_main, P99_PROTECT({ \ { LNG("Sampling opt. >","ｻﾝﾌﾟﾘﾝｸﾞｵﾌﾟｼｮﾝ>"), OPT_SUBMENU, { .sub = { &menu_sampling, NULL, NULL } } }, { LNG("Sync opt. >","ﾄﾞｳｷｵﾌﾟｼｮﾝ >"), OPT_SUBMENU, { .sub = { &menu_sync, NULL, NULL } } }, { LNG("Output opt. >","ｼｭﾂﾘｮｸｵﾌﾟｼｮﾝ >"), OPT_SUBMENU, { .sub = { &menu_output, NULL, NULL } } }, + { LNG("Scanline opt. >","ｽｷｬﾝﾗｲﾝｵﾌﾟｼｮﾝ >"), OPT_SUBMENU, { .sub = { &menu_scanlines, NULL, NULL } } }, { LNG("Post-proc. >","ｱﾄｼｮﾘ >"), OPT_SUBMENU, { .sub = { &menu_postproc, NULL, NULL } } }, { LNG("Compatibility >","ｺﾞｶﾝｾｲ >"), OPT_SUBMENU, { .sub = { &menu_compatibility, NULL, NULL } } }, AUDIO_MENU diff --git a/software/sys_controller_bsp/drivers/inc/sc_config_regs.h b/software/sys_controller_bsp/drivers/inc/sc_config_regs.h new file mode 100644 index 0000000..aa5ceed --- /dev/null +++ b/software/sys_controller_bsp/drivers/inc/sc_config_regs.h @@ -0,0 +1,135 @@ +// +// Copyright (C) 2015-2019 Markus Hiienkari +// +// This file is part of Open Source Scan Converter project. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef SC_CONFIG_REGS_H_ +#define SC_CONFIG_REGS_H_ + +#include + +// bit-fields coded as little-endian +typedef union { + struct { + alt_u16 vmax:11; + alt_u8 interlace_flag:1; + alt_u8 sc_rsv2:4; + alt_u8 fpga_vsyncgen:2; + alt_u16 vmax_tvp:11; + alt_u8 sc_rsv:2; + alt_u8 vsync_flag:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sc_status_reg; + +typedef union { + struct { + alt_u32 pcnt_frame:20; + alt_u16 sc_rsv:12; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sc_status2_reg; + +typedef union { + struct { + alt_u16 lt_lat_result:16; + alt_u16 lt_stb_result:12; + alt_u8 lt_rsv:3; + alt_u8 lt_finished:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} lt_status_reg; + +typedef union { + struct { + alt_u16 h_active:11; + alt_u16 h_backporch:9; + alt_u8 h_synclen:8; + alt_u8 h_l3_240x360:1; + alt_u8 h_l5fmt:1; + alt_u8 h_multmode:2; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} h_config_reg; + +typedef union { + struct { + alt_u16 h_opt_startoff:10; + alt_u8 h_opt_sample_mult:3; + alt_u8 h_opt_sample_sel:3; + alt_u8 h_opt_scale:3; + alt_u16 h_mask:11; + alt_u8 h_rsv:2; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} h_config2_reg; + +typedef union { + struct { + alt_u16 v_active:11; + alt_u8 v_backporch:6; + alt_u8 v_synclen:3; + alt_u8 v_mask:6; + alt_u8 v_rsv:3; + alt_u8 v_multmode:3; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} v_config_reg; + +typedef union { + struct { + alt_u8 mask_br:4; + alt_u8 rev_lpf_str:5; + alt_u32 misc_rsv:23; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} misc_config_reg; + +typedef union { + struct { + alt_u32 sl_l_str_arr:20; + alt_u8 sl_l_overlay:5; + alt_u8 sl_hybr_str:5; + alt_u8 sl_method:1; + alt_u8 sl_no_altern:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sl_config_reg; + +typedef union { + struct { + alt_u32 sl_c_str_arr:24; + alt_u8 sl_c_overlay:6; + alt_u8 sl_rsv:1; + alt_u8 sl_altiv:1; + } __attribute__((packed, __may_alias__)); + alt_u32 data; +} sl_config2_reg; + +typedef struct { + sc_status_reg sc_status; + sc_status2_reg sc_status2; + lt_status_reg lt_status; + h_config_reg h_config; + h_config2_reg h_config2; + v_config_reg v_config; + misc_config_reg misc_config; + sl_config_reg sl_config; + sl_config2_reg sl_config2; +} __attribute__((packed, __may_alias__)) sc_regs; + +#endif //SC_CONFIG_REGS_H_ diff --git a/software/sys_controller_bsp/libhal_bsp.a b/software/sys_controller_bsp/libhal_bsp.a index 7c919f2..6449da9 100644 Binary files a/software/sys_controller_bsp/libhal_bsp.a and b/software/sys_controller_bsp/libhal_bsp.a differ diff --git a/software/sys_controller_bsp/system.h b/software/sys_controller_bsp/system.h index b0d4636..660f1f4 100644 --- a/software/sys_controller_bsp/system.h +++ b/software/sys_controller_bsp/system.h @@ -382,192 +382,13 @@ /* - * pio_2 configuration + * sc_config configuration * */ -#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio -#define PIO_2_BASE 0x210c0 -#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_2_CAPTURE 0 -#define PIO_2_DATA_WIDTH 32 -#define PIO_2_DO_TEST_BENCH_WIRING 0 -#define PIO_2_DRIVEN_SIM_VALUE 0 -#define PIO_2_EDGE_TYPE "NONE" -#define PIO_2_FREQ 27000000 -#define PIO_2_HAS_IN 1 -#define PIO_2_HAS_OUT 0 -#define PIO_2_HAS_TRI 0 -#define PIO_2_IRQ -1 -#define PIO_2_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_2_IRQ_TYPE "NONE" -#define PIO_2_NAME "/dev/pio_2" -#define PIO_2_RESET_VALUE 0 -#define PIO_2_SPAN 16 -#define PIO_2_TYPE "altera_avalon_pio" - - -/* - * pio_3 configuration - * - */ - -#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio -#define PIO_3_BASE 0x210b0 -#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_3_CAPTURE 0 -#define PIO_3_DATA_WIDTH 32 -#define PIO_3_DO_TEST_BENCH_WIRING 0 -#define PIO_3_DRIVEN_SIM_VALUE 0 -#define PIO_3_EDGE_TYPE "NONE" -#define PIO_3_FREQ 27000000 -#define PIO_3_HAS_IN 0 -#define PIO_3_HAS_OUT 1 -#define PIO_3_HAS_TRI 0 -#define PIO_3_IRQ -1 -#define PIO_3_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_3_IRQ_TYPE "NONE" -#define PIO_3_NAME "/dev/pio_3" -#define PIO_3_RESET_VALUE 0 -#define PIO_3_SPAN 16 -#define PIO_3_TYPE "altera_avalon_pio" - - -/* - * pio_4 configuration - * - */ - -#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio -#define PIO_4_BASE 0x210a0 -#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_4_CAPTURE 0 -#define PIO_4_DATA_WIDTH 32 -#define PIO_4_DO_TEST_BENCH_WIRING 0 -#define PIO_4_DRIVEN_SIM_VALUE 0 -#define PIO_4_EDGE_TYPE "NONE" -#define PIO_4_FREQ 27000000 -#define PIO_4_HAS_IN 0 -#define PIO_4_HAS_OUT 1 -#define PIO_4_HAS_TRI 0 -#define PIO_4_IRQ -1 -#define PIO_4_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_4_IRQ_TYPE "NONE" -#define PIO_4_NAME "/dev/pio_4" -#define PIO_4_RESET_VALUE 0 -#define PIO_4_SPAN 16 -#define PIO_4_TYPE "altera_avalon_pio" - - -/* - * pio_5 configuration - * - */ - -#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio -#define PIO_5_BASE 0x21090 -#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_5_CAPTURE 0 -#define PIO_5_DATA_WIDTH 32 -#define PIO_5_DO_TEST_BENCH_WIRING 0 -#define PIO_5_DRIVEN_SIM_VALUE 0 -#define PIO_5_EDGE_TYPE "NONE" -#define PIO_5_FREQ 27000000 -#define PIO_5_HAS_IN 0 -#define PIO_5_HAS_OUT 1 -#define PIO_5_HAS_TRI 0 -#define PIO_5_IRQ -1 -#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_5_IRQ_TYPE "NONE" -#define PIO_5_NAME "/dev/pio_5" -#define PIO_5_RESET_VALUE 0 -#define PIO_5_SPAN 16 -#define PIO_5_TYPE "altera_avalon_pio" - - -/* - * pio_6 configuration - * - */ - -#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio -#define PIO_6_BASE 0x21080 -#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_6_CAPTURE 0 -#define PIO_6_DATA_WIDTH 32 -#define PIO_6_DO_TEST_BENCH_WIRING 0 -#define PIO_6_DRIVEN_SIM_VALUE 0 -#define PIO_6_EDGE_TYPE "NONE" -#define PIO_6_FREQ 27000000 -#define PIO_6_HAS_IN 0 -#define PIO_6_HAS_OUT 1 -#define PIO_6_HAS_TRI 0 -#define PIO_6_IRQ -1 -#define PIO_6_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_6_IRQ_TYPE "NONE" -#define PIO_6_NAME "/dev/pio_6" -#define PIO_6_RESET_VALUE 0 -#define PIO_6_SPAN 16 -#define PIO_6_TYPE "altera_avalon_pio" - - -/* - * pio_7 configuration - * - */ - -#define ALT_MODULE_CLASS_pio_7 altera_avalon_pio -#define PIO_7_BASE 0x21070 -#define PIO_7_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_7_CAPTURE 0 -#define PIO_7_DATA_WIDTH 32 -#define PIO_7_DO_TEST_BENCH_WIRING 0 -#define PIO_7_DRIVEN_SIM_VALUE 0 -#define PIO_7_EDGE_TYPE "NONE" -#define PIO_7_FREQ 27000000 -#define PIO_7_HAS_IN 1 -#define PIO_7_HAS_OUT 0 -#define PIO_7_HAS_TRI 0 -#define PIO_7_IRQ -1 -#define PIO_7_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_7_IRQ_TYPE "NONE" -#define PIO_7_NAME "/dev/pio_7" -#define PIO_7_RESET_VALUE 0 -#define PIO_7_SPAN 16 -#define PIO_7_TYPE "altera_avalon_pio" - - -/* - * pio_8 configuration - * - */ - -#define ALT_MODULE_CLASS_pio_8 altera_avalon_pio -#define PIO_8_BASE 0x21060 -#define PIO_8_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_8_CAPTURE 0 -#define PIO_8_DATA_WIDTH 32 -#define PIO_8_DO_TEST_BENCH_WIRING 0 -#define PIO_8_DRIVEN_SIM_VALUE 0 -#define PIO_8_EDGE_TYPE "NONE" -#define PIO_8_FREQ 27000000 -#define PIO_8_HAS_IN 1 -#define PIO_8_HAS_OUT 0 -#define PIO_8_HAS_TRI 0 -#define PIO_8_IRQ -1 -#define PIO_8_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_8_IRQ_TYPE "NONE" -#define PIO_8_NAME "/dev/pio_8" -#define PIO_8_RESET_VALUE 0 -#define PIO_8_SPAN 16 -#define PIO_8_TYPE "altera_avalon_pio" +#define ALT_MODULE_CLASS_sc_config_0 sc_config +#define SC_CONFIG_0_BASE 0x22000 +#define SC_CONFIG_0_SPAN 16 /* diff --git a/sys.qsys b/sys.qsys index c4dcdce..d12a9fe 100644 --- a/sys.qsys +++ b/sys.qsys @@ -219,153 +219,6 @@ type = "String"; } } - element pio_2 - { - datum _sortIndex - { - value = "12"; - type = "int"; - } - } - element pio_2.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135360"; - type = "String"; - } - } - element pio_3 - { - datum _sortIndex - { - value = "13"; - type = "int"; - } - } - element pio_3.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135344"; - type = "String"; - } - } - element pio_4 - { - datum _sortIndex - { - value = "14"; - type = "int"; - } - } - element pio_4.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135328"; - type = "String"; - } - } - element pio_5 - { - datum _sortIndex - { - value = "15"; - type = "int"; - } - } - element pio_5.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135312"; - type = "String"; - } - } - element pio_6 - { - datum _sortIndex - { - value = "16"; - type = "int"; - } - } - element pio_6.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135296"; - type = "String"; - } - } - element pio_7 - { - datum _sortIndex - { - value = "17"; - type = "int"; - } - } - element pio_7.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135280"; - type = "String"; - } - } - element pio_8 - { - datum _sortIndex - { - value = "18"; - type = "int"; - } - } - element pio_8.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "135264"; - type = "String"; - } - } element pulpino_0 { datum _sortIndex @@ -382,6 +235,27 @@ type = "boolean"; } } + element sc_config_0 + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + } + element sc_config_0.avalon_s + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "139264"; + type = "String"; + } + } element timer_0 { datum _sortIndex @@ -450,47 +324,17 @@ internal="pio_1.external_connection" type="conduit" dir="end" /> - - - - - - - + @@ -618,104 +462,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -728,6 +474,7 @@ + @@ -758,6 +505,15 @@ + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - + diff --git a/sys.sopcinfo b/sys.sopcinfo index a219d82..3abd255 100644 --- a/sys.sopcinfo +++ b/sys.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1540839221 + 1553288785 false true false @@ -348,54 +348,12 @@ parameters are a RESULT of the module parameters. --> clk pio_1.clk - - false - pio_2 - clk - pio_2.clk - - - false - pio_3 - clk - pio_3.clk - - - false - pio_4 - clk - pio_4.clk - false timer_0 clk timer_0.clk - - false - pio_5 - clk - pio_5.clk - - - false - pio_6 - clk - pio_6.clk - - - false - pio_7 - clk - pio_7.clk - - - false - pio_8 - clk - pio_8.clk - false master_0 @@ -438,6 +396,12 @@ parameters are a RESULT of the module parameters. --> clock_sink epcq_controller_0.clock_sink + + false + sc_config_0 + clock_sink + sc_config_0.clock_sink + - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 32 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 27000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 32 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 32 - false - true - true - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - - java.lang.String @@ -13842,6 +8442,14 @@ parameters are a RESULT of the module parameters. --> 131104 8 + + false + sc_config_0 + avalon_s + sc_config_0.avalon_s + 139264 + 64 + false hw_crc32_0 @@ -13906,62 +8514,6 @@ parameters are a RESULT of the module parameters. --> 135376 16 - - false - pio_2 - s1 - pio_2.s1 - 135360 - 16 - - - false - pio_3 - s1 - pio_3.s1 - 135344 - 16 - - - false - pio_4 - s1 - pio_4.s1 - 135328 - 16 - - - false - pio_5 - s1 - pio_5.s1 - 135312 - 16 - - - false - pio_6 - s1 - pio_6.s1 - 135296 - 16 - - - false - pio_7 - s1 - pio_7.s1 - 135280 - 16 - - - false - pio_8 - s1 - pio_8.s1 - 135264 - 16 - false onchip_memory2_0 @@ -14349,6 +8901,592 @@ parameters are a RESULT of the module parameters. --> + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_i + Input + 1 + clk + + + + + + java.lang.String + clock_sink + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_i + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 64 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock_sink + false + true + true + true + + + java.lang.String + reset_sink + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avalon_s_address + Input + 4 + address + + + avalon_s_writedata + Input + 32 + writedata + + + avalon_s_readdata + Output + 32 + readdata + + + avalon_s_byteenable + Input + 4 + byteenable + + + avalon_s_write + Input + 1 + write + + + avalon_s_read + Input + 1 + read + + + avalon_s_chipselect + Input + 1 + chipselect + + + avalon_s_waitrequest_n + Output + 1 + waitrequest_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + sc_status_i + Input + 32 + sc_status_i + + + sc_status2_i + Input + 32 + sc_status2_i + + + lt_status_i + Input + 32 + lt_status_i + + + h_config_o + Output + 32 + h_config_o + + + h_config2_o + Output + 32 + h_config2_o + + + v_config_o + Output + 32 + v_config_o + + + misc_config_o + Output + 32 + misc_config_o + + + sl_config_o + Output + 32 + sl_config_o + + + sl_config2_o + Output + 32 + sl_config2_o + + + jtag_uart_0 avalon_jtag_slave + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00022000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pulpino_0 + avalon_master_lsu + sc_config_0 + avalon_s + pio_1 s1 - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000210c0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_2 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000210b0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_3 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000210a0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_4 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00021090 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_5 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00021080 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_6 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00021070 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_7 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00021060 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_lsu - pio_8 - s1 - pio_1 clk - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_2 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_3 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_4 - clk - timer_0 clk - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_5 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_6 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_7 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pio_8 - clk - epcq_controller_0 clock_sink + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk + sc_config_0 + clock_sink + pio_1 reset - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_2 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_3 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_4 - reset - timer_0 reset - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_5 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_6 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_7 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pio_8 - reset - hw_crc32_0 reset_sink + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk_reset + sc_config_0 + reset_sink + 1 clock_source @@ -17347,7 +11855,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 18 + 12 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -17355,7 +11863,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 18 + 12 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -17363,7 +11871,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 19 + 13 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -17395,7 +11903,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 12 + 6 conduit_end com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -17443,7 +11951,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 9 + 2 altera_avalon_pio com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule @@ -17466,6 +11974,14 @@ parameters are a RESULT of the module parameters. --> Interrupt Receiver 17.1 + + 1 + sc_config + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + sc_config + 1.0 + 1 altera_avalon_timer @@ -17475,7 +11991,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 20 + 14 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -17483,7 +11999,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 18 + 12 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -17499,7 +12015,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 18 + 12 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection