mirror of
https://github.com/marqs85/ossc.git
synced 2024-12-31 22:31:25 +00:00
sdc: update input pclk parameters
-rename to pclk_direct/pclk_indirect for clarity -raise pclk_indirect from 27MHz to 33MHz to match actual line5x:ed input
This commit is contained in:
marqs
parent
817012e23e
commit
a8d1fad24a
40
ossc.sdc
40
ossc.sdc
@ -9,14 +9,14 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
|
||||
|
||||
### Scanconverter clock constraints ###
|
||||
|
||||
create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
|
||||
create_clock -period 27MHz -name pclk_sdtv [get_ports PCLK_in] -add
|
||||
create_clock -period 108MHz -name pclk_direct [get_ports PCLK_in]
|
||||
create_clock -period 33MHz -name pclk_indirect [get_ports PCLK_in] -add
|
||||
|
||||
#derive_pll_clocks
|
||||
create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
|
||||
create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
|
||||
create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
|
||||
create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
|
||||
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
|
||||
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
|
||||
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
|
||||
create_generated_clock -master_clock pclk_indirect -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
@ -24,17 +24,17 @@ derive_clock_uncertainty
|
||||
set TVP_dmin 0
|
||||
set TVP_dmax 1.5
|
||||
set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
|
||||
set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs
|
||||
set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
|
||||
set_input_delay -clock pclk_sdtv -min $TVP_dmin $critinputs -add_delay
|
||||
set_input_delay -clock pclk_sdtv -max $TVP_dmax $critinputs -add_delay
|
||||
set_input_delay -clock pclk_direct -min $TVP_dmin $critinputs
|
||||
set_input_delay -clock pclk_direct -max $TVP_dmax $critinputs
|
||||
set_input_delay -clock pclk_indirect -min $TVP_dmin $critinputs -add_delay
|
||||
set_input_delay -clock pclk_indirect -max $TVP_dmax $critinputs -add_delay
|
||||
|
||||
# output delay constraints
|
||||
set IT_Tsu 1.0
|
||||
set IT_Th -0.5
|
||||
set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -min $IT_Th $critoutputs_hdmi
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -max $IT_Tsu $critoutputs_hdmi
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_direct -min $IT_Th $critoutputs_hdmi
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_direct -max $IT_Tsu $critoutputs_hdmi
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -max $IT_Tsu $critoutputs_hdmi -add_delay
|
||||
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -min $IT_Th $critoutputs_hdmi -add_delay
|
||||
@ -48,17 +48,17 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
|
||||
|
||||
### CPU/scanconverter clock relations ###
|
||||
|
||||
# Set hdtv pixel clock group as exclusive
|
||||
set_clock_groups -exclusive -group {pclk_hdtv}
|
||||
# Set direct pixel clock as exclusive group
|
||||
set_clock_groups -exclusive -group {pclk_direct}
|
||||
|
||||
# Treat CPU clock asynchronous to pixel clocks
|
||||
set_clock_groups -asynchronous -group {clk27}
|
||||
|
||||
# Ignore following clock transfers
|
||||
set_false_path -from [get_clocks pclk_2x] -to [get_clocks {pclk_sdtv pclk_3x pclk_4x pclk_5x}]
|
||||
set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv pclk_2x pclk_4x pclk_5x}]
|
||||
set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_5x}]
|
||||
set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_4x}]
|
||||
set_false_path -from [get_clocks pclk_2x] -to [get_clocks {pclk_indirect pclk_3x pclk_4x pclk_5x}]
|
||||
set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_indirect pclk_2x pclk_4x pclk_5x}]
|
||||
set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_indirect pclk_2x pclk_3x pclk_5x}]
|
||||
set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_indirect pclk_2x pclk_3x pclk_4x}]
|
||||
|
||||
# Ignore paths which would result from pclk_act switchover during postprocess chain
|
||||
set pclk_act_regs [get_registers {scanconverter:scanconverter_inst|R_out* \
|
||||
@ -68,8 +68,8 @@ set pclk_act_regs [get_registers {scanconverter:scanconverter_inst|R_out* \
|
||||
scanconverter:scanconverter_inst|VSYNC_out \
|
||||
scanconverter:scanconverter_inst|DE_out \
|
||||
scanconverter:scanconverter_inst|*_pp*}]
|
||||
set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs
|
||||
set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*]
|
||||
set_false_path -from [get_clocks {pclk_indirect}] -to $pclk_act_regs
|
||||
set_false_path -from [get_clocks {pclk_indirect}] -to [get_ports HDMI_TX_*]
|
||||
|
||||
# Ignore paths from registers which are updated only at leading edge of vsync
|
||||
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user