From aa1e9eb60cb94da1e479e69e2fb415b82b4c69f2 Mon Sep 17 00:00:00 2001
From: marqs <mhiienka@niksula.hut.fi>
Date: Sun, 9 Feb 2020 18:41:33 +0200
Subject: [PATCH] tvp7002 related updates

* fix clock selection function implementation
* add support for ALC filter configuration
* add coarse clamp LPF selection
* add support for clamp/ALC offset
---
 software/sys_controller/tvp7002/tvp7002.c | 42 ++++++++++++++++-------
 software/sys_controller/tvp7002/tvp7002.h | 10 ++++--
 2 files changed, 37 insertions(+), 15 deletions(-)

diff --git a/software/sys_controller/tvp7002/tvp7002.c b/software/sys_controller/tvp7002/tvp7002.c
index 8251a23..aa5c756 100644
--- a/software/sys_controller/tvp7002/tvp7002.c
+++ b/software/sys_controller/tvp7002/tvp7002.c
@@ -25,7 +25,6 @@
 #include "tvp7002.h"
 
 //#define SYNCBYPASS    // Bypass VGA syncs (for debug - needed for interlace?)
-//#define EXTADCCLK     // Use external ADC clock (external osc)
 //#define ADCPOWERDOWN  // Power-down ADCs
 //#define PLLPOSTDIV    // Double-rate PLL with div-by-2 (decrease jitter?)
 
@@ -159,8 +158,8 @@ void tvp_init()
 
     // Set default configuration (skip those which match register reset values)
 
-    // Configure external refclk
-    tvp_sel_clk(REFCLK_EXT27);
+    // Configure external refclk, HPLL generated pclk
+    tvp_sel_clk(REFCLK_EXT27, 0);
 
     // Hsync input->output delay (horizontal shift)
     // Default is 13, which maintains alignment of RGB and hsync at output
@@ -261,20 +260,21 @@ void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldi
     tvp_writereg(TVP_HPLLCTRL, ((vco_range << 6) | (cp_current << 3)));
 }
 
-void tvp_sel_clk(tvp_refclk_t refclk)
+void tvp_sel_clk(tvp_refclk_t refclk, alt_u8 ext_pclk)
 {
-    alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xFA;
+    alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xF5;
 
     //TODO: set SOG and CLP LPF based on mode
-    if (refclk == REFCLK_INTCLK) {
-        tvp_writereg(TVP_INPMUX2, status|0x2);
+    if (refclk == REFCLK_EXT27) {
+        status |= 0x8;
+
+        if (!ext_pclk)
+            status |= 0x2;
     } else {
-#ifdef EXTADCCLK
-        tvp_writereg(TVP_INPMUX2, status|0x8);
-#else
-        tvp_writereg(TVP_INPMUX2, status|0xA);
-#endif
+        status |= 0x2;
     }
+
+    tvp_writereg(TVP_INPMUX2, status);
 }
 
 void tvp_sel_csc(const ypbpr_to_rgb_csc_t *csc)
@@ -315,6 +315,13 @@ void tvp_set_sync_lpf(alt_u8 val)
     printf("Sync LPF value set to 0x%x\n", val);
 }
 
+void tvp_set_clp_lpf(alt_u8 val)
+{
+    alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xCF;
+    tvp_writereg(TVP_INPMUX2, status|(val<<4));
+    printf("CLP LPF value set to 0x%x\n", val);
+}
+
 alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult)
 {
     alt_u8 sample_sel;
@@ -360,8 +367,17 @@ void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen)
     }
 }
 
-void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen)
+void tvp_set_alcfilt(alt_u8 nsv, alt_u8 nsh) {
+    tvp_writereg(TVP_ALCFILT, (nsv<<3)|nsh);
+}
+
+void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_8 clampoffset)
 {
+    if (((alt_16)h_syncinlen + clampoffset) < 0)
+        h_syncinlen = 0;
+    else
+        h_syncinlen += clampoffset;
+
     // Clamp position and ALC
     tvp_set_clamp_position(type, h_syncinlen);
     tvp_set_alc(1, type, h_syncinlen);
diff --git a/software/sys_controller/tvp7002/tvp7002.h b/software/sys_controller/tvp7002/tvp7002.h
index e6662e3..c77a5bb 100644
--- a/software/sys_controller/tvp7002/tvp7002.h
+++ b/software/sys_controller/tvp7002/tvp7002.h
@@ -34,6 +34,8 @@
 #define DEFAULT_FINE_GAIN       26
 #define DEFAULT_FINE_OFFSET     0x80
 #define DEFAULT_COARSE_GAIN     0x8
+#define DEFAULT_ALC_H_FILTER    0x3
+#define DEFAULT_ALC_V_FILTER    0xA
 
 #define TVP_INTCLK_HZ           6500000UL
 #define TVP_EXTCLK_HZ           27000000UL
@@ -105,7 +107,7 @@ void tvp_set_gain_offset(color_setup_t *col);
 
 void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2);
 
-void tvp_sel_clk(tvp_refclk_t refclk);
+void tvp_sel_clk(tvp_refclk_t refclk, alt_u8 ext_pclk);
 
 void tvp_sel_csc(const ypbpr_to_rgb_csc_t *csc);
 
@@ -113,13 +115,17 @@ void tvp_set_lpf(alt_u8 val);
 
 void tvp_set_sync_lpf(alt_u8 val);
 
+void tvp_set_clp_lpf(alt_u8 val);
+
 alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult);
 
 void tvp_set_sog_thold(alt_u8 val);
 
 void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen);
 
-void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen);
+void tvp_set_alcfilt(alt_u8 nsv, alt_u8 nsh);
+
+void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_8 clampoffset);
 
 void tvp_source_sel(tvp_input_t input, tvp_sync_input_t syncinput, video_format fmt);