From aa4beec9579e96e50c500c66273c029e27f5ee64 Mon Sep 17 00:00:00 2001 From: marqs Date: Tue, 31 Jan 2023 20:50:33 +0200 Subject: [PATCH] bump sys_ctrl register to 32bit --- software/sys_controller/ossc/controls.c | 4 ++-- software/sys_controller/ossc/firmware.c | 2 +- software/sys_controller/spi_charlcd/lcd.c | 2 +- software/sys_controller/ulibSD/spi_io.c | 2 +- software/sys_controller_bsp/libhal_bsp.a | Bin 34716 -> 34716 bytes software/sys_controller_bsp/system.h | 2 +- sys.qsys | 2 +- sys.sopcinfo | 12 ++++++------ 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/software/sys_controller/ossc/controls.c b/software/sys_controller/ossc/controls.c index 59c7425..1ea34d3 100644 --- a/software/sys_controller/ossc/controls.c +++ b/software/sys_controller/ossc/controls.c @@ -43,7 +43,7 @@ extern avmode_t cm; extern avconfig_t tc; extern avinput_t target_input; extern alt_u8 menu_active; -extern alt_u16 sys_ctrl; +extern alt_u32 sys_ctrl; extern alt_u16 tc_sampler_phase; extern alt_u8 profile_sel, profile_sel_menu; extern alt_u8 lcd_bl_timeout; @@ -182,7 +182,7 @@ int parse_control() sniprintf((char*)osd->osd_array.data[1][0], OSD_CHAR_COLS, "Mode preset:"); sniprintf((char*)osd->osd_array.data[1][1], OSD_CHAR_COLS, "%s", video_modes[cm.id].name); sniprintf((char*)osd->osd_array.data[2][0], OSD_CHAR_COLS, "Imode (FPGA):"); - sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)((sc_status.vmax+1)<osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)sc_status.vmax, sc_status.interlace_flag ? 'i' : 'p', sc_status.fpga_vsyncgen ? '*' : ' ', fpga_v_hz_x100/100, diff --git a/software/sys_controller/ossc/firmware.c b/software/sys_controller/ossc/firmware.c index 9ba1576..6be99ed 100644 --- a/software/sys_controller/ossc/firmware.c +++ b/software/sys_controller/ossc/firmware.c @@ -33,7 +33,7 @@ extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1]; extern alt_u16 rc_keymap[REMOTE_MAX_KEYS]; extern SD_DEV sdcard_dev; -extern alt_u16 sys_ctrl; +extern alt_u32 sys_ctrl; static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr) { diff --git a/software/sys_controller/spi_charlcd/lcd.c b/software/sys_controller/spi_charlcd/lcd.c index 2740c13..21f375e 100644 --- a/software/sys_controller/spi_charlcd/lcd.c +++ b/software/sys_controller/spi_charlcd/lcd.c @@ -31,7 +31,7 @@ #define WRDELAY 20 #define CLEARDELAY 800 -extern alt_u16 sys_ctrl; +extern alt_u32 sys_ctrl; static void lcd_cmd(alt_u8 cmd, alt_u16 postdelay) { SPI_write(I2CA_BASE, &cmd, 1); diff --git a/software/sys_controller/ulibSD/spi_io.c b/software/sys_controller/ulibSD/spi_io.c index 949bd65..a9172b9 100644 --- a/software/sys_controller/ulibSD/spi_io.c +++ b/software/sys_controller/ulibSD/spi_io.c @@ -7,7 +7,7 @@ #include "spi_io.h" #include "av_controller.h" -extern alt_u16 sys_ctrl; +extern alt_u32 sys_ctrl; alt_u32 sd_timer_ts; diff --git a/software/sys_controller_bsp/libhal_bsp.a b/software/sys_controller_bsp/libhal_bsp.a index f7b96a6eaa125286da9031a2aac57b363f41ba76..204804f3aae151cf2f2ca8936157023e8a4a8585 100644 GIT binary patch delta 344 zcmbQ!&orl>X@V4oxsj2Pp`nS{Mx_!qIA`-bHWL9jZ}K`JiOrwHuCT*JHlLIG!Ggq7 z4q=7!CZCg&-0ZCB&y5h7$0oLUgULH)6p_grOq@3Vvsi;Fy7`37BPN8pbwc8sPuk}q z*=6SvfzYvep8F0YSI7Cua3JfI+&nvs8KHMF$Q^s4&LNo(5n*H8ye{qpBV6m|x`Y4} gZQ`5Xrc6axJNcZl)8;c7LP(yT$0ok{Z|;0a09R3B-2eap delta 200 zcmbQ!&orl>X@b<`xI(UtDn)EST5j_eHaP(>JQ8SQxvYoWt<_#wAm_dxm8%&%w|Fc-b4Ay|+kPyhe` diff --git a/software/sys_controller_bsp/system.h b/software/sys_controller_bsp/system.h index 080221f..6e506f6 100644 --- a/software/sys_controller_bsp/system.h +++ b/software/sys_controller_bsp/system.h @@ -337,7 +337,7 @@ #define PIO_0_BIT_CLEARING_EDGE_REGISTER 0 #define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0 #define PIO_0_CAPTURE 0 -#define PIO_0_DATA_WIDTH 16 +#define PIO_0_DATA_WIDTH 32 #define PIO_0_DO_TEST_BENCH_WIRING 0 #define PIO_0_DRIVEN_SIM_VALUE 0 #define PIO_0_EDGE_TYPE "NONE" diff --git a/sys.qsys b/sys.qsys index 8dbac89..34431cf 100644 --- a/sys.qsys +++ b/sys.qsys @@ -502,7 +502,7 @@ - + diff --git a/sys.sopcinfo b/sys.sopcinfo index da17af9..d19b6dc 100644 --- a/sys.sopcinfo +++ b/sys.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1672145913 + 1672179572 false true false @@ -6544,7 +6544,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.DATA_WIDTH - 16 + 32 embeddedsw.CMacro.DO_TEST_BENCH_WIRING @@ -6596,7 +6596,7 @@ the requested settings for a module instance. --> embeddedsw.dts.params.altr,gpio-bank-width - 16 + 32 embeddedsw.dts.params.resetvalue @@ -6688,7 +6688,7 @@ the requested settings for a module instance. --> int - 16 + 32 false true true @@ -7296,7 +7296,7 @@ parameters are a RESULT of the module parameters. --> out_port Output - 16 + 32 export