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marqs 2020-06-17 02:22:24 +03:00
parent daf9ec1611
commit aa7a92e130
5 changed files with 8587 additions and 8415 deletions
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16992
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

2
software/sys_controller/ossc/av_controller.c
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@ -642,7 +642,7 @@ void program_mode()
v_syncinlen = tvp_readreg(TVP_VSINWIDTH);
printf("Hswidth: %u Vswidth: %u Macrovision: %u\n", (unsigned)h_syncinlen, (unsigned)(v_syncinlen & 0x1F), (unsigned)cm.macrovis);
sniprintf(row1, LCD_ROW_LEN+1, "%s %u%c", avinput_str[cm.avinput], (unsigned)cm.totlines, cm.progressive ? 'p' : 'i');
sniprintf(row1, LCD_ROW_LEN+1, "%s %u-%c", avinput_str[cm.avinput], (unsigned)cm.totlines, cm.progressive ? 'p' : 'i');
sniprintf(row2, LCD_ROW_LEN+1, "%u.%.2ukHz %u.%.2uHz", (unsigned)(h_hz/1000), (unsigned)((h_hz%1000)/10), (unsigned)(v_hz_x100/100), (unsigned)(v_hz_x100%100));
if (!menu_active) {
osd->osd_config.status_refresh = 1;

2
software/sys_controller/ossc/avconfig.h
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@ -56,7 +56,7 @@
#define L5FMT_1600x1200 1
#define L5FMT_1920x1200 2
static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr", "Last used" };
static const char *avinput_str[] = { "Test pattern", "AV1_RGBS", "AV1_RGsB", "AV1_YPbPr", "AV2_YPbPr", "AV2_RGsB", "AV3_RGBHV", "AV3_RGBS", "AV3_RGsB", "AV3_YPbPr", "Last used" };
typedef enum {
AV_TESTPAT = 0,

2
software/sys_controller/ossc/controls.c
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@ -170,7 +170,7 @@ int parse_control()
((fpga_status >> 16) & 0x3) ? '*' : ' ',
fpga_v_hz_x100/100,
fpga_v_hz_x100%100);*/
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %lu", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu-%c%c %lu", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
sc_status.interlace_flag ? 'i' : 'p',
sc_status.fpga_vsyncgen ? '*' : ' ',
(unsigned long)sc_status2.pcnt_frame);

4
software/sys_controller/tvp7002/video_modes.c
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@ -139,8 +139,8 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_1X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hdmitx_vic = video_modes[i].vic;
// Upsample / pixel-repeat horizontal resolution of 240p/480i modes to fulfill min. 25MHz TMDS clock requirement
if ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_480I)) {
// Upsample / pixel-repeat horizontal resolution of 240p/480i/384p modes to fulfill min. 25MHz TMDS clock requirement
if ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_480I) || ((video_modes[i].group == GROUP_384P) && (video_modes[i].flags & MODE_PLLDIVBY2))) {
if (cm.cc.upsample2x)
cm.sample_mult = 2;
else