From ac0181a69814d25d8b195dd86619ecae1c3724cc Mon Sep 17 00:00:00 2001 From: marqs Date: Mon, 15 Jul 2024 12:23:20 +0300 Subject: [PATCH] update to Quartus 23.1 * add patch file to enforce LE use on small memory blocks * utilize M9K freed from epcq_controller for restoring profile export function --- ossc.qsf | 2 +- rtl/char_array.qip | 2 +- rtl/char_array.v | 4 +- rtl/char_rom.qip | 2 +- rtl/char_rom.v | 4 +- rtl/linebuf.qip | 2 +- rtl/linebuf.v | 4 +- rtl/lpm_mult_8x5_9.qip | 2 +- rtl/lpm_mult_8x5_9.v | 18 +- rtl/lpm_mult_sl.qip | 2 +- rtl/lpm_mult_sl.v | 4 +- rtl/ossc.v | 7 + rtl/pll_2x.qip | 2 +- rtl/pll_2x.v | 7 +- scripts/qsys.patch | 35 ++ software/sys_controller/link.common.ld | 2 +- software/sys_controller/ossc/menu.c | 2 - sys.qsys | 176 ++---- sys.sopcinfo | 829 +++++++------------------ 19 files changed, 362 insertions(+), 744 deletions(-) create mode 100644 scripts/qsys.patch diff --git a/ossc.qsf b/ossc.qsf index 23fd326..243d454 100644 --- a/ossc.qsf +++ b/ossc.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8 set_global_assignment -name TOP_LEVEL_ENTITY ossc set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 diff --git a/rtl/char_array.qip b/rtl/char_array.qip index 9dc3a16..7bbcb8b 100644 --- a/rtl/char_array.qip +++ b/rtl/char_array.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_TOOL_VERSION "23.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"] diff --git a/rtl/char_array.v b/rtl/char_array.v index 60ee132..79240a2 100644 --- a/rtl/char_array.v +++ b/rtl/char_array.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition // ************************************************************ -//Copyright (C) 2021 Intel Corporation. All rights reserved. +//Copyright (C) 2024 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing diff --git a/rtl/char_rom.qip b/rtl/char_rom.qip index f17cff1..625ec26 100644 --- a/rtl/char_rom.qip +++ b/rtl/char_rom.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_TOOL_VERSION "23.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"] diff --git a/rtl/char_rom.v b/rtl/char_rom.v index 7d7df19..d9453e2 100644 --- a/rtl/char_rom.v +++ b/rtl/char_rom.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition // ************************************************************ -//Copyright (C) 2021 Intel Corporation. All rights reserved. +//Copyright (C) 2024 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing diff --git a/rtl/linebuf.qip b/rtl/linebuf.qip index 17270d7..9fe20c8 100644 --- a/rtl/linebuf.qip +++ b/rtl/linebuf.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_TOOL_VERSION "23.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"] diff --git a/rtl/linebuf.v b/rtl/linebuf.v index 19140a9..4190b1f 100644 --- a/rtl/linebuf.v +++ b/rtl/linebuf.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition // ************************************************************ -//Copyright (C) 2021 Intel Corporation. All rights reserved. +//Copyright (C) 2024 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing diff --git a/rtl/lpm_mult_8x5_9.qip b/rtl/lpm_mult_8x5_9.qip index 39a35c4..ed60fb5 100644 --- a/rtl/lpm_mult_8x5_9.qip +++ b/rtl/lpm_mult_8x5_9.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_TOOL_VERSION "23.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_8x5_9.v"] diff --git a/rtl/lpm_mult_8x5_9.v b/rtl/lpm_mult_8x5_9.v index 2c704cc..e27b9dc 100644 --- a/rtl/lpm_mult_8x5_9.v +++ b/rtl/lpm_mult_8x5_9.v @@ -1,7 +1,7 @@ // megafunction wizard: %LPM_MULT% // GENERATION: STANDARD // VERSION: WM1.0 -// MODULE: lpm_mult +// MODULE: lpm_mult // ============================================================ // File Name: lpm_mult_8x5_9.v @@ -14,17 +14,17 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition // ************************************************************ -//Copyright (C) 2021 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and any partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License +//Copyright (C) 2024 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License //Subscription Agreement, the Intel Quartus Prime License Agreement, //the Intel FPGA IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for diff --git a/rtl/lpm_mult_sl.qip b/rtl/lpm_mult_sl.qip index 7fd7606..b6c579b 100644 --- a/rtl/lpm_mult_sl.qip +++ b/rtl/lpm_mult_sl.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_TOOL_VERSION "23.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_sl.v"] diff --git a/rtl/lpm_mult_sl.v b/rtl/lpm_mult_sl.v index 4b660dc..7818116 100644 --- a/rtl/lpm_mult_sl.v +++ b/rtl/lpm_mult_sl.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition // ************************************************************ -//Copyright (C) 2021 Intel Corporation. All rights reserved. +//Copyright (C) 2024 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing diff --git a/rtl/ossc.v b/rtl/ossc.v index 58678e5..474bf10 100644 --- a/rtl/ossc.v +++ b/rtl/ossc.v @@ -406,6 +406,13 @@ sys sys_inst( .pll_reconfig_0_pll_reconfig_if_scandone (pll_scandone) ); +// These do not work in current Quartus version (23.1) and a patch file (scripts/qsys.patch) must be used after Qsys generation instead +defparam + sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.USE_MEMORY_BLOCKS = 0, + sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.avst_fifo.USE_MEMORY_BLOCKS = 0, + sys_inst.master_0.fifo.USE_MEMORY_BLOCKS = 0, + sys_inst.onchip_memory2_0.the_altsyncram.MAXIMUM_DEPTH = 2048; + scanconverter #( .EMIF_ENABLE(0), .NUM_LINE_BUFFERS(2) diff --git a/rtl/pll_2x.qip b/rtl/pll_2x.qip index d047ad4..9716b1d 100644 --- a/rtl/pll_2x.qip +++ b/rtl/pll_2x.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_TOOL_VERSION "23.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"] diff --git a/rtl/pll_2x.v b/rtl/pll_2x.v index 2f50912..4b590d1 100644 --- a/rtl/pll_2x.v +++ b/rtl/pll_2x.v @@ -9,16 +9,16 @@ // altpll // // Simulation Library Files(s): -// altera_mf +// // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition // ************************************************************ -//Copyright (C) 2021 Intel Corporation. All rights reserved. +//Copyright (C) 2024 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing @@ -377,5 +377,4 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE -// Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/scripts/qsys.patch b/scripts/qsys.patch new file mode 100644 index 0000000..d5de326 --- /dev/null +++ b/scripts/qsys.patch @@ -0,0 +1,35 @@ +--- sys/synthesis/submodules/altera_asmi2_xip_controller.sv 2024-07-15 02:34:49.476724296 +0300 ++++ sys/synthesis/submodules/altera_asmi2_xip_controller.sv 2024-07-15 02:50:24.750038794 +0300 +@@ -611,7 +611,7 @@ + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (3), +- .USE_MEMORY_BLOCKS (1), ++ .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + +--- sys/synthesis/submodules/sys_master_0.v 2024-07-15 02:34:47.396703537 +0300 ++++ sys/synthesis/submodules/sys_master_0.v 2024-07-15 02:50:14.617938092 +0300 +@@ -163,7 +163,7 @@ + .USE_PACKETS (0), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (3), +- .USE_MEMORY_BLOCKS (1), ++ .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + +--- sys/synthesis/submodules/sys_onchip_memory2_0.v 2024-07-15 02:34:47.540704974 +0300 ++++ sys/synthesis/submodules/sys_onchip_memory2_0.v 2024-07-15 02:49:59.685789671 +0300 +@@ -71,7 +71,7 @@ + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", +- the_altsyncram.maximum_depth = 10496, ++ the_altsyncram.maximum_depth = 2048, + the_altsyncram.numwords_a = 10496, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", diff --git a/software/sys_controller/link.common.ld b/software/sys_controller/link.common.ld index f0d6e7b..48a00f3 100644 --- a/software/sys_controller/link.common.ld +++ b/software/sys_controller/link.common.ld @@ -3,7 +3,7 @@ __DYNAMIC = 0; MEMORY { - dataram : ORIGIN = 0x00010000, LENGTH = 0xa000 + dataram : ORIGIN = 0x00010000, LENGTH = 0xa400 } /* Stack information variables */ diff --git a/software/sys_controller/ossc/menu.c b/software/sys_controller/ossc/menu.c index bc5ae54..1beaa27 100644 --- a/software/sys_controller/ossc/menu.c +++ b/software/sys_controller/ossc/menu.c @@ -255,9 +255,7 @@ MENU(menu_settings, P99_PROTECT({ \ { LNG("","<ｾｯﾃｲｦｼｮｷｶ >"), OPT_FUNC_CALL, { .fun = { set_default_avconfig, NULL } } }, #ifndef DEBUG { LNG("","<ｾｯﾃｲﾖﾐｺﾐ >"), OPT_FUNC_CALL, { .fun = { import_userdata, NULL } } }, -#if 0 { LNG("","<ｾｯﾃｲｶｷｺﾐ >"), OPT_FUNC_CALL, { .fun = { export_userdata, NULL } } }, -#endif { LNG("","<ﾌｧｰﾑｳｪｱｱｯﾌﾟﾃﾞｰﾄ>"), OPT_FUNC_CALL, { .fun = { fw_update, NULL } } }, #endif })) diff --git a/sys.qsys b/sys.qsys index 0e47089..253950b 100644 --- a/sys.qsys +++ b/sys.qsys @@ -13,7 +13,7 @@ { datum _sortIndex { - value = "0"; + value = "1"; type = "int"; } } @@ -118,28 +118,15 @@ { datum _sortIndex { - value = "5"; + value = "0"; type = "int"; } } - element jtag_uart_0.avalon_jtag_slave - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "131104"; - type = "String"; - } - } element master_0 { datum _sortIndex { - value = "3"; + value = "4"; type = "int"; } } @@ -147,7 +134,7 @@ { datum _sortIndex { - value = "2"; + value = "3"; type = "int"; } } @@ -164,19 +151,6 @@ type = "String"; } } - element onchip_memory2_0.s2 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "65536"; - type = "String"; - } - } element osd_generator_0 { datum _sortIndex @@ -265,7 +239,7 @@ { datum _sortIndex { - value = "1"; + value = "2"; type = "int"; } } @@ -302,23 +276,10 @@ { datum _sortIndex { - value = "4"; + value = "5"; type = "int"; } } - element timer_0.s1 - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "131072"; - type = "String"; - } - } } ]]> @@ -387,7 +348,7 @@ internal="sc_config_0.sc_if" type="conduit" dir="end" /> - + @@ -396,7 +357,7 @@ @@ -426,7 +387,7 @@ @@ -444,8 +405,8 @@ @@ -454,13 +415,12 @@ - $${FILENAME}_onchip_memory2_0 @@ -470,14 +430,14 @@ COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 - + - + @@ -490,7 +450,7 @@ - + @@ -504,7 +464,7 @@ - + @@ -532,7 +492,7 @@ - + @@ -546,7 +506,7 @@ @@ -555,7 +515,7 @@ @@ -564,7 +524,7 @@ @@ -573,7 +533,7 @@ @@ -582,7 +542,7 @@ @@ -591,7 +551,7 @@ @@ -600,7 +560,7 @@ @@ -609,7 +569,7 @@ @@ -618,7 +578,7 @@ @@ -627,7 +587,7 @@ @@ -636,7 +596,7 @@ @@ -645,7 +605,7 @@ @@ -654,7 +614,7 @@ @@ -663,16 +623,16 @@ + end="onchip_memory2_0.s1"> @@ -681,166 +641,166 @@ + end="onchip_memory2_0.s1"> - - - - - + + + + + diff --git a/sys.sopcinfo b/sys.sopcinfo index 604310a..63a6d53 100644 --- a/sys.sopcinfo +++ b/sys.sopcinfo @@ -1,11 +1,11 @@ - - + + java.lang.Integer - 1695068946 + 1721036059 false true false @@ -95,7 +95,7 @@ true true - + @@ -148,7 +148,7 @@ the requested settings for a module instance. --> true true - + @@ -213,7 +213,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -262,7 +262,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -415,7 +415,7 @@ parameters are a RESULT of the module parameters. --> epcq_controller2_0.clock_sink - + @@ -480,7 +480,7 @@ parameters are a RESULT of the module parameters. --> @@ -686,7 +686,7 @@ the requested settings for a module instance. --> true true - + @@ -1063,7 +1063,7 @@ parameters are a RESULT of the module parameters. --> readdatavalid - + @@ -1452,7 +1452,7 @@ parameters are a RESULT of the module parameters. --> byteenable - + @@ -1529,7 +1529,7 @@ parameters are a RESULT of the module parameters. --> irq - + @@ -1590,7 +1590,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -1655,7 +1655,7 @@ the requested settings for a module instance. --> true true - + @@ -1700,7 +1700,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -1745,7 +1745,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -2154,7 +2154,7 @@ the requested settings for a module instance. --> true true - + @@ -2199,7 +2199,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -2244,7 +2244,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -2301,7 +2301,7 @@ parameters are a RESULT of the module parameters. --> export - + @@ -2672,7 +2672,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -2781,7 +2781,7 @@ the requested settings for a module instance. --> true true - + @@ -2826,7 +2826,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -2871,7 +2871,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -2928,7 +2928,7 @@ parameters are a RESULT of the module parameters. --> export - + @@ -3299,7 +3299,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -3380,7 +3380,7 @@ parameters are a RESULT of the module parameters. --> @@ -3563,7 +3563,7 @@ the requested settings for a module instance. --> true true - + @@ -3624,7 +3624,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -3669,7 +3669,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -4046,7 +4046,7 @@ parameters are a RESULT of the module parameters. --> waitrequest - + @@ -4126,8 +4126,8 @@ parameters are a RESULT of the module parameters. --> @@ -4177,14 +4177,6 @@ the requested settings for a module instance. --> true true - - int - 0 - false - true - true - true - java.lang.String CYCLONEIVE @@ -4229,7 +4221,7 @@ the requested settings for a module instance. --> true true - + @@ -4274,7 +4266,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -4319,7 +4311,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -4648,13 +4640,13 @@ parameters are a RESULT of the module parameters. --> false onchip_memory2_0 - s2 - onchip_memory2_0.s2 + s1 + onchip_memory2_0.s1 65536 - 40960 + 41984 - + @@ -4719,7 +4711,7 @@ parameters are a RESULT of the module parameters. --> @@ -4737,7 +4729,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.DUAL_PORT - 1 + 0 embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE @@ -4777,7 +4769,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.SIZE_VALUE - 40960 + 41984 embeddedsw.CMacro.WRITABLE @@ -4853,7 +4845,7 @@ the requested settings for a module instance. --> boolean - true + false false true true @@ -4863,7 +4855,7 @@ the requested settings for a module instance. --> boolean false false - true + false true true @@ -4909,7 +4901,7 @@ the requested settings for a module instance. --> long - 40960 + 41984 false true true @@ -4919,7 +4911,7 @@ the requested settings for a module instance. --> java.lang.String DONT_CARE false - true + false true true @@ -4943,7 +4935,7 @@ the requested settings for a module instance. --> boolean true false - true + false true true @@ -4967,7 +4959,7 @@ the requested settings for a module instance. --> int 1 false - true + false true true @@ -5110,7 +5102,52 @@ the requested settings for a module instance. --> true true - + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + @@ -5140,7 +5177,7 @@ parameters are a RESULT of the module parameters. --> int - 1 + 0 false true false @@ -5148,7 +5185,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 40960 + 41984 true true false @@ -5236,7 +5273,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 40960 + 41984 false true true @@ -5487,429 +5524,7 @@ parameters are a RESULT of the module parameters. --> byteenable - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 1 - false - true - false - true - - - java.math.BigInteger - 40960 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk1 - false - true - true - true - - - java.lang.String - reset1 - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 40960 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address2 - Input - 14 - address - - - chipselect2 - Input - 1 - chipselect - - - clken2 - Input - 1 - clken - - - write2 - Input - 1 - write - - - readdata2 - Output - 32 - readdata - - - writedata2 - Input - 32 - writedata - - - byteenable2 - Input - 4 - byteenable - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - + @@ -5984,7 +5599,7 @@ the requested settings for a module instance. --> true true - + @@ -6029,7 +5644,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -6074,7 +5689,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -6457,7 +6072,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -6527,7 +6142,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -6784,7 +6399,7 @@ the requested settings for a module instance. --> true true - + @@ -6845,7 +6460,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -6890,7 +6505,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -7255,7 +6870,7 @@ parameters are a RESULT of the module parameters. --> readdata - + @@ -7301,7 +6916,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -7558,7 +7173,7 @@ the requested settings for a module instance. --> true true - + @@ -7619,7 +7234,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -7664,7 +7279,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -8011,7 +7626,7 @@ parameters are a RESULT of the module parameters. --> readdata - + @@ -8080,7 +7695,7 @@ the requested settings for a module instance. --> true true - + @@ -8125,7 +7740,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -8170,7 +7785,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -8553,7 +8168,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -8730,7 +8345,7 @@ the requested settings for a module instance. --> true true - + @@ -8775,7 +8390,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -8838,7 +8453,7 @@ parameters are a RESULT of the module parameters. --> boot_addr_i - + @@ -8883,7 +8498,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -8987,7 +8602,7 @@ parameters are a RESULT of the module parameters. --> 1 - + @@ -9285,10 +8900,10 @@ parameters are a RESULT of the module parameters. --> s1 onchip_memory2_0.s1 65536 - 40960 + 41984 - + @@ -9709,13 +9324,13 @@ parameters are a RESULT of the module parameters. --> false onchip_memory2_0 - s2 - onchip_memory2_0.s2 + s1 + onchip_memory2_0.s1 65536 - 40960 + 41984 - + @@ -10112,7 +9727,7 @@ the requested settings for a module instance. --> true true - + @@ -10157,7 +9772,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -10202,7 +9817,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -10585,7 +10200,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -10718,7 +10333,7 @@ parameters are a RESULT of the module parameters. --> @@ -10770,6 +10385,10 @@ the requested settings for a module instance. --> embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT 0 + + embeddedsw.CMacro.TIMER_DEVICE_TYPE + 1 + embeddedsw.dts.compatible altr,timer-1.0 @@ -10944,7 +10563,7 @@ the requested settings for a module instance. --> true true - + @@ -11005,7 +10624,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -11050,7 +10669,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -11419,7 +11038,7 @@ parameters are a RESULT of the module parameters. --> write_n - + @@ -11500,7 +11119,7 @@ parameters are a RESULT of the module parameters. --> @@ -11551,7 +11170,7 @@ parameters are a RESULT of the module parameters. --> @@ -11602,7 +11221,7 @@ parameters are a RESULT of the module parameters. --> @@ -11653,7 +11272,7 @@ parameters are a RESULT of the module parameters. --> @@ -11704,7 +11323,7 @@ parameters are a RESULT of the module parameters. --> @@ -11755,7 +11374,7 @@ parameters are a RESULT of the module parameters. --> @@ -11806,7 +11425,7 @@ parameters are a RESULT of the module parameters. --> @@ -11857,7 +11476,7 @@ parameters are a RESULT of the module parameters. --> @@ -11908,7 +11527,7 @@ parameters are a RESULT of the module parameters. --> @@ -11959,7 +11578,7 @@ parameters are a RESULT of the module parameters. --> @@ -12010,7 +11629,7 @@ parameters are a RESULT of the module parameters. --> @@ -12061,7 +11680,7 @@ parameters are a RESULT of the module parameters. --> @@ -12112,7 +11731,7 @@ parameters are a RESULT of the module parameters. --> @@ -12161,11 +11780,11 @@ parameters are a RESULT of the module parameters. --> s1 + end="onchip_memory2_0.s1"> int 1 @@ -12209,12 +11828,12 @@ parameters are a RESULT of the module parameters. --> pulpino_0 avalon_master_lsu onchip_memory2_0 - s2 + s1 @@ -12263,11 +11882,11 @@ parameters are a RESULT of the module parameters. --> avalon_slave_debug + end="onchip_memory2_0.s1"> int 1 @@ -12311,12 +11930,12 @@ parameters are a RESULT of the module parameters. --> master_0 master onchip_memory2_0 - s2 + s1 @@ -12343,7 +11962,7 @@ parameters are a RESULT of the module parameters. --> @@ -12370,7 +11989,7 @@ parameters are a RESULT of the module parameters. --> @@ -12397,7 +12016,7 @@ parameters are a RESULT of the module parameters. --> @@ -12424,7 +12043,7 @@ parameters are a RESULT of the module parameters. --> @@ -12451,7 +12070,7 @@ parameters are a RESULT of the module parameters. --> @@ -12478,7 +12097,7 @@ parameters are a RESULT of the module parameters. --> @@ -12505,7 +12124,7 @@ parameters are a RESULT of the module parameters. --> @@ -12532,7 +12151,7 @@ parameters are a RESULT of the module parameters. --> @@ -12559,7 +12178,7 @@ parameters are a RESULT of the module parameters. --> @@ -12586,7 +12205,7 @@ parameters are a RESULT of the module parameters. --> @@ -12613,7 +12232,7 @@ parameters are a RESULT of the module parameters. --> @@ -12640,7 +12259,7 @@ parameters are a RESULT of the module parameters. --> @@ -12667,7 +12286,7 @@ parameters are a RESULT of the module parameters. --> @@ -12694,7 +12313,7 @@ parameters are a RESULT of the module parameters. --> @@ -12729,7 +12348,7 @@ parameters are a RESULT of the module parameters. --> @@ -12764,7 +12383,7 @@ parameters are a RESULT of the module parameters. --> @@ -12799,7 +12418,7 @@ parameters are a RESULT of the module parameters. --> @@ -12834,7 +12453,7 @@ parameters are a RESULT of the module parameters. --> @@ -12869,7 +12488,7 @@ parameters are a RESULT of the module parameters. --> @@ -12896,7 +12515,7 @@ parameters are a RESULT of the module parameters. --> @@ -12923,7 +12542,7 @@ parameters are a RESULT of the module parameters. --> @@ -12950,7 +12569,7 @@ parameters are a RESULT of the module parameters. --> @@ -12977,7 +12596,7 @@ parameters are a RESULT of the module parameters. --> @@ -13004,7 +12623,7 @@ parameters are a RESULT of the module parameters. --> @@ -13031,7 +12650,7 @@ parameters are a RESULT of the module parameters. --> @@ -13058,7 +12677,7 @@ parameters are a RESULT of the module parameters. --> @@ -13085,7 +12704,7 @@ parameters are a RESULT of the module parameters. --> @@ -13112,7 +12731,7 @@ parameters are a RESULT of the module parameters. --> @@ -13139,7 +12758,7 @@ parameters are a RESULT of the module parameters. --> @@ -13166,7 +12785,7 @@ parameters are a RESULT of the module parameters. --> @@ -13193,7 +12812,7 @@ parameters are a RESULT of the module parameters. --> @@ -13220,7 +12839,7 @@ parameters are a RESULT of the module parameters. --> @@ -13250,7 +12869,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Clock Source - 21.1 + 23.1 1 @@ -13258,7 +12877,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Input - 21.1 + 23.1 1 @@ -13266,7 +12885,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Input - 21.1 + 23.1 1 @@ -13274,7 +12893,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Output - 21.1 + 23.1 1 @@ -13282,7 +12901,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output - 21.1 + 23.1 1 @@ -13290,15 +12909,15 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Serial Flash Controller II Intel FPGA IP - 21.1 + 23.1 - 15 + 14 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Slave - 21.1 + 23.1 5 @@ -13306,7 +12925,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Interrupt Sender - 21.1 + 23.1 14 @@ -13314,7 +12933,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Input - 21.1 + 23.1 14 @@ -13322,7 +12941,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Input - 21.1 + 23.1 1 @@ -13346,7 +12965,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Conduit - 21.1 + 23.1 1 @@ -13354,15 +12973,15 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule JTAG UART Intel FPGA IP - 21.1 + 23.1 1 - altera_jtag_avalon_master_mod + altera_jtag_avalon_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - JTAG to Avalon Master Bridge (customized) - 1.0 + JTAG to Avalon Master Bridge + 23.1 3 @@ -13370,7 +12989,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Master - 21.1 + 23.1 1 @@ -13378,7 +12997,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output - 21.1 + 23.1 1 @@ -13386,7 +13005,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule On-Chip Memory (RAM or ROM) Intel FPGA IP - 21.1 + 23.1 1 @@ -13402,7 +13021,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule PIO (Parallel I/O) Intel FPGA IP - 21.1 + 23.1 1 @@ -13426,7 +13045,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Interrupt Receiver - 21.1 + 23.1 1 @@ -13442,7 +13061,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Interval Timer Intel FPGA IP - 21.1 + 23.1 16 @@ -13450,7 +13069,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Avalon Memory Mapped Connection - 21.1 + 23.1 14 @@ -13458,7 +13077,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Clock Connection - 21.1 + 23.1 5 @@ -13466,7 +13085,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Interrupt Connection - 21.1 + 23.1 14 @@ -13474,8 +13093,8 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Reset Connection - 21.1 + 23.1 - 21.1 842 + 23.1 993