From b22365af2006b2695ca591e8b4c879baf47df66c Mon Sep 17 00:00:00 2001
From: marqs <mhiienka@niksula.hut.fi>
Date: Mon, 7 Oct 2019 23:20:44 +0300
Subject: [PATCH] add timeout to pll_reconfig and update postprocess pipeline
 diagram

---
 ip/pll_reconfig/pll_reconfig_top.sv | 12 +++++++-----
 rtl/scanconverter.v                 | 18 +++++++++---------
 sys.sopcinfo                        |  4 ++--
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/ip/pll_reconfig/pll_reconfig_top.sv b/ip/pll_reconfig/pll_reconfig_top.sv
index 3938a23..31e142a 100644
--- a/ip/pll_reconfig/pll_reconfig_top.sv
+++ b/ip/pll_reconfig/pll_reconfig_top.sv
@@ -56,7 +56,7 @@ reg [1:0] state;
 reg scan_shift;
 reg scandone_prev;
 reg configupdate_pre;
-reg [7:0] shift_ctr;
+reg [7:0] ctr;
 
 wire pll_reset = pll_config_status[0];
 wire start_update = pll_config_status[1];
@@ -141,7 +141,7 @@ begin
                     if (start_update) begin
                         pll_config_status[31] <= 1'b1;
                         scanclkena <= 1'b1;
-                        shift_ctr <= PLL_CONFIG_DATA_BITS;
+                        ctr <= PLL_CONFIG_DATA_BITS;
                         state <= STATE_SHIFT;
                     end else begin
                         pll_config_status[31] <= 1'b0;
@@ -150,19 +150,21 @@ begin
             STATE_SHIFT:
                 begin
                     scan_shift <= 1'b1;
-                    if (shift_ctr > 0) begin
-                        shift_ctr <= shift_ctr - 1'b1;
+                    if (ctr > 0) begin
+                        ctr <= ctr - 1'b1;
                     end else begin
                         scan_shift <= 1'b0;
                         scanclkena <= 1'b0;
                         configupdate_pre <= 1'b1;
+                        ctr <= 8'hff;
                         state <= STATE_WAITRESP;
                     end
                 end    
             STATE_WAITRESP:
                 begin
                     configupdate_pre <= 1'b0;
-                    if (scandone_prev) begin
+                    ctr <= ctr - 1'b1;
+                    if (scandone_prev | (ctr == 8'h0)) begin
                         areset_strobe <= 1'b1;
                         state <= STATE_IDLE;
                     end
diff --git a/rtl/scanconverter.v b/rtl/scanconverter.v
index cfb87f8..f111f00 100644
--- a/rtl/scanconverter.v
+++ b/rtl/scanconverter.v
@@ -549,15 +549,15 @@ linebuf linebuf_rgb (
 // RGB:                             2 cycles
 //
 // Pipeline structure
-// |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |  10   |  11   |
-// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
-// | LBUF  | LBUF  |       |       |       |       |       |       |       |       |       |
-// |       |       | RLPF  | RLPF  | RLPF  |       |       |       |       |       |       |
-// |       |       |       |   Y   |   Y   |       |       |       |       |       |       |
-// |       |       |       |       |       |  SLG  |  SLG  |  SLG  |  SLG  |  SLG  |       |
-// |       |       |       |       |       |       |       |       |       |       | MASK  |
-// |       |       |       |       |       |       |       |       |       |       | LTBOX |
-// |       |       |       |       |       |       |       |       |       |       | OSD   |
+// |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |  10   |  11   |  12   |
+// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
+// | RADDR |       |       |       |       |       |       |       |       |       |       |       |
+// |       | LBUF  | LBUF  |       |       |       |       |       |       |       |       |       |
+// |       |       |       | RLPF  | RLPF  | RLPF  |       |       |       |       |       |       |
+// |       |       |       |       |   Y   |   Y   |       |       |       |       |       |       |
+// |       |       |       |       |       |       |  SLG  |  SLG  |  SLG  |  SLG  |  SLG  |       |
+// |       |       |       |       |       |       |       |       |       |       |       | MASK  |
+// |       |       |       |       |       |       |       |       |       |       |       | LTBOX |
 integer pp_idx;
 always @(posedge pclk_act)
 begin
diff --git a/sys.sopcinfo b/sys.sopcinfo
index 7d2482f..d2f87b0 100644
--- a/sys.sopcinfo
+++ b/sys.sopcinfo
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
  <!-- Format version 17.1 590 (Future versions may contain additional information.) -->
- <!-- 2019.10.06.04:16:28 -->
+ <!-- 2019.10.07.23:17:08 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1570324587</value>
+  <value>1570479428</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>