diff --git a/software/sys_controller/tvp7002/tvp7002.c b/software/sys_controller/tvp7002/tvp7002.c
old mode 100755
new mode 100644
index 994bbe9..6c7fcdb
--- a/software/sys_controller/tvp7002/tvp7002.c
+++ b/software/sys_controller/tvp7002/tvp7002.c
@@ -167,6 +167,7 @@ void tvp_init()
 
     // Use HSYNC leading edge as fine clamp reference
     // Allows minimizing HSYNC window
+    // Does not work properly for some reason, but is not critical as reference is at most LEADEDGE+MVSWIDTH
     //tvp_writereg(TVP_OUTFORMAT, 0x0C);
 
     // Minimize HSYNC window for best sync stability
diff --git a/software/sys_controller/tvp7002/tvp7002.h b/software/sys_controller/tvp7002/tvp7002.h
old mode 100755
new mode 100644
diff --git a/software/sys_controller_bsp/settings.bsp b/software/sys_controller_bsp/settings.bsp
index 98b927d..723c6ed 100644
--- a/software/sys_controller_bsp/settings.bsp
+++ b/software/sys_controller_bsp/settings.bsp
@@ -2,9 +2,9 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>Aug 22, 2016 11:41:13 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1471898473341</BspGeneratedUnixTimeStamp>
-        <BspGeneratedLocation>/home/markus/Code/ossc/software/sys_controller_bsp</BspGeneratedLocation>
+        <BspGeneratedTimeStamp>Aug 23, 2016 7:19:50 PM</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1471969190153</BspGeneratedUnixTimeStamp>
+        <BspGeneratedLocation>./</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
         <JdiFile>default</JdiFile>