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osd_generator: add M9K support to allow larger character array
This commit is contained in:
marqs
parent
a6bdd8cfab
commit
d1fd30019f
@ -20,6 +20,15 @@ set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# parameters
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#
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add_parameter USE_MEMORY_BLOCKS INTEGER 1
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set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks for character array"
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set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
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set_parameter_property USE_MEMORY_BLOCKS UNITS None
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set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
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#
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# file sets
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#
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@ -17,7 +17,9 @@
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module osd_generator_top(
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module osd_generator_top #(
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parameter USE_MEMORY_BLOCKS = 0
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) (
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// common
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input clk_i,
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input rst_i,
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@ -45,13 +47,10 @@ localparam OSD_CONFIG_REGNUM = 4'h0;
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reg [31:0] osd_config;
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reg [7:0] char_ptr[CHAR_ROWS*CHAR_COLS-1:0], char_ptr_pp3[7:0] /* synthesis ramstyle = "logic" */;
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reg [10:0] xpos_scaled;
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reg [10:0] ypos_scaled;
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reg [7:0] x_ptr[2:5], y_ptr[2:5] /* synthesis ramstyle = "logic" */;
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reg osd_act_pp[2:5];
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reg [4:0] char_idx;
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reg [2:0] char_idx_lo;
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reg [14:0] to_ctr, to_ctr_ms;
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wire render_enable = osd_config[0];
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@ -63,11 +62,31 @@ wire [2:0] y_offset = osd_config[10:8];
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wire [1:0] x_size = osd_config[12:11];
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wire [1:0] y_size = osd_config[14:13];
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wire [7:0] rom_rdaddr = char_ptr_pp3[char_idx_lo];
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wire [7:0] rom_rdaddr;
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wire [0:7] char_data[7:0];
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wire [4:0] char_idx = CHAR_COLS*(ypos_scaled >> 3) + (xpos_scaled >> 3);
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assign avalon_s_waitrequest_n = 1'b1;
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generate
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if (USE_MEMORY_BLOCKS == 1) begin
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char_array char_array_inst (
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.byteena_a(avalon_s_byteenable),
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.data(avalon_s_writedata),
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.rdaddress(char_idx),
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.rdclock(vclk),
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.wraddress(avalon_s_address-1'b1),
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.wrclock(clk_i),
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.wren(avalon_s_chipselect && avalon_s_write && (avalon_s_address > 4'h0)),
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.q(rom_rdaddr)
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);
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end else begin
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reg [7:0] char_ptr[CHAR_ROWS*CHAR_COLS-1:0], char_ptr_pp3[7:0] /* synthesis ramstyle = "logic" */;
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reg [4:0] char_idx_pp[2:3];
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assign rom_rdaddr = char_ptr_pp3[char_idx_pp[3][2:0]];
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end
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endgenerate
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char_rom char_rom_inst (
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.clock(vclk),
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@ -76,12 +95,12 @@ char_rom char_rom_inst (
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);
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// Pipeline structure
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// | 1 | 2 | 3 | 4 | 5 | 6 |
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// |-------------|------------|-------------|---------|---------|------------|
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// | xpos_scaled | x_ptr | x_ptr | x_ptr | x_ptr | |
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// | ypos_scaled | y_ptr | y_ptr | y_ptr | y_ptr | |
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// | | osd_act | osd_act | osd_act | osd_act | osd_enable |
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// | | char_idx | char_idx_lo | CBUF | CBUF | osd_color |
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// | 1 | 2 | 3 | 4 | 5 | 6 |
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// |-------------|------------|----------|---------|---------|------------|
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// | xpos_scaled | x_ptr | x_ptr | x_ptr | x_ptr | |
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// | ypos_scaled | y_ptr | y_ptr | y_ptr | y_ptr | |
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// | | osd_act | osd_act | osd_act | osd_act | osd_enable |
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// | | char_idx | char_idx | CBUF | CBUF | osd_color |
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integer idx, pp_idx;
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always @(posedge vclk) begin
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xpos_scaled <= (xpos >> x_size)-({3'h0, x_offset} << 3);
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@ -94,13 +113,6 @@ always @(posedge vclk) begin
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y_ptr[pp_idx] <= y_ptr[pp_idx-1];
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end
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char_idx <= CHAR_COLS*(ypos_scaled >> 3) + (xpos_scaled >> 3);
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char_idx_lo <= char_idx[2:0];
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for(idx = 0; idx <= 7; idx = idx+1) begin
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char_ptr_pp3[idx] <= char_ptr[{char_idx[4:3], 3'(idx)}];
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end
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osd_act_pp[2] <= render_enable & (menu_active || (to_ctr_ms > 0)) & ((xpos_scaled < 8*CHAR_COLS) && (ypos_scaled < 8*CHAR_ROWS));
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for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin
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osd_act_pp[pp_idx] <= osd_act_pp[pp_idx-1];
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@ -110,6 +122,19 @@ always @(posedge vclk) begin
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osd_color = char_data[y_ptr[5]][x_ptr[5]];
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end
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generate
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if (USE_MEMORY_BLOCKS == 0) begin
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always @(posedge vclk) begin
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char_idx_pp[2] <= char_idx;
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char_idx_pp[3] <= char_idx_pp[2];
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for(idx = 0; idx <= 7; idx = idx+1) begin
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char_ptr_pp3[idx] <= char_ptr[{char_idx_pp[2][4:3], 3'(idx)}];
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end
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end
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end
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endgenerate
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// OSD status timeout counters
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always @(posedge clk_i)
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begin
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@ -155,23 +180,25 @@ end
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genvar i;
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generate
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for (i = 0; i < (CHAR_ROWS*CHAR_COLS); i = i + 4) begin : genreg
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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char_ptr[i] <= 0;
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char_ptr[i+1] <= 0;
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char_ptr[i+2] <= 0;
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char_ptr[i+3] <= 0;
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end else begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==1+(i/4))) begin
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if (avalon_s_byteenable[3])
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char_ptr[i+3] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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char_ptr[i+2] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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char_ptr[i+1] <= avalon_s_writedata[15:8];
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if (avalon_s_byteenable[0])
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char_ptr[i] <= avalon_s_writedata[7:0];
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if (USE_MEMORY_BLOCKS == 0) begin
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for (i = 0; i < (CHAR_ROWS*CHAR_COLS); i = i + 4) begin : genreg
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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char_ptr[i] <= 0;
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char_ptr[i+1] <= 0;
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char_ptr[i+2] <= 0;
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char_ptr[i+3] <= 0;
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end else begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==1+(i/4))) begin
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if (avalon_s_byteenable[3])
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char_ptr[i+3] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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char_ptr[i+2] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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char_ptr[i+1] <= avalon_s_writedata[15:8];
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if (avalon_s_byteenable[0])
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char_ptr[i] <= avalon_s_writedata[7:0];
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end
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end
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end
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end
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3
ossc.qsf
3
ossc.qsf
@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 1
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set_global_assignment -name SEED 2
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@ -247,4 +247,5 @@ set_global_assignment -name QIP_FILE rtl/mux5.qip
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set_global_assignment -name SDC_FILE ossc.sdc
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name QIP_FILE rtl/char_array.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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6
rtl/char_array.qip
Normal file
6
rtl/char_array.qip
Normal file
@ -0,0 +1,6 @@
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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_bb.v"]
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222
rtl/char_array.v
Normal file
222
rtl/char_array.v
Normal file
@ -0,0 +1,222 @@
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// megafunction wizard: %RAM: 2-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: char_array.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2017 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module char_array (
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byteena_a,
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data,
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rdaddress,
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rdclock,
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wraddress,
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wrclock,
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wren,
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q);
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input [3:0] byteena_a;
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input [31:0] data;
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input [9:0] rdaddress;
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input rdclock;
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input [7:0] wraddress;
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input wrclock;
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input wren;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 [3:0] byteena_a;
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tri1 wrclock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.byteena_a (byteena_a),
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.clock0 (wrclock),
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.clock1 (rdclock),
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.data_a (data),
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.wren_a (wren),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({8{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.byte_size = 8,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 256,
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altsyncram_component.numwords_b = 1024,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "CLOCK1",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.widthad_a = 8,
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altsyncram_component.widthad_b = 10,
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altsyncram_component.width_a = 32,
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altsyncram_component.width_b = 8,
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altsyncram_component.width_byteena_a = 4;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "1"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGq NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGrren NUMERIC "1"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
|
||||
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
|
||||
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
||||
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
|
||||
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
|
||||
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
|
||||
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
|
||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
|
||||
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
|
||||
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
12
sys.sopcinfo
12
sys.sopcinfo
@ -1,11 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
|
||||
<!-- 2019.10.03.23:37:09 -->
|
||||
<!-- 2019.10.05.03:41:15 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1570135029</value>
|
||||
<value>1570236075</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
@ -5944,6 +5944,14 @@ parameters are a RESULT of the module parameters. -->
|
||||
path="osd_generator_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="USE_MEMORY_BLOCKS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user